[coreboot-gerrit] New patch to review for coreboot: 4c8ae00 intel/sandybridge: Locate CBMEM TOC early in ramstage

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3513

-gerrit

commit 4c8ae00520bed65aa2eca7d8a069accfde983e0e
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jun 21 15:37:55 2013 +0300

    intel/sandybridge: Locate CBMEM TOC early in ramstage
    
    This patch allows the use of migrated CAR_GLOBAL variables from
    the very beginning of ramstage. Without the patch, CAR_GLOBALS were
    not available until northbridge set_resources().
    
    Change-Id: Ifd4ab2ed52e07dcbe8c77e2e460dc483323e93c0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/intel/sandybridge/northbridge.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 0a413b4..d8e2e9d 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -51,6 +51,21 @@ int bridge_silicon_revision(void)
 	return bridge_revision_id;
 }
 
+static unsigned long get_top_of_ram(void)
+{
+	/* Base of TSEG is top of usable DRAM */
+	u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG);
+	return (unsigned long) tom;
+}
+
+struct cbmem_entry *get_cbmem_toc(void)
+{
+	static struct cbmem_entry *toc = NULL;
+	if (!toc)
+		toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
+	return toc;
+}
+
 /* Reserve everything between A segment and 1MB:
  *
  * 0xa0000 - 0xbffff: legacy VGA