[coreboot-gerrit] Patch set updated for coreboot: 3071785 Drop some duplicates of PCI-e config functions

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Fri Jun 21 00:33:39 CEST 2013


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3502

-gerrit

commit 30717856261e86c2a6bcae6b02764c3e769b49a0
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Jun 19 23:05:00 2013 +0300

    Drop some duplicates of PCI-e config functions
    
    These are not specific to Intel. Further work needs to be done to
    combine these with MMCONF_SUPPORT in arch/io.h.
    
    Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/include/arch/pcie_config.h         | 89 +++++++++++++++++++++++++
 src/mainboard/google/stout/mainboard_smi.c      |  2 +-
 src/northbridge/intel/i945/early_init.c         |  2 +-
 src/northbridge/intel/i945/pcie_config.c        | 68 -------------------
 src/northbridge/intel/sandybridge/early_init.c  |  2 +-
 src/northbridge/intel/sandybridge/finalize.c    |  2 +-
 src/northbridge/intel/sandybridge/pcie_config.c | 89 -------------------------
 src/northbridge/intel/sch/pcie_config.c         | 66 ------------------
 src/southbridge/intel/bd82x6x/finalize.c        |  2 +-
 src/southbridge/intel/bd82x6x/me.c              |  2 +-
 src/southbridge/intel/bd82x6x/me_8.x.c          |  2 +-
 src/southbridge/intel/bd82x6x/smihandler.c      |  2 +-
 src/southbridge/intel/bd82x6x/spi.c             |  2 +-
 src/southbridge/intel/i82801dx/smihandler.c     |  6 --
 src/southbridge/intel/i82801gx/smihandler.c     |  2 +-
 src/southbridge/intel/sch/smihandler.c          |  7 --
 16 files changed, 99 insertions(+), 246 deletions(-)

diff --git a/src/arch/x86/include/arch/pcie_config.h b/src/arch/x86/include/arch/pcie_config.h
new file mode 100644
index 0000000..672457d
--- /dev/null
+++ b/src/arch/x86/include/arch/pcie_config.h
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
+
+static inline __attribute__ ((always_inline))
+u8 pcie_read_config8(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read8(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u16 pcie_read_config16(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read16(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u32 pcie_read_config32(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read32(addr);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config8(device_t dev, unsigned int where, u8 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write8(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config16(device_t dev, unsigned int where, u16 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write16(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config32(device_t dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write32(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
+{
+	u8 value = pcie_read_config8(dev, where);
+	pcie_write_config8(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
+{
+	u16 value = pcie_read_config16(dev, where);
+	pcie_write_config16(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
+{
+	u32 value = pcie_read_config32(dev, where);
+	pcie_write_config32(dev, where, value | ormask);
+}
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
index 7981046..3f7df82 100644
--- a/src/mainboard/google/stout/mainboard_smi.c
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -24,7 +24,7 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pcie_config.h>
 #include <cpu/intel/model_206ax/model_206ax.h>
 
 /* Include romstage serial for SIO helper functions */
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d91930f..97ef679 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,7 +23,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include "i945.h"
-#include "pcie_config.c"
+#include <arch/pcie_config.h>
 
 int i945_silicon_revision(void)
 {
diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c
deleted file mode 100644
index 0310d67..0000000
--- a/src/northbridge/intel/i945/pcie_config.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "i945.h"
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write32(addr, value);
-}
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index c2d4909..a1938b8 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -25,7 +25,7 @@
 #include <device/pci_def.h>
 #include <elog.h>
 #include "sandybridge.h"
-#include "pcie_config.c"
+#include <arch/pcie_config.h>
 
 static void sandybridge_setup_bars(void)
 {
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index 0fa8d1a..bafa736 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -20,7 +20,7 @@
 
 #include <arch/io.h>
 #include <stdlib.h>
-#include "pcie_config.c"
+#include <arch/pcie_config.h>
 #include "sandybridge.h"
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)
diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c
deleted file mode 100644
index 0677d76..0000000
--- a/src/northbridge/intel/sandybridge/pcie_config.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "sandybridge.h"
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write32(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
-{
-	u8 value = pcie_read_config8(dev, where);
-	pcie_write_config8(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
-{
-	u16 value = pcie_read_config16(dev, where);
-	pcie_write_config16(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
-{
-	u32 value = pcie_read_config32(dev, where);
-	pcie_write_config32(dev, where, value | ormask);
-}
diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c
deleted file mode 100644
index ad7d746..0000000
--- a/src/northbridge/intel/sch/pcie_config.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
-	write32(addr, value);
-}
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index bcc2f3d..1492278 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -20,7 +20,7 @@
 
 #include <arch/io.h>
 #include <console/post_codes.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pcie_config.h>
 #include "pch.h"
 #include <spi-generic.h>
 
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 7fdf926..5d4add9 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -38,7 +38,7 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pcie_config.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index f79adf5..4bc5506 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -38,7 +38,7 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pcie_config.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 5913115..be22a1b 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -37,7 +37,7 @@
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pcie_config.h>
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 09169b1..455f37c 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -34,7 +34,7 @@
 #define min(a, b) ((a)<(b)?(a):(b))
 
 #ifdef __SMM__
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pcie_config.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pcie_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 5470890..9b0c235 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-// #include "../../../northbridge/intel/i945/pcie_config.c"
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 2e29acd..1de1ec9 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -206,7 +206,7 @@ static void dump_tco_status(u32 tco_sts)
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
-#include "../../../northbridge/intel/i945/pcie_config.c"
+#include <arch/pcie_config.h>
 
 int southbridge_io_trap_handler(int smif)
 {
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c
index 2ccbc7f..5074138 100644
--- a/src/southbridge/intel/sch/smihandler.c
+++ b/src/southbridge/intel/sch/smihandler.c
@@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts)
 }
 #endif
 
-
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-//#include "../../../northbridge/intel/i945/pcie_config.c"
-
 int southbridge_io_trap_handler(int smif)
 {
 	//global_nvs_t *gnvs = (global_nvs_t *)0xc00;



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