[coreboot-gerrit] New patch to review for coreboot: a10b0e1 qemu: move ram ressource reservation from "set" to "read" stage

[Gerd Hoffmann (kraxel@redhat.com)]

Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3491

-gerrit

commit a10b0e1177af72b577f72704f682d6dbf996e19b
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Mon Jun 17 13:30:50 2013 +0200

    qemu: move ram ressource reservation from "set" to "read" stage
    
    So the pci allocation code knows where memory is and doesn't
    try map pci devices there.  We also don't have to check for
    overlaps between pci hole and memory then.
    
    Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
 src/mainboard/emulation/qemu-i440fx/northbridge.c | 34 ++++++++---------------
 1 file changed, 12 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index c2e4ba2..ed372b6 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -18,39 +18,29 @@
 
 static void cpu_pci_domain_set_resources(device_t dev)
 {
-	u32 pci_tolm = find_pci_tolm(dev->link_list);
-	unsigned long tomk = 0, tolmk;
-	int idx;
+	assign_resources(dev->link_list);
+}
+
+static void cpu_pci_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+	unsigned long tomk = 0;
+	int idx = 10;
+
+	pci_domain_read_resources(dev);
 
 	tomk = qemu_get_memory_size();
-	printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
-	       tomk, tomk / 1024);
-
-	/* Compute the top of Low memory */
-	tolmk = pci_tolm >> 10;
-	if (tolmk >= tomk) {
-		/* The PCI hole does not overlap the memory. */
-		tolmk = tomk;
-	}
+	printk(BIOS_DEBUG, "Detected %lu MiB RAM.\n", tomk / 1024);
 
 	/* Report the memory regions. */
 	idx = 10;
 	ram_resource(dev, idx++, 0, 640);
-	ram_resource(dev, idx++, 768, tolmk - 768);
+	ram_resource(dev, idx++, 768, tomk - 768);
 
 	/* Leave some space for ACPI, PIRQ and MP tables */
 	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
 	high_tables_size = HIGH_MEMORY_SIZE;
 
-	assign_resources(dev->link_list);
-}
-
-static void cpu_pci_domain_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	pci_domain_read_resources(dev);
-
 	/* Reserve space for the IOAPIC.  This should be in the Southbridge,
 	 * but I couldn't tell which device to put it in. */
 	res = new_resource(dev, 2);