[coreboot-gerrit] New patch to review for coreboot: 7325290 lynxpoint: Fix early EHCI BAR programming

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3472

-gerrit

commit 7325290197c8a484b28ec832675c92a924719bf3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 15 12:30:13 2013 +0300

    lynxpoint: Fix early EHCI BAR programming
    
    LynxPoint LP has only EHCI controller #1.
    Change EHCI #2 to different BAR from EHCI #1.
    
    Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/intel/lynxpoint/early_usb.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index ebd5c2c..d800eff 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -37,7 +37,9 @@
 void enable_usb_bar(void)
 {
 	device_t usb0 = PCH_EHCI1_DEV;
+#if !CONFIG_INTEL_LYNXPOINT_LP
 	device_t usb1 = PCH_EHCI2_DEV;
+#endif
 	u32 cmd;
 
 	/* USB Controller 1 */
@@ -47,10 +49,12 @@ void enable_usb_bar(void)
 	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 	pci_write_config32(usb0, PCI_COMMAND, cmd);
 
-	/* USB Controller 1 */
+	/* USB Controller 2 */
+#if !CONFIG_INTEL_LYNXPOINT_LP
 	pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
-			   PCH_EHCI1_TEMP_BAR0);
+			   PCH_EHCI2_TEMP_BAR0);
 	cmd = pci_read_config32(usb1, PCI_COMMAND);
 	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 	pci_write_config32(usb1, PCI_COMMAND, cmd);
+#endif
 }