[coreboot-gerrit] Patch set updated for coreboot: a75043f AMD sb800 agesa/hudson: Use PCI defines

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Fri Jun 14 18:32:48 CEST 2013


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3466

-gerrit

commit a75043f8e02e221bc85572ccfa277c002e9a911f
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jun 14 17:48:20 2013 +0300

    AMD sb800 agesa/hudson: Use PCI defines
    
    The original lines had contradicting comment and code.
    This change follows the code and sets MASTER bit too.
    
    Change-Id: Id2886bfc107612530f0e9747e5d49a9740fb8532
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 3 ++-
 src/southbridge/amd/sb800/enable_usbdebug.c        | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index c74ac9a..128885a 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -50,6 +50,7 @@ void enable_usbdebug(unsigned int port)
 
 	pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2),
 			   EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), 0x04, 0x6);	/* mem space enabe */
+	pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2),
+				PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 	set_debug_port(port);
 }
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index f085eab..28a1665 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -50,6 +50,7 @@ void enable_usbdebug(unsigned int port)
 
 	pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2),
 			   EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), 0x04, 0x6);	/* mem space enabe */
+	pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2),
+				PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 	set_debug_port(port);
 }



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