[coreboot-gerrit] Patch set updated for coreboot: 0a3f297 Support for nehalem northbridge.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Fri Jun 14 02:03:03 CEST 2013
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3454
-gerrit
commit 0a3f297812f709333d409049fd48dcb0aaaacc7d
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Thu Jun 13 22:05:16 2013 +0200
Support for nehalem northbridge.
Split out out of my X201 work.
Tested on X201.
Change-Id: I5ae7d2b4c3cab0026bcd4c642e7d3b56d54bae2c
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/northbridge/intel/Kconfig | 1 +
src/northbridge/intel/Makefile.inc | 1 +
src/northbridge/intel/nehalem/Kconfig | 84 +
src/northbridge/intel/nehalem/Makefile.inc | 35 +
src/northbridge/intel/nehalem/acpi.c | 195 +
src/northbridge/intel/nehalem/acpi/hostbridge.asl | 351 ++
src/northbridge/intel/nehalem/acpi/igd.asl | 342 ++
src/northbridge/intel/nehalem/acpi/nehalem.asl | 55 +
src/northbridge/intel/nehalem/chip.h | 42 +
src/northbridge/intel/nehalem/early_init.c | 169 +
src/northbridge/intel/nehalem/fake_vbios.c | 1797 +++++++
src/northbridge/intel/nehalem/finalize.c | 57 +
src/northbridge/intel/nehalem/gma.c | 1196 +++++
src/northbridge/intel/nehalem/gma.h | 168 +
src/northbridge/intel/nehalem/nehalem.h | 609 +++
src/northbridge/intel/nehalem/northbridge.c | 381 ++
src/northbridge/intel/nehalem/pcie_config.c | 89 +
src/northbridge/intel/nehalem/raminit.c | 5282 ++++++++++++++++++++
src/northbridge/intel/nehalem/raminit.h | 29 +
src/northbridge/intel/nehalem/raminit_fake.c | 2056 ++++++++
src/northbridge/intel/nehalem/raminit_tables.c | 1258 +++++
src/northbridge/intel/nehalem/udelay.c | 55 +
src/southbridge/intel/Kconfig | 1 +
src/southbridge/intel/Makefile.inc | 1 +
src/southbridge/intel/ibexpeak/Kconfig | 72 +
src/southbridge/intel/ibexpeak/Makefile.inc | 75 +
src/southbridge/intel/ibexpeak/acpi/audio.asl | 36 +
src/southbridge/intel/ibexpeak/acpi/globalnvs.asl | 301 ++
src/southbridge/intel/ibexpeak/acpi/irqlinks.asl | 493 ++
src/southbridge/intel/ibexpeak/acpi/lpc.asl | 248 +
src/southbridge/intel/ibexpeak/acpi/pch.asl | 280 ++
src/southbridge/intel/ibexpeak/acpi/pcie.asl | 218 +
src/southbridge/intel/ibexpeak/acpi/pcie_port.asl | 30 +
src/southbridge/intel/ibexpeak/acpi/sata.asl | 83 +
.../intel/ibexpeak/acpi/sleepstates.asl | 27 +
src/southbridge/intel/ibexpeak/acpi/smbus.asl | 242 +
src/southbridge/intel/ibexpeak/acpi/usb.asl | 160 +
src/southbridge/intel/ibexpeak/azalia.c | 372 ++
src/southbridge/intel/ibexpeak/bootblock.c | 98 +
src/southbridge/intel/ibexpeak/chip.h | 103 +
src/southbridge/intel/ibexpeak/early_me.c | 200 +
src/southbridge/intel/ibexpeak/early_smbus.c | 77 +
src/southbridge/intel/ibexpeak/early_usb.c | 65 +
src/southbridge/intel/ibexpeak/elog.c | 114 +
src/southbridge/intel/ibexpeak/finalize.c | 65 +
src/southbridge/intel/ibexpeak/gpio.c | 100 +
src/southbridge/intel/ibexpeak/gpio.h | 161 +
src/southbridge/intel/ibexpeak/lpc.c | 693 +++
src/southbridge/intel/ibexpeak/me.c | 658 +++
src/southbridge/intel/ibexpeak/me.h | 374 ++
src/southbridge/intel/ibexpeak/me_8.x.c | 935 ++++
src/southbridge/intel/ibexpeak/me_status.c | 213 +
src/southbridge/intel/ibexpeak/nvs.h | 160 +
src/southbridge/intel/ibexpeak/pch.c | 429 ++
src/southbridge/intel/ibexpeak/pch.h | 571 +++
src/southbridge/intel/ibexpeak/pci.c | 145 +
src/southbridge/intel/ibexpeak/pcie.c | 315 ++
src/southbridge/intel/ibexpeak/reset.c | 32 +
src/southbridge/intel/ibexpeak/sata.c | 300 ++
src/southbridge/intel/ibexpeak/smbus.c | 109 +
src/southbridge/intel/ibexpeak/smbus.h | 244 +
src/southbridge/intel/ibexpeak/smi.c | 415 ++
src/southbridge/intel/ibexpeak/smihandler.c | 849 ++++
src/southbridge/intel/ibexpeak/spi.c | 746 +++
src/southbridge/intel/ibexpeak/thermal.c | 85 +
src/southbridge/intel/ibexpeak/usb_debug.c | 60 +
src/southbridge/intel/ibexpeak/usb_ehci.c | 125 +
src/southbridge/intel/ibexpeak/watchdog.c | 59 +
68 files changed, 25391 insertions(+)
diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index a20f7b0..2a40c15 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -12,5 +12,6 @@ source src/northbridge/intel/i945/Kconfig
source src/northbridge/intel/gm45/Kconfig
source src/northbridge/intel/sch/Kconfig
source src/northbridge/intel/i5000/Kconfig
+source src/northbridge/intel/nehalem/Kconfig
source src/northbridge/intel/sandybridge/Kconfig
source src/northbridge/intel/haswell/Kconfig
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 62e427d..9156b99 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -12,6 +12,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
new file mode 100644
index 0000000..5b946cf
--- /dev/null
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -0,0 +1,84 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+## Copyright (C) 2013 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_NEHALEM
+ bool
+ select CACHE_MRC_BIN
+ select CPU_INTEL_MODEL_2065X
+ select VGA
+
+if NORTHBRIDGE_INTEL_NEHALEM
+
+config VGA_BIOS_ID
+ string
+ default "8086,0046"
+
+config CACHE_MRC_SIZE_KB
+ int
+ default 256
+
+# FIXME: build from rom size
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x500000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x10000
+
+config DCACHE_RAM_MRC_VAR_SIZE
+ hex
+ default 0x4000
+
+config MARK_GRAPHICS_MEM_WRCOMB
+ bool "Mark graphics memory as write-combining."
+ default n
+ help
+ The graphics performance may increase if the graphics
+ memory is set as write-combining cache type. This option
+ enables marking the graphics memory as write-combining.
+
+config CBFS_SIZE
+ hex "Size of CBFS filesystem in ROM"
+ default 0x100000
+ help
+ On Sandybridge and Ivybridge systems the firmware image has to
+ store a lot more than just coreboot, including:
+ - a firmware descriptor
+ - Intel Management Engine firmware
+ - MRC cache information
+ This option allows to limit the size of the CBFS portion in the
+ firmware image.
+
+endif
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
new file mode 100644
index 0000000..5e07b58
--- /dev/null
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -0,0 +1,35 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Google Inc.
+# Copyright (C) 2013 Vladimir Serbinenko
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ramstage-y += northbridge.c
+ramstage-y += gma.c
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+ramstage-y += ../sandybridge/mrccache.c
+
+romstage-y += raminit.c
+romstage-y += early_init.c
+romstage-y += ../sandybridge/mrccache.c
+romstage-y += ../../../arch/x86/lib/walkcbfs.S
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+$(obj)/northbridge/intel/nehalem/acpi.ramstage.o : $(obj)/build.h
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
new file mode 100644
index 0000000..ed85918
--- /dev/null
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <build.h>
+#include "nehalem.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ u32 pciexbar = 0;
+ u32 pciexbar_reg;
+ int max_buses;
+
+ pciexbar_reg = read32(0xeff01050);
+
+ // MMCFG not supported or not enabled.
+ if (!(pciexbar_reg & (1 << 0)))
+ return current;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: // 256MB
+ pciexbar =
+ pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28));
+ max_buses = 256;
+ break;
+ case 1: // 128M
+ pciexbar =
+ pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27));
+ max_buses = 128;
+ break;
+ case 2: // 64M
+ pciexbar =
+ pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27) | (1 << 26));
+ max_buses = 64;
+ break;
+ default: // RSVD
+ return current;
+ }
+
+ if (!pciexbar)
+ return current;
+
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+ pciexbar, 0x0, 0x0, max_buses - 1);
+
+ return current;
+}
+
+static void *get_intel_vbios(void)
+{
+ /* This should probably be looking at CBFS or we should always
+ * deploy the VBIOS on Intel systems, even if we don't run it
+ * in coreboot (e.g. SeaBIOS only scenarios).
+ */
+ u8 *vbios = (u8 *) 0xc0000;
+
+ optionrom_header_t *oprom = (optionrom_header_t *) vbios;
+ optionrom_pcir_t *pcir = (optionrom_pcir_t *) (vbios +
+ oprom->pcir_offset);
+
+ printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
+ oprom->signature, pcir->vendor, pcir->classcode[0],
+ pcir->classcode[1], pcir->classcode[2]);
+
+ if ((oprom->signature == OPROM_SIGNATURE) &&
+ (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
+ (pcir->classcode[0] == 0x00) &&
+ (pcir->classcode[1] == 0x00) && (pcir->classcode[2] == 0x03))
+ return (void *)vbios;
+
+ return NULL;
+}
+
+static int init_opregion_vbt(igd_opregion_t * opregion)
+{
+ void *vbios;
+ vbios = get_intel_vbios();
+ if (!vbios) {
+ printk(BIOS_DEBUG, "VBIOS not found.\n");
+ return 1;
+ }
+
+ printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
+ optionrom_header_t *oprom = (optionrom_header_t *) vbios;
+ optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
+
+ if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ printk(BIOS_DEBUG, "VBT not found!\n");
+ return 1;
+ }
+
+ memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
+ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
+ vbt->hdr_vbt_size : 7168);
+
+ return 0;
+}
+
+/* Initialize IGD OpRegion, called from ACPI code */
+int init_igd_opregion(igd_opregion_t * opregion)
+{
+ device_t igd;
+ u16 reg16;
+
+ memset((void *)opregion, 0, sizeof(igd_opregion_t));
+
+ // FIXME if IGD is disabled, we should exit here.
+
+ memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+ sizeof(IGD_OPREGION_SIGNATURE));
+
+ /* 8kb */
+ opregion->header.size = sizeof(igd_opregion_t) / 1024;
+ opregion->header.version = IGD_OPREGION_VERSION;
+
+ // FIXME We just assume we're mobile for now
+ opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+ // TODO Initialize Mailbox 1
+
+ // TODO Initialize Mailbox 3
+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+ opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+ init_opregion_vbt(opregion);
+
+ /* TODO This needs to happen in S3 resume, too.
+ * Maybe it should move to the finalize handler
+ */
+ igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+
+ pci_write_config32(igd, ASLS, (u32) opregion);
+ reg16 = pci_read_config16(igd, SWSCI);
+ reg16 &= ~(1 << 0);
+ reg16 |= (1 << 15);
+ pci_write_config16(igd, SWSCI, reg16);
+
+ /* clear dmisci status */
+ reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
+ reg16 |= DMISCI_STS; // reference code does an &=
+ outw(DEFAULT_PMBASE + TCO1_STS, reg16);
+
+ /* clear acpi tco status */
+ outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
+
+ /* enable acpi tco scis */
+ reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
+ reg16 |= TCOSCI_EN;
+ outw(DEFAULT_PMBASE + GPE0_EN, reg16);
+
+ return 0;
+}
diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl
new file mode 100644
index 0000000..3ab6838
--- /dev/null
+++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl
@@ -0,0 +1,351 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+Name(_HID,EISAID("PNP0A08")) // PCIe
+Name(_CID,EISAID("PNP0A03")) // PCI
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Device (MCHC)
+{
+ Name(_ADR, 0x00000000) // 0:0.0
+
+ OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
+ Field (MCHP, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40), // EPBAR
+ EPEN, 1, // Enable
+ , 11, //
+ EPBR, 24, // EPBAR
+
+ Offset (0x48), // MCHBAR
+ MHEN, 1, // Enable
+ , 13, //
+ MHBR, 22, // MCHBAR
+
+ Offset (0x60), // PCIe BAR
+ PXEN, 1, // Enable
+ PXSZ, 2, // BAR size
+ , 23, //
+ PXBR, 10, // PCIe BAR
+
+ Offset (0x68), // DMIBAR
+ DMEN, 1, // Enable
+ , 11, //
+ DMBR, 24, // DMIBAR
+
+
+ Offset (0xa0),
+ TOM, 16,
+ TUUD, 16,
+
+ Offset (0xb0), // Top of Low Used Memory
+ TLUD, 16,
+ }
+
+ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
+ Name (CTCC, 0) /* CTDP Current Selection */
+ Name (CTCN, 0) /* CTDP Nominal Select */
+ Name (CTCD, 1) /* CTDP Down Select */
+ Name (CTCU, 2) /* CTDP Up Select */
+
+ OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
+ Field (MCHB, DWordAcc, Lock, Preserve)
+ {
+ Offset (0x5930),
+ CTDN, 15, /* CTDP Nominal PL1 */
+ Offset (0x59a0),
+ PL1V, 15, /* Power Limit 1 Value */
+ PL1E, 1, /* Power Limit 1 Enable */
+ PL1C, 1, /* Power Limit 1 Clamp */
+ PL1T, 7, /* Power Limit 1 Time */
+ Offset (0x59a4),
+ PL2V, 15, /* Power Limit 2 Value */
+ PL2E, 1, /* Power Limit 2 Enable */
+ PL2C, 1, /* Power Limit 2 Clamp */
+ PL2T, 7, /* Power Limit 2 Time */
+ Offset (0x5f3c),
+ TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
+ Offset (0x5f40),
+ CTDD, 15, /* CTDP Down PL1 */
+ , 1,
+ TARD, 8, /* CTDP Down Turbo Activation Ratio */
+ Offset (0x5f48),
+ CTDU, 15, /* CTDP Up PL1 */
+ , 1,
+ TARU, 8, /* CTDP Up Turbo Activation Ratio */
+ Offset (0x5f50),
+ CTCS, 2, /* CTDP Select */
+ Offset (0x5f54),
+ TARS, 8, /* Turbo Activation Ratio Select */
+ }
+
+ /*
+ * Search CPU0 _PSS looking for control=arg0 and then
+ * return previous P-state entry number for new _PPC
+ *
+ * Format of _PSS:
+ * Name (_PSS, Package () {
+ * Package (6) { freq, power, tlat, blat, control, status }
+ * }
+ */
+ External (\_PR.CPU0._PSS)
+ Method (PSSS, 1, NotSerialized)
+ {
+ Store (One, Local0) /* Start at P1 */
+ Store (SizeOf (\_PR.CPU0._PSS), Local1)
+
+ While (LLess (Local0, Local1)) {
+ /* Store _PSS entry Control value to Local2 */
+ ShiftRight (DeRefOf (Index (DeRefOf (Index
+ (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2)
+ If (LEqual (Local2, Arg0)) {
+ Return (Subtract (Local0, 1))
+ }
+ Increment (Local0)
+ }
+
+ Return (0)
+ }
+
+ /* Set TDP Down */
+ Method (STND, 0, Serialized)
+ {
+ If (Acquire (CTCM, 100)) {
+ Return (0)
+ }
+ If (LEqual (CTCD, CTCC)) {
+ Release (CTCM)
+ Return (0)
+ }
+
+ Store ("Set TDP Down", Debug)
+
+ /* Set CTC */
+ Store (CTCD, CTCS)
+
+ /* Set TAR */
+ Store (TARD, TARS)
+
+ /* Set PPC limit and notify OS */
+ Store (PSSS (TARD), PPCM)
+ PPCN ()
+
+ /* Set PL2 to 1.25 * PL1 */
+ Divide (Multiply (CTDD, 125), 100, Local0, PL2V)
+
+ /* Set PL1 */
+ Store (CTDD, PL1V)
+
+ /* Store the new TDP Down setting */
+ Store (CTCD, CTCC)
+
+ Release (CTCM)
+ Return (1)
+ }
+
+ /* Set TDP Nominal from Down */
+ Method (STDN, 0, Serialized)
+ {
+ If (Acquire (CTCM, 100)) {
+ Return (0)
+ }
+ If (LEqual (CTCN, CTCC)) {
+ Release (CTCM)
+ Return (0)
+ }
+
+ Store ("Set TDP Nominal", Debug)
+
+ /* Set PL1 */
+ Store (CTDN, PL1V)
+
+ /* Set PL2 to 1.25 * PL1 */
+ Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
+
+ /* Set PPC limit and notify OS */
+ Store (PSSS (TARN), PPCM)
+ PPCN ()
+
+ /* Set TAR */
+ Store (TARN, TARS)
+
+ /* Set CTC */
+ Store (CTCN, CTCS)
+
+ /* Store the new TDP Nominal setting */
+ Store (CTCN, CTCC)
+
+ Release (CTCM)
+ Return (1)
+ }
+}
+
+// Current Resource Settings
+
+Method (_CRS, 0, Serialized)
+{
+ Name (MCRS, ResourceTemplate()
+ {
+ // Bus Numbers
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+ // IO Region 0
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+ // PCI Config Space
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ // IO Region 1
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+ // VGA memory (0xa0000-0xbffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000,,, ASEG)
+
+ // OPROM reserved (0xc0000-0xc3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000,,, OPR0)
+
+ // OPROM reserved (0xc4000-0xc7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000,,, OPR1)
+
+ // OPROM reserved (0xc8000-0xcbfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000,,, OPR2)
+
+ // OPROM reserved (0xcc000-0xcffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000,,, OPR3)
+
+ // OPROM reserved (0xd0000-0xd3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000,,, OPR4)
+
+ // OPROM reserved (0xd4000-0xd7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000,,, OPR5)
+
+ // OPROM reserved (0xd8000-0xdbfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000,,, OPR6)
+
+ // OPROM reserved (0xdc000-0xdffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000,,, OPR7)
+
+ // BIOS Extension (0xe0000-0xe3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000,,, ESG0)
+
+ // BIOS Extension (0xe4000-0xe7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000,,, ESG1)
+
+ // BIOS Extension (0xe8000-0xebfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000,,, ESG2)
+
+ // BIOS Extension (0xec000-0xeffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000,,, ESG3)
+
+ // System BIOS (0xf0000-0xfffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000,,, FSEG)
+
+ // PCI Memory Region (Top of memory-0xfebfffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
+ 0xfec00000,,, PM01)
+
+ // TPM Area (0xfed40000-0xfed44fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+ 0x00005000,,, TPMR)
+ })
+
+ // Find PCI resource area in MCRS
+ CreateDwordField(MCRS, PM01._MIN, PMIN)
+ CreateDwordField(MCRS, PM01._MAX, PMAX)
+ CreateDwordField(MCRS, PM01._LEN, PLEN)
+
+ // Fix up PCI memory region
+ // Start with Top of Lower Usable DRAM
+ Store (^MCHC.TLUD, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Store (^MCHC.TUUD, Local1)
+
+ // Check if ME base is equal
+ If (LEqual (Local0, Local1)) {
+ // Use Top Of Memory instead
+ Store (^MCHC.TOM, Local0)
+ ShiftRight (Local0, 6, Local0)
+ }
+
+ ShiftLeft (Local0, 20, Local0)
+ Store (Local0, PMIN)
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+ Return (MCRS)
+}
+
+/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
+#include "acpi/nehalem_pci_irqs.asl"
+
+
diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl
new file mode 100644
index 0000000..1b44059
--- /dev/null
+++ b/src/northbridge/intel/nehalem/acpi/igd.asl
@@ -0,0 +1,342 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (GFX0)
+{
+ Name (_ADR, 0x00020000)
+
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
+ }
+
+ /* Display Output Switching */
+ Method (_DOS, 1)
+ {
+ /* Windows 2000 and Windows XP call _DOS to enable/disable
+ * Display Output Switching during init and while a switch
+ * is already active
+ */
+ Store (And(Arg0, 7), DSEN)
+ }
+
+ /* We try to support as many i945 systems as possible,
+ * so keep the number of DIDs flexible.
+ */
+ Method (_DOD, 0)
+ {
+ If (LEqual(NDID, 1)) {
+ Name(DOD1, Package() {
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID1), Index(DOD1, 0))
+ Return(DOD1)
+ }
+
+ If (LEqual(NDID, 2)) {
+ Name(DOD2, Package() {
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID2), Index(DOD2, 0))
+ Store (Or(0x00010000, DID2), Index(DOD2, 1))
+ Return(DOD2)
+ }
+
+ If (LEqual(NDID, 3)) {
+ Name(DOD3, Package() {
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID3), Index(DOD3, 0))
+ Store (Or(0x00010000, DID3), Index(DOD3, 1))
+ Store (Or(0x00010000, DID3), Index(DOD3, 2))
+ Return(DOD3)
+ }
+
+ If (LEqual(NDID, 4)) {
+ Name(DOD4, Package() {
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID4), Index(DOD4, 0))
+ Store (Or(0x00010000, DID4), Index(DOD4, 1))
+ Store (Or(0x00010000, DID4), Index(DOD4, 2))
+ Store (Or(0x00010000, DID4), Index(DOD4, 3))
+ Return(DOD4)
+ }
+
+ If (LGreater(NDID, 4)) {
+ Name(DOD5, Package() {
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID5), Index(DOD5, 0))
+ Store (Or(0x00010000, DID5), Index(DOD5, 1))
+ Store (Or(0x00010000, DID5), Index(DOD5, 2))
+ Store (Or(0x00010000, DID5), Index(DOD5, 3))
+ Store (Or(0x00010000, DID5), Index(DOD5, 4))
+ Return(DOD5)
+ }
+
+ /* Some error happened, but we have to return something */
+ Return (Package() {0x00000400})
+ }
+
+ Device(DD01)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID1, 0)) {
+ Return (1)
+ } Else {
+ Return (And(0xffff, DID1))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 1)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 1)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+ Device(DD02)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID2, 0)) {
+ Return (2)
+ } Else {
+ Return (And(0xffff, DID2))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 2)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 2)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+
+ Device(DD03)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID3, 0)) {
+ Return (3)
+ } Else {
+ Return (And(0xffff, DID3))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 4)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 4)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+
+ Device(DD04)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID4, 0)) {
+ Return (4)
+ } Else {
+ Return (And(0xffff, DID4))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 8)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 4)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+
+ Device(DD05)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID5, 0)) {
+ Return (5)
+ } Else {
+ Return (And(0xffff, DID5))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 16)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 4)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+}
+
diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl
new file mode 100644
index 0000000..52c341f
--- /dev/null
+++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "../nehalem.h"
+#include "hostbridge.asl"
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, 1)
+
+ Name (PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+ Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+
+#if CONFIG_CHROMEOS_RAMOOPS
+ Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
+#endif
+ })
+
+ // Current Resource Settings
+ Method (_CRS, 0, Serialized)
+ {
+ Return(PDRS)
+ }
+}
+
+// Integrated graphics 0:2.0
+#include "igd.asl"
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h
new file mode 100644
index 0000000..3164035
--- /dev/null
+++ b/src/northbridge/intel/nehalem/chip.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Digital Port Hotplug Enable:
+ * 0x04 = Enabled, 2ms short pulse
+ * 0x05 = Enabled, 4.5ms short pulse
+ * 0x06 = Enabled, 6ms short pulse
+ * 0x07 = Enabled, 100ms short pulse
+ */
+struct northbridge_intel_nehalem_config {
+ u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
+ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
+ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
+
+ u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
+ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
+ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
+ u16 gpu_panel_power_down_delay; /* T3 time sequence */
+ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
+ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
+
+ u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
+ u32 gpu_pch_backlight; /* PCH Backlight PWM value */
+};
+
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
new file mode 100644
index 0000000..66cfabc
--- /dev/null
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <elog.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <arch/cpu.h>
+
+#include "nehalem.h"
+#include "pcie_config.c"
+
+static void nehalem_setup_bars(void)
+{
+ /* Setting up Southbridge. In the northbridge code. */
+ printk(BIOS_DEBUG, "Setting up static southbridge registers...");
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+
+ printk(BIOS_DEBUG, " done.\n");
+
+ printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
+ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+ outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); /* halt timer */
+ printk(BIOS_DEBUG, " done.\n");
+
+ printk(BIOS_DEBUG, "Setting up static northbridge registers...");
+ /* Set up all hardcoded northbridge BARs */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
+ (0LL + DEFAULT_EPBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
+ (0LL + DEFAULT_MCHBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4,
+ (0LL + DEFAULT_PCIEXBAR) >> 32);
+ pci_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1);
+
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
+ (0LL + DEFAULT_DMIBAR) >> 32);
+
+ /* Set C0000-FFFFF to access RAM on both reads and writes */
+ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
+ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33);
+ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33);
+ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33);
+ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33);
+ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
+ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
+
+#if CONFIG_ELOG_BOOT_COUNT
+ /* Increment Boot Counter for non-S3 resume */
+ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
+ ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
+ boot_count_increment();
+#endif
+
+ printk(BIOS_DEBUG, " done.\n");
+
+#if CONFIG_ELOG_BOOT_COUNT
+ /* Increment Boot Counter except when resuming from S3 */
+ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
+ ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
+ return;
+ boot_count_increment();
+#endif
+}
+
+static void early_cpu_init (void)
+{
+ msr_t m;
+
+ /* bit 0 = disable multicore,
+ bit 1 = disable quadcore,
+ bit 8 = disable hyperthreading. */
+ pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80,
+ (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000);
+
+ u8 reg8;
+ struct cpuid_result result;
+ result = cpuid_ext(0x6, 0x8b);
+ if (!(result.eax & 0x2)) {
+ m = rdmsr(MSR_FSB_CLOCK_VCC);
+ reg8 = ((m.lo & 0xff00) >> 8) + 1;
+ m = rdmsr (IA32_PERF_CTL);
+ m.lo = (m.lo & ~0xff) | reg8;
+ wrmsr(IA32_PERF_CTL, m);
+
+ m = rdmsr(MSR_IA32_MISC_ENABLES);
+ m.hi &= ~0x00000040;
+ m.lo |= 0x10000;
+
+ wrmsr(MSR_IA32_MISC_ENABLES, m);
+ }
+
+ m = rdmsr(MSR_FSB_CLOCK_VCC);
+ reg8 = ((m.lo & 0xff00) >> 8) + 1;
+
+ m = rdmsr (IA32_PERF_CTL);
+ m.lo = (m.lo & ~0xff) | reg8;
+ wrmsr(IA32_PERF_CTL, m);
+
+ m = rdmsr(MSR_IA32_MISC_ENABLES);
+ m.lo |= 0x10000;
+ wrmsr(MSR_IA32_MISC_ENABLES, m);
+
+ m = rdmsr(0x1f1);
+ m.lo |= 1;
+ wrmsr(0x1f1, m);
+
+}
+
+void nehalem_early_initialization(int chipset_type)
+{
+ u32 capid0_a;
+ u8 reg8;
+
+ /* Device ID Override Enable should be done very early */
+ capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
+ if (capid0_a & (1 << 10)) {
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
+ reg8 &= ~7; /* Clear 2:0 */
+
+ if (chipset_type == NEHALEM_MOBILE)
+ reg8 |= 1; /* Set bit 0 */
+
+ pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
+ }
+
+ /* Setup all BARs required for early PCIe and raminit */
+ nehalem_setup_bars();
+
+ /* Device Enable */
+ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, 9 | 2);
+
+ early_cpu_init();
+
+ pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR);
+ pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+}
diff --git a/src/northbridge/intel/nehalem/fake_vbios.c b/src/northbridge/intel/nehalem/fake_vbios.c
new file mode 100644
index 0000000..8b9f404
--- /dev/null
+++ b/src/northbridge/intel/nehalem/fake_vbios.c
@@ -0,0 +1,1797 @@
+my_outb(0x03c2, 0x23); // Device I/O <--
+my_outb(0x03da, 0x02); // Device I/O <--
+my_inb(0x03c2); // Device I/O --> 10
+my_outb(0x03da, 0x01); // Device I/O <--
+my_inb(0x03c2); // Device I/O --> 10
+my_outl(0x1040, 0x00070080); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00070180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00071180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00041000); // Device I/O
+my_inl(0x1044); // Device I/O --> 00002900
+my_outl(0x1044, 0x8000298e); // Device I/O
+my_outl(0x1040, 0x0007019c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0007119c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00000000); // Device I/O
+my_inl(0x1044); // Device I/O --> ffffffff
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00000000); // Device I/O
+my_inl(0x1044); // Device I/O --> ffffffff
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00000000); // Device I/O
+my_inl(0x1044); // Device I/O --> ffffffff
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00000000); // Device I/O
+my_inl(0x1044); // Device I/O --> ffffffff
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00000000); // Device I/O
+my_inl(0x1044); // Device I/O --> ffffffff
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x000fc008); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outl(0x1040, 0x000fc020); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outl(0x1040, 0x000fc038); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outl(0x1040, 0x000fc050); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outl(0x1040, 0x000fc408); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outl(0x1040, 0x000fc420); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outl(0x1040, 0x000fc438); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outl(0x1040, 0x000fc450); // Device I/O
+my_inl(0x1044); // Device I/O --> 2c010757
+my_outl(0x1044, 0x2c010000); // Device I/O
+my_outw(0x03ce, 0x0018); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x01000001); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f048); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x03030000); // Device I/O
+my_outl(0x1040, 0x0004f050); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000001); // Device I/O
+my_outl(0x1040, 0x0004f058); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1044, 0x03030000); // Device I/O
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1044, 0x03030000); // Device I/O
+my_outl(0x1040, 0x00042004); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x02000000); // Device I/O
+my_outl(0x1040, 0x000fd034); // Device I/O
+my_inl(0x1044); // Device I/O --> 39cfffe0
+my_outl(0x1044, 0x8421ffe0); // Device I/O
+int i;
+for (i = 0; i < 0x1fff; i++) {
+ my_outl(0x1040, 0x00000001 | (i << 2)); // Device I/O
+ my_outl(0x1044, 0xc2000001 | (i << 12)); // Device I/O
+}
+
+my_outw(0x03c4, 0x0302); // Device I/O
+my_outw(0x03c4, 0x0003); // Device I/O
+my_outw(0x03c4, 0x0204); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outw(0x03c4, 0x0300); // Device I/O
+my_outb(0x03c2, 0x67); // Device I/O <--
+my_outb(0x03d4, 0x11); // Device I/O <--
+my_inw(0x03d4); // Device I/O --> 0x0011
+my_outw(0x03d4, 0x0011); // Device I/O
+my_outw(0x03d4, 0x5f00); // Device I/O
+my_outw(0x03d4, 0x4f01); // Device I/O
+my_outw(0x03d4, 0x5002); // Device I/O
+my_outw(0x03d4, 0x8203); // Device I/O
+my_outw(0x03d4, 0x5504); // Device I/O
+my_outw(0x03d4, 0x8105); // Device I/O
+my_outw(0x03d4, 0xbf06); // Device I/O
+my_outw(0x03d4, 0x1f07); // Device I/O
+my_outw(0x03d4, 0x0008); // Device I/O
+my_outw(0x03d4, 0x4f09); // Device I/O
+my_outw(0x03d4, 0x0d0a); // Device I/O
+my_outw(0x03d4, 0x0e0b); // Device I/O
+my_outw(0x03d4, 0x000c); // Device I/O
+my_outw(0x03d4, 0x000d); // Device I/O
+my_outw(0x03d4, 0x000e); // Device I/O
+my_outw(0x03d4, 0x000f); // Device I/O
+my_outw(0x03d4, 0x9c10); // Device I/O
+my_outw(0x03d4, 0x8e11); // Device I/O
+my_outw(0x03d4, 0x8f12); // Device I/O
+my_outw(0x03d4, 0x2813); // Device I/O
+my_outw(0x03d4, 0x1f14); // Device I/O
+my_outw(0x03d4, 0x9615); // Device I/O
+my_outw(0x03d4, 0xb916); // Device I/O
+my_outw(0x03d4, 0xa317); // Device I/O
+my_outw(0x03d4, 0xff18); // Device I/O
+my_inb(0x03da); // Device I/O --> 31
+my_inb(0x03ba); // Device I/O --> ff
+my_inb(0x03da); // Device I/O --> 21
+my_inb(0x03ba); // Device I/O --> ff
+my_inb(0x03da); // Device I/O --> 01
+my_inb(0x03ba); // Device I/O --> ff
+my_outw(0x03ce, 0x0000); // Device I/O
+my_outw(0x03ce, 0x0001); // Device I/O
+my_outw(0x03ce, 0x0002); // Device I/O
+my_outw(0x03ce, 0x0003); // Device I/O
+my_outw(0x03ce, 0x0004); // Device I/O
+my_outw(0x03ce, 0x1005); // Device I/O
+my_outw(0x03ce, 0x0e06); // Device I/O
+my_outw(0x03ce, 0x0007); // Device I/O
+my_outw(0x03ce, 0xff08); // Device I/O
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00010000); // Device I/O
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00010000
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00010000
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x000e1100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000001
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000001
+my_outl(0x1044, 0x00000001); // Device I/O
+my_outl(0x1040, 0x000e4200); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000001c
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 00050000
+my_outl(0x1044, 0x8004003e); // Device I/O
+my_outl(0x1040, 0x000e4214); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x80060002); // Device I/O
+my_outl(0x1040, 0x000e4218); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x01000000); // Device I/O
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1044, 0x5344003e); // Device I/O
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 0144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 0144003e
+my_outl(0x1044, 0x8074003e); // Device I/O
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1044, 0x5344003e); // Device I/O
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 0144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 0144003e
+my_outl(0x1044, 0x8074003e); // Device I/O
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1044, 0x5344003e); // Device I/O
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 0144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 0144003e
+my_outl(0x1044, 0x8074003e); // Device I/O
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1040, 0x000e4210); // Device I/O
+my_inl(0x1044); // Device I/O --> 5144003e
+my_outl(0x1044, 0x5344003e); // Device I/O
+my_outl(0x1040, 0x000e4f00); // Device I/O
+my_inl(0x1044); // Device I/O --> 0100038e
+my_outl(0x1044, 0x0100030c); // Device I/O
+my_outl(0x1040, 0x000e4f04); // Device I/O
+my_inl(0x1044); // Device I/O --> 00b8338e
+my_outl(0x1044, 0x00b8230c); // Device I/O
+my_outl(0x1040, 0x000e4f08); // Device I/O
+my_inl(0x1044); // Device I/O --> 0178838e
+my_outl(0x1044, 0x06f8930c); // Device I/O
+my_outl(0x1040, 0x000e4f0c); // Device I/O
+my_inl(0x1044); // Device I/O --> 09f8e38e
+my_outl(0x1044, 0x09f8e38e); // Device I/O
+my_outl(0x1040, 0x000e4f10); // Device I/O
+my_inl(0x1044); // Device I/O --> 00b8038e
+my_outl(0x1044, 0x00b8030c); // Device I/O
+my_outl(0x1040, 0x000e4f14); // Device I/O
+my_inl(0x1044); // Device I/O --> 0978838e
+my_outl(0x1044, 0x0b78830c); // Device I/O
+my_outl(0x1040, 0x000e4f18); // Device I/O
+my_inl(0x1044); // Device I/O --> 09f8b38e
+my_outl(0x1044, 0x0ff8d3cf); // Device I/O
+my_outl(0x1040, 0x000e4f1c); // Device I/O
+my_inl(0x1044); // Device I/O --> 0178038e
+my_outl(0x1044, 0x01e8030c); // Device I/O
+my_outl(0x1040, 0x000e4f20); // Device I/O
+my_inl(0x1044); // Device I/O --> 09f8638e
+my_outl(0x1044, 0x0ff863cf); // Device I/O
+my_outl(0x1040, 0x000e4f24); // Device I/O
+my_inl(0x1044); // Device I/O --> 09f8038e
+my_outl(0x1044, 0x0ff803cf); // Device I/O
+my_outl(0x1040, 0x000c4030); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00001000); // Device I/O
+my_outl(0x1040, 0x000c4000); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000c4030); // Device I/O
+my_inl(0x1044); // Device I/O --> 00001000
+my_outl(0x1044, 0x00001000); // Device I/O
+my_outl(0x1040, 0x000e1150); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000001c
+my_outl(0x1040, 0x000e1150); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000001c
+my_outl(0x1044, 0x0000089c); // Device I/O
+my_outl(0x1040, 0x000fcc00); // Device I/O
+my_inl(0x1044); // Device I/O --> 01773f30
+my_outl(0x1044, 0x01986f00); // Device I/O
+my_outl(0x1040, 0x000fcc0c); // Device I/O
+my_inl(0x1044); // Device I/O --> 01773f30
+my_outl(0x1044, 0x01986f00); // Device I/O
+my_outl(0x1040, 0x000fcc18); // Device I/O
+my_inl(0x1044); // Device I/O --> 01773f30
+my_outl(0x1044, 0x01986f00); // Device I/O
+my_outl(0x1040, 0x000fcc24); // Device I/O
+my_inl(0x1044); // Device I/O --> 01773f30
+my_outl(0x1044, 0x01986f00); // Device I/O
+my_outl(0x1040, 0x000c4000); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 40000002
+my_inb(0x03d4); // Device I/O --> 18
+my_inb(0x03d6); // Device I/O --> ff
+my_inb(0x03d0); // Device I/O --> ff
+my_inb(0x03ce); // Device I/O --> 08
+my_inb(0x03d2); // Device I/O --> ff
+my_inb(0x03c4); // Device I/O --> 00
+my_inb(0x03c7); // Device I/O --> 00
+my_inb(0x03c8); // Device I/O --> 00
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outw(0x03c4, 0x2001); // Device I/O
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000800
+my_outl(0x1040, 0x000c5100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000003); // Device I/O
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008800
+my_outl(0x1040, 0x000c5120); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x000c5104); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x460000a0); // Device I/O
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000ca00
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000ca00
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000ca00
+my_outl(0x1040, 0x000c5120); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x000c5104); // Device I/O
+my_inl(0x1044); // Device I/O --> 060000a0
+my_outl(0x1044, 0x4a8000a1); // Device I/O
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a08
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a08
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> ffffff00
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a0c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a0c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00ffffff
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a10
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a10
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 4011ae30
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a14
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a14
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a18
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a18
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03011300
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a1c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a1c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 78101a80
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a20
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a20
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 9795baea
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a24
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a24
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 278c5559
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a28
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a28
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00545021
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a2c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a2c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 01010000
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a30
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a30
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 01010101
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a34
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a34
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 01010101
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a38
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a38
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 01010101
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a3c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a3c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 1b120101
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a40
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a40
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 20508000
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a44
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a44
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 20183014
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a48
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a48
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> a3050044
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a4c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a4c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 1f000010
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a50
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a50
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 80001693
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a54
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a54
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 30142050
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a58
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a58
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00442018
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a5c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a5c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 0010a305
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a60
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a60
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00001f00
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a64
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a64
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 81000f00
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a68
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a68
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 0a813c0a
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a6c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a6c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00091632
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a70
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a70
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 01f0e430
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a74
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a74
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> fe000000
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a78
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a78
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 31504c00
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a7c
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008a7c
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 58573132
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008800
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008800
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> 4c542d33
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008800
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008800
+my_outl(0x1040, 0x000c510c); // Device I/O
+my_inl(0x1044); // Device I/O --> ac003143
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008000
+my_outl(0x1040, 0x000c5104); // Device I/O
+my_inl(0x1044); // Device I/O --> 028000a1
+my_outl(0x1044, 0x480000a0); // Device I/O
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008000
+my_outl(0x1040, 0x000c5100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000003
+my_outl(0x1044, 0x48000000); // Device I/O
+my_outl(0x1040, 0x000c5108); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008000
+my_outl(0x1044, 0x00008000); // Device I/O
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outw(0x03c4, 0x0001); // Device I/O
+my_outb(0x03d4, 0x18); // Device I/O <--
+my_outb(0x03d6, 0xff); // Device I/O <--
+my_outb(0x03d0, 0xff); // Device I/O <--
+my_outb(0x03ce, 0x08); // Device I/O <--
+my_outb(0x03d2, 0xff); // Device I/O <--
+my_outb(0x03c4, 0x00); // Device I/O <--
+my_outb(0x03c8, 0x00); // Device I/O <--
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 40000002
+my_outl(0x1044, 0x00000300); // Device I/O
+my_outl(0x1040, 0x000c7208); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00fa09c4); // Device I/O
+my_outl(0x1040, 0x000c720c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00fa09c4); // Device I/O
+my_outl(0x1040, 0x000c7210); // Device I/O
+my_inl(0x1044); // Device I/O --> 00186904
+my_outl(0x1044, 0x00186903); // Device I/O
+my_outl(0x1040, 0x00048250); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x80000000); // Device I/O
+my_outl(0x1040, 0x00048254); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x061a061a); // Device I/O
+my_outl(0x1040, 0x000c8254); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x061a061a); // Device I/O
+my_outl(0x1040, 0x000c8250); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x000c8250); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x80000000); // Device I/O
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000c4000); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000001
+my_outl(0x1044, 0x0000020d); // Device I/O
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000020d
+my_outl(0x1040, 0x0004f050); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f050); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000020d
+my_outl(0x1044, 0x0000020d); // Device I/O
+my_outl(0x1040, 0x0004f050); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0xc0000000); // Device I/O
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000020d
+my_outl(0x1040, 0x0004f054); // Device I/O
+my_inl(0x1044); // Device I/O --> 0000020d
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000400); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000400
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000400
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c6, 0xff); // Device I/O <--
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1044, 0x03300000); // Device I/O
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03300000
+my_outl(0x1044, 0x30300000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 30300000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 30300000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 30300000
+my_outl(0x1040, 0x0004f048); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 30300000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 30300000
+my_outl(0x1044, 0x30030000); // Device I/O
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 30030000
+my_outl(0x1044, 0x03030000); // Device I/O
+
+vga_textmode_init();
+
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000001
+my_outl(0x1044, 0x01000008); // Device I/O
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1044, 0x03030000); // Device I/O
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1044, 0x03030000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00070080); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000700c0); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x0001
+my_outw(0x03c4, 0x2001); // Device I/O
+my_outl(0x1040, 0x00041000); // Device I/O
+my_inl(0x1044); // Device I/O --> 8000298e
+my_outl(0x1040, 0x00041000); // Device I/O
+my_inl(0x1044); // Device I/O --> 8000298e
+my_outl(0x1044, 0x8000298e); // Device I/O
+my_outl(0x1040, 0x00070180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00071180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00068070); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00068080); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00068074); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000400); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000400
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000400
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00041000); // Device I/O
+my_inl(0x1044); // Device I/O --> 8000298e
+my_outl(0x1044, 0x8020298e); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outw(0x03ce, 0x0010); // Device I/O
+my_outw(0x03ce, 0x0011); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outw(0x03c4, 0x0100); // Device I/O
+my_outw(0x03c4, 0x2001); // Device I/O
+my_outw(0x03c4, 0x0302); // Device I/O
+my_outw(0x03c4, 0x0003); // Device I/O
+my_outw(0x03c4, 0x0204); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outw(0x03c4, 0x0300); // Device I/O
+my_outb(0x03c2, 0x67); // Device I/O <--
+my_outb(0x03d4, 0x11); // Device I/O <--
+my_inw(0x03d4); // Device I/O --> 0x8e11
+my_outw(0x03d4, 0x0e11); // Device I/O
+my_outw(0x03d4, 0x5f00); // Device I/O
+my_outw(0x03d4, 0x4f01); // Device I/O
+my_outw(0x03d4, 0x5002); // Device I/O
+my_outw(0x03d4, 0x8203); // Device I/O
+my_outw(0x03d4, 0x5504); // Device I/O
+my_outw(0x03d4, 0x8105); // Device I/O
+my_outw(0x03d4, 0xbf06); // Device I/O
+my_outw(0x03d4, 0x1f07); // Device I/O
+my_outw(0x03d4, 0x0008); // Device I/O
+my_outw(0x03d4, 0x4f09); // Device I/O
+my_outw(0x03d4, 0x0d0a); // Device I/O
+my_outw(0x03d4, 0x0e0b); // Device I/O
+my_outw(0x03d4, 0x000c); // Device I/O
+my_outw(0x03d4, 0x000d); // Device I/O
+my_outw(0x03d4, 0x000e); // Device I/O
+my_outw(0x03d4, 0x000f); // Device I/O
+my_outw(0x03d4, 0x9c10); // Device I/O
+my_outw(0x03d4, 0x8e11); // Device I/O
+my_outw(0x03d4, 0x8f12); // Device I/O
+my_outw(0x03d4, 0x2813); // Device I/O
+my_outw(0x03d4, 0x1f14); // Device I/O
+my_outw(0x03d4, 0x9615); // Device I/O
+my_outw(0x03d4, 0xb916); // Device I/O
+my_outw(0x03d4, 0xa317); // Device I/O
+my_outw(0x03d4, 0xff18); // Device I/O
+my_inb(0x03da); // Device I/O --> 01
+my_inb(0x03ba); // Device I/O --> ff
+my_inb(0x03da); // Device I/O --> 21
+my_inb(0x03ba); // Device I/O --> ff
+my_inb(0x03da); // Device I/O --> 01
+my_inb(0x03ba); // Device I/O --> ff
+my_outw(0x03ce, 0x0000); // Device I/O
+my_outw(0x03ce, 0x0001); // Device I/O
+my_outw(0x03ce, 0x0002); // Device I/O
+my_outw(0x03ce, 0x0003); // Device I/O
+my_outw(0x03ce, 0x0004); // Device I/O
+my_outw(0x03ce, 0x1005); // Device I/O
+my_outw(0x03ce, 0x0e06); // Device I/O
+my_outw(0x03ce, 0x0007); // Device I/O
+my_outw(0x03ce, 0xff08); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c6, 0xff); // Device I/O <--
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+vga_textmode_init();
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f050); // Device I/O
+my_inl(0x1044); // Device I/O --> c0000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03ce, 0x06); // Device I/O <--
+my_inw(0x03ce); // Device I/O --> 0x0e06
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00041000); // Device I/O
+my_inl(0x1044); // Device I/O --> 8020298e
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000302
+my_outl(0x1044, 0x00008302); // Device I/O
+my_outl(0x1040, 0x00048250); // Device I/O
+my_inl(0x1044); // Device I/O --> 80000000
+my_outl(0x1044, 0x80000000); // Device I/O
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008302
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008302
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008302
+my_outl(0x1040, 0x000c6200); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00001000); // Device I/O
+my_outl(0x1040, 0x000c6200); // Device I/O
+my_inl(0x1044); // Device I/O --> 00001000
+my_outl(0x1044, 0x00001002); // Device I/O
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0xabcd0000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f00c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000c6040); // Device I/O
+my_inl(0x1044); // Device I/O --> 00030d07
+my_outl(0x1044, 0x00021005); // Device I/O
+my_outl(0x1040, 0x000c6014); // Device I/O
+my_inl(0x1044); // Device I/O --> 04800080
+my_outl(0x1044, 0x88046004); // Device I/O
+my_outl(0x1040, 0x000c6014); // Device I/O
+my_inl(0x1044); // Device I/O --> 88046004
+my_outl(0x1044, 0x88046004); // Device I/O
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> abcd0000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008302
+my_outl(0x1044, 0x00008302); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060000); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x057f04ff); // Device I/O
+my_outl(0x1040, 0x00060004); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x057f04ff); // Device I/O
+my_outl(0x1040, 0x00060008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x05370517); // Device I/O
+my_outl(0x1040, 0x0006000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x0333031f); // Device I/O
+my_outl(0x1040, 0x00060010); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x0333031f); // Device I/O
+my_outl(0x1040, 0x00060014); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x03270323); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outl(0x1040, 0x0006001c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x02cf018f); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00070008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f050); // Device I/O
+my_inl(0x1044); // Device I/O --> c0000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03ce, 0x06); // Device I/O <--
+my_inw(0x03ce); // Device I/O --> 0x0e06
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outb(0x03c4, 0x01); // Device I/O <--
+my_inw(0x03c4); // Device I/O --> 0x2001
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0006001c); // Device I/O
+my_inl(0x1044); // Device I/O --> 02cf018f
+my_outl(0x1044, 0x027f018f); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00068080); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x80800000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00068070); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00068074); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x05000320); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00070008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00070008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060030); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x7e127ae1); // Device I/O
+my_outl(0x1040, 0x00060034); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00800000); // Device I/O
+my_outl(0x1040, 0x00060040); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00020da7); // Device I/O
+my_outl(0x1040, 0x00060044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00080000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000040
+my_outl(0x1044, 0x00002040); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00002040
+my_outl(0x1044, 0x00002050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00044000
+my_outl(0x1044, 0x00044000); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00070008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000040); // Device I/O
+my_outl(0x1040, 0x000f0008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000040); // Device I/O
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00002050
+my_outl(0x1044, 0x00022050); // Device I/O
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00070008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000040
+my_outl(0x1044, 0x00000050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00070008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000050
+my_outl(0x1044, 0x80000050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x00041000); // Device I/O
+my_inl(0x1044); // Device I/O --> 8020298e
+my_outl(0x1044, 0x0020298e); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000080); // Device I/O
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f0018); // Device I/O
+my_inl(0x1044); // Device I/O --> 000007ff
+my_outl(0x1044, 0x000000ff); // Device I/O
+my_outl(0x1040, 0x000f1018); // Device I/O
+my_inl(0x1044); // Device I/O --> 000007ff
+my_outl(0x1044, 0x000000ff); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00022050
+my_outl(0x1044, 0x001a2050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060100); // Device I/O
+my_inl(0x1044); // Device I/O --> 00044000
+my_outl(0x1044, 0x001c4000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060100); // Device I/O
+my_inl(0x1044); // Device I/O --> 001c4000
+my_outl(0x1044, 0x801c4000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 001a2050
+my_outl(0x1044, 0x801a2050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060100); // Device I/O
+my_inl(0x1044); // Device I/O --> 801c4000
+my_outl(0x1044, 0x801c4000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 801a2050
+my_outl(0x1044, 0x801a2050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f0014); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000100
+my_outl(0x1040, 0x000f0014); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000100
+my_outl(0x1044, 0x00000100); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060100); // Device I/O
+my_inl(0x1044); // Device I/O --> 801c4000
+my_outl(0x1044, 0x901c4000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 801a2050
+my_outl(0x1044, 0x901a2050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f0014); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000600
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000e0000); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x057f04ff); // Device I/O
+my_outl(0x1040, 0x000e0004); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x057f04ff); // Device I/O
+my_outl(0x1040, 0x000e0008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x05370517); // Device I/O
+my_outl(0x1040, 0x000e000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x0333031f); // Device I/O
+my_outl(0x1040, 0x000e0010); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x0333031f); // Device I/O
+my_outl(0x1040, 0x000e0014); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x03270323); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00060100); // Device I/O
+my_inl(0x1044); // Device I/O --> 901c4000
+my_outl(0x1044, 0xb01c4000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f000c); // Device I/O
+my_inl(0x1044); // Device I/O --> 901a2050
+my_outl(0x1044, 0xb01a2050); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000f0008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000040
+my_outl(0x1044, 0x80000040); // Device I/O
+my_outl(0x1040, 0x000e1180); // Device I/O
+my_inl(0x1044); // Device I/O --> 00008302
+my_outl(0x1044, 0x80008302); // Device I/O
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0xabcd0000); // Device I/O
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> abcd0000
+my_outl(0x1044, 0xabcd0002); // Device I/O
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> abcd0002
+my_outl(0x1044, 0xabcd0003); // Device I/O
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d000000a
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> d0000009
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> c0000008
+my_outl(0x1040, 0x000c7200); // Device I/O
+my_inl(0x1044); // Device I/O --> c0000008
+my_outl(0x1040, 0x000c7204); // Device I/O
+my_inl(0x1044); // Device I/O --> abcd0003
+my_outl(0x1044, 0x00000003); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f040); // Device I/O
+my_inl(0x1044); // Device I/O --> 01000008
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000400); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000400
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000400
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x0004f044); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x0004f04c); // Device I/O
+my_inl(0x1044); // Device I/O --> 03030000
+my_outl(0x1040, 0x000c4030); // Device I/O
+my_inl(0x1044); // Device I/O --> 00001000
+my_outl(0x1040, 0x000c4030); // Device I/O
+my_inl(0x1044); // Device I/O --> 00001000
+my_outl(0x1044, 0x00001000); // Device I/O
+my_outl(0x1040, 0x000c4008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x000c4008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x000c4008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1040, 0x00044008); // Device I/O
+my_inl(0x1044); // Device I/O --> 00000000
+my_outl(0x1044, 0x00000000); // Device I/O
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c
new file mode 100644
index 0000000..26d89a1
--- /dev/null
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <stdlib.h>
+#include "pcie_config.c"
+#include "nehalem.h"
+
+#define NORTHBRIDGE PCI_DEV(0, 0, 0)
+
+void intel_nehalem_finalize_smm(void)
+{
+ pcie_or_config16(NORTHBRIDGE, 0x50, 1 << 0); /* GGC */
+ pcie_or_config32(NORTHBRIDGE, 0x5c, 1 << 0); /* DPR */
+ pcie_or_config32(NORTHBRIDGE, 0x78, 1 << 10); /* ME */
+ pcie_or_config32(NORTHBRIDGE, 0x90, 1 << 0); /* REMAPBASE */
+ pcie_or_config32(NORTHBRIDGE, 0x98, 1 << 0); /* REMAPLIMIT */
+ pcie_or_config32(NORTHBRIDGE, 0xa0, 1 << 0); /* TOM */
+ pcie_or_config32(NORTHBRIDGE, 0xa8, 1 << 0); /* TOUUD */
+ pcie_or_config32(NORTHBRIDGE, 0xb0, 1 << 0); /* BDSM */
+ pcie_or_config32(NORTHBRIDGE, 0xb4, 1 << 0); /* BGSM */
+ pcie_or_config32(NORTHBRIDGE, 0xb8, 1 << 0); /* TSEGMB */
+ pcie_or_config32(NORTHBRIDGE, 0xbc, 1 << 0); /* TOLUD */
+
+ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
+ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
+ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
+ MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
+ MCHBAR32_OR(0x6800, 1 << 31);
+ MCHBAR32_OR(0x7000, 1 << 31);
+ MCHBAR32_OR(0x77fc, 1 << 0);
+
+ /* Memory Controller Lockdown */
+ MCHBAR8(0x50fc) = 0x8f;
+
+ /* Read+write the following */
+ MCHBAR32(0x6030) = MCHBAR32(0x6030);
+ MCHBAR32(0x6034) = MCHBAR32(0x6034);
+ MCHBAR32(0x6008) = MCHBAR32(0x6008);
+}
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
new file mode 100644
index 0000000..2924ac5
--- /dev/null
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -0,0 +1,1196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+#include "chip.h"
+#include "nehalem.h"
+
+struct gt_powermeter {
+ u16 reg;
+ u32 value;
+};
+
+static const struct gt_powermeter snb_pm_gt1[] = {
+ {0xa200, 0xcc000000},
+ {0xa204, 0x07000040},
+ {0xa208, 0x0000fe00},
+ {0xa20c, 0x00000000},
+ {0xa210, 0x17000000},
+ {0xa214, 0x00000021},
+ {0xa218, 0x0817fe19},
+ {0xa21c, 0x00000000},
+ {0xa220, 0x00000000},
+ {0xa224, 0xcc000000},
+ {0xa228, 0x07000040},
+ {0xa22c, 0x0000fe00},
+ {0xa230, 0x00000000},
+ {0xa234, 0x17000000},
+ {0xa238, 0x00000021},
+ {0xa23c, 0x0817fe19},
+ {0xa240, 0x00000000},
+ {0xa244, 0x00000000},
+ {0xa248, 0x8000421e},
+ {0}
+};
+
+static const struct gt_powermeter snb_pm_gt2[] = {
+ {0xa200, 0x330000a6},
+ {0xa204, 0x402d0031},
+ {0xa208, 0x00165f83},
+ {0xa20c, 0xf1000000},
+ {0xa210, 0x00000000},
+ {0xa214, 0x00160016},
+ {0xa218, 0x002a002b},
+ {0xa21c, 0x00000000},
+ {0xa220, 0x00000000},
+ {0xa224, 0x330000a6},
+ {0xa228, 0x402d0031},
+ {0xa22c, 0x00165f83},
+ {0xa230, 0xf1000000},
+ {0xa234, 0x00000000},
+ {0xa238, 0x00160016},
+ {0xa23c, 0x002a002b},
+ {0xa240, 0x00000000},
+ {0xa244, 0x00000000},
+ {0xa248, 0x8000421e},
+ {0}
+};
+
+static const struct gt_powermeter ivb_pm_gt1[] = {
+ {0xa800, 0x00000000},
+ {0xa804, 0x00021c00},
+ {0xa808, 0x00000403},
+ {0xa80c, 0x02001700},
+ {0xa810, 0x05000200},
+ {0xa814, 0x00000000},
+ {0xa818, 0x00690500},
+ {0xa81c, 0x0000007f},
+ {0xa820, 0x01002501},
+ {0xa824, 0x00000300},
+ {0xa828, 0x01000331},
+ {0xa82c, 0x0000000c},
+ {0xa830, 0x00010016},
+ {0xa834, 0x01100101},
+ {0xa838, 0x00010103},
+ {0xa83c, 0x00041300},
+ {0xa840, 0x00000b30},
+ {0xa844, 0x00000000},
+ {0xa848, 0x7f000000},
+ {0xa84c, 0x05000008},
+ {0xa850, 0x00000001},
+ {0xa854, 0x00000004},
+ {0xa858, 0x00000007},
+ {0xa85c, 0x00000000},
+ {0xa860, 0x00010000},
+ {0xa248, 0x0000221e},
+ {0xa900, 0x00000000},
+ {0xa904, 0x00001c00},
+ {0xa908, 0x00000000},
+ {0xa90c, 0x06000000},
+ {0xa910, 0x09000200},
+ {0xa914, 0x00000000},
+ {0xa918, 0x00590000},
+ {0xa91c, 0x00000000},
+ {0xa920, 0x04002501},
+ {0xa924, 0x00000100},
+ {0xa928, 0x03000410},
+ {0xa92c, 0x00000000},
+ {0xa930, 0x00020000},
+ {0xa934, 0x02070106},
+ {0xa938, 0x00010100},
+ {0xa93c, 0x00401c00},
+ {0xa940, 0x00000000},
+ {0xa944, 0x00000000},
+ {0xa948, 0x10000e00},
+ {0xa94c, 0x02000004},
+ {0xa950, 0x00000001},
+ {0xa954, 0x00000004},
+ {0xa960, 0x00060000},
+ {0xaa3c, 0x00001c00},
+ {0xaa54, 0x00000004},
+ {0xaa60, 0x00060000},
+ {0}
+};
+
+static const struct gt_powermeter ivb_pm_gt2[] = {
+ {0xa800, 0x10000000},
+ {0xa804, 0x00033800},
+ {0xa808, 0x00000902},
+ {0xa80c, 0x0c002f00},
+ {0xa810, 0x12000400},
+ {0xa814, 0x00000000},
+ {0xa818, 0x00d20800},
+ {0xa81c, 0x00000002},
+ {0xa820, 0x03004b02},
+ {0xa824, 0x00000600},
+ {0xa828, 0x07000773},
+ {0xa82c, 0x00000000},
+ {0xa830, 0x00010032},
+ {0xa834, 0x1520040d},
+ {0xa838, 0x00020105},
+ {0xa83c, 0x00083700},
+ {0xa840, 0x0000151d},
+ {0xa844, 0x00000000},
+ {0xa848, 0x20001b00},
+ {0xa84c, 0x0a000010},
+ {0xa850, 0x00000000},
+ {0xa854, 0x00000008},
+ {0xa858, 0x00000008},
+ {0xa85c, 0x00000000},
+ {0xa860, 0x00020000},
+ {0xa248, 0x0000221e},
+ {0xa900, 0x00000000},
+ {0xa904, 0x00003500},
+ {0xa908, 0x00000000},
+ {0xa90c, 0x0c000000},
+ {0xa910, 0x12000500},
+ {0xa914, 0x00000000},
+ {0xa918, 0x00b20000},
+ {0xa91c, 0x00000000},
+ {0xa920, 0x08004b02},
+ {0xa924, 0x00000200},
+ {0xa928, 0x07000820},
+ {0xa92c, 0x00000000},
+ {0xa930, 0x00030000},
+ {0xa934, 0x050f020d},
+ {0xa938, 0x00020300},
+ {0xa93c, 0x00903900},
+ {0xa940, 0x00000000},
+ {0xa944, 0x00000000},
+ {0xa948, 0x20001b00},
+ {0xa94c, 0x0a000010},
+ {0xa950, 0x00000000},
+ {0xa954, 0x00000008},
+ {0xa960, 0x00110000},
+ {0xaa3c, 0x00003900},
+ {0xaa54, 0x00000008},
+ {0xaa60, 0x00110000},
+ {0}
+};
+
+static const struct gt_powermeter ivb_pm_gt2_17w[] = {
+ {0xa800, 0x20000000},
+ {0xa804, 0x000e3800},
+ {0xa808, 0x00000806},
+ {0xa80c, 0x0c002f00},
+ {0xa810, 0x0c000800},
+ {0xa814, 0x00000000},
+ {0xa818, 0x00d20d00},
+ {0xa81c, 0x000000ff},
+ {0xa820, 0x03004b02},
+ {0xa824, 0x00000600},
+ {0xa828, 0x07000773},
+ {0xa82c, 0x00000000},
+ {0xa830, 0x00020032},
+ {0xa834, 0x1520040d},
+ {0xa838, 0x00020105},
+ {0xa83c, 0x00083700},
+ {0xa840, 0x000016ff},
+ {0xa844, 0x00000000},
+ {0xa848, 0xff000000},
+ {0xa84c, 0x0a000010},
+ {0xa850, 0x00000002},
+ {0xa854, 0x00000008},
+ {0xa858, 0x0000000f},
+ {0xa85c, 0x00000000},
+ {0xa860, 0x00020000},
+ {0xa248, 0x0000221e},
+ {0xa900, 0x00000000},
+ {0xa904, 0x00003800},
+ {0xa908, 0x00000000},
+ {0xa90c, 0x0c000000},
+ {0xa910, 0x12000800},
+ {0xa914, 0x00000000},
+ {0xa918, 0x00b20000},
+ {0xa91c, 0x00000000},
+ {0xa920, 0x08004b02},
+ {0xa924, 0x00000300},
+ {0xa928, 0x01000820},
+ {0xa92c, 0x00000000},
+ {0xa930, 0x00030000},
+ {0xa934, 0x15150406},
+ {0xa938, 0x00020300},
+ {0xa93c, 0x00903900},
+ {0xa940, 0x00000000},
+ {0xa944, 0x00000000},
+ {0xa948, 0x20001b00},
+ {0xa94c, 0x0a000010},
+ {0xa950, 0x00000000},
+ {0xa954, 0x00000008},
+ {0xa960, 0x00110000},
+ {0xaa3c, 0x00003900},
+ {0xaa54, 0x00000008},
+ {0xaa60, 0x00110000},
+ {0}
+};
+
+static const struct gt_powermeter ivb_pm_gt2_35w[] = {
+ {0xa800, 0x00000000},
+ {0xa804, 0x00030400},
+ {0xa808, 0x00000806},
+ {0xa80c, 0x0c002f00},
+ {0xa810, 0x0c000300},
+ {0xa814, 0x00000000},
+ {0xa818, 0x00d20d00},
+ {0xa81c, 0x000000ff},
+ {0xa820, 0x03004b02},
+ {0xa824, 0x00000600},
+ {0xa828, 0x07000773},
+ {0xa82c, 0x00000000},
+ {0xa830, 0x00020032},
+ {0xa834, 0x1520040d},
+ {0xa838, 0x00020105},
+ {0xa83c, 0x00083700},
+ {0xa840, 0x000016ff},
+ {0xa844, 0x00000000},
+ {0xa848, 0xff000000},
+ {0xa84c, 0x0a000010},
+ {0xa850, 0x00000001},
+ {0xa854, 0x00000008},
+ {0xa858, 0x00000008},
+ {0xa85c, 0x00000000},
+ {0xa860, 0x00020000},
+ {0xa248, 0x0000221e},
+ {0xa900, 0x00000000},
+ {0xa904, 0x00003800},
+ {0xa908, 0x00000000},
+ {0xa90c, 0x0c000000},
+ {0xa910, 0x12000800},
+ {0xa914, 0x00000000},
+ {0xa918, 0x00b20000},
+ {0xa91c, 0x00000000},
+ {0xa920, 0x08004b02},
+ {0xa924, 0x00000300},
+ {0xa928, 0x01000820},
+ {0xa92c, 0x00000000},
+ {0xa930, 0x00030000},
+ {0xa934, 0x15150406},
+ {0xa938, 0x00020300},
+ {0xa93c, 0x00903900},
+ {0xa940, 0x00000000},
+ {0xa944, 0x00000000},
+ {0xa948, 0x20001b00},
+ {0xa94c, 0x0a000010},
+ {0xa950, 0x00000000},
+ {0xa954, 0x00000008},
+ {0xa960, 0x00110000},
+ {0xaa3c, 0x00003900},
+ {0xaa54, 0x00000008},
+ {0xaa60, 0x00110000},
+ {0}
+};
+
+static struct resource *gtt_res = NULL;
+
+static inline u32 gtt_read(u32 reg)
+{
+ return read32(gtt_res->base + reg);
+}
+
+static inline void gtt_write(u32 reg, u32 data)
+{
+ write32(gtt_res->base + reg, data);
+}
+
+static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
+{
+ for (; pm && pm->reg; pm++)
+ gtt_write(pm->reg, pm->value);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(u32 reg, u32 mask, u32 value)
+{
+ unsigned try = GTT_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = gtt_read(reg);
+ if ((data & mask) == value)
+ return 1;
+ udelay(10);
+ }
+
+ printk(BIOS_ERR, "GT init timeout\n");
+ return 0;
+}
+
+static void gma_pm_init_pre_vbios(struct device *dev)
+{
+ u32 reg32;
+
+ printk(BIOS_DEBUG, "GT Power Management Init\n");
+
+ gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!gtt_res || !gtt_res->base)
+ return;
+
+ /* 1: Enable force wake */
+ gtt_write(0xa18c, 0x00000001);
+ gtt_poll(0x130090, (1 << 0), (1 << 0));
+
+ /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+ reg32 = gtt_read(0x42004);
+ reg32 |= (1 << 14) | (1 << 15);
+ gtt_write(0x42004, reg32);
+
+ /* 2: Get GT SKU from GTT+0x911c[13] */
+ reg32 = gtt_read(0x911c);
+ if (reg32 & (1 << 13)) {
+ printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n");
+ gtt_write_powermeter(snb_pm_gt1);
+ } else {
+ printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n");
+ gtt_write_powermeter(snb_pm_gt2);
+ }
+
+ /* 3: Gear ratio map */
+ gtt_write(0xa004, 0x00000010);
+
+ /* 4: GFXPAUSE */
+ gtt_write(0xa000, 0x00070020);
+
+ /* 5: Dynamic EU trip control */
+ gtt_write(0xa080, 0x00000004);
+
+ /* 6: ECO bits */
+ reg32 = gtt_read(0xa180);
+ reg32 |= (1 << 26) | (1 << 31);
+ gtt_write(0xa180, reg32);
+
+ /* 6b: Clocking reset controls */
+ gtt_write(0x9424, 0x00000000);
+
+ /* 7 */
+ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
+ gtt_write(0x138128, 0x00000029); /* Mailbox Data */
+ gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
+ if (gtt_poll(0x138124, (1 << 31), (0 << 31)))
+ gtt_write(0x138124, 0x8000000a);
+ gtt_poll(0x138124, (1 << 31), (0 << 31));
+ }
+
+ /* 8 */
+ gtt_write(0xa090, 0x00000000); /* RC Control */
+ gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+ gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+ gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+ gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+ gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+ /* 9 */
+ gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */
+ gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */
+ gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */
+
+ /* 10 */
+ gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+ gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */
+ gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */
+ gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */
+ gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+ /* 11 */
+ gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */
+ gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */
+ gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */
+ gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */
+ gtt_write(0xa068, 0x000186a0); /* RP Up EI */
+ gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
+ gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+ /* 11a: Enable Render Standby (RC6) */
+ gtt_write(0xa090, 0x88040000); /* HW RC Control */
+
+ /* 12: Normal Frequency Request */
+ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+ reg32 = MCHBAR32(0x5998);
+ reg32 >>= 16;
+ reg32 &= 0xef;
+ reg32 <<= 25;
+ gtt_write(0xa008, reg32);
+
+ /* 13: RP Control */
+ gtt_write(0xa024, 0x00000592);
+
+ /* 14: Enable PM Interrupts */
+ gtt_write(0x4402c, 0x03000076);
+
+ /* Clear 0x6c024 [8:6] */
+ reg32 = gtt_read(0x6c024);
+ reg32 &= ~0x000001c0;
+ gtt_write(0x6c024, reg32);
+}
+
+#if 1
+
+static u8 my_inb(u16 addr)
+{
+ u8 val;
+
+ val = inb(addr);
+
+ return val;
+}
+
+static u16 my_inw(u16 addr)
+{
+ u16 val;
+
+ val = inw(addr);
+
+ return val;
+}
+
+static u32 my_inl(u16 addr)
+{
+ u32 val;
+
+ val = inl(addr);
+
+ return val;
+}
+
+static void my_outb(u16 addr, u8 val)
+{
+ outb(val, addr);
+}
+
+static void my_outw(u16 addr, u16 val)
+{
+ outw(val, addr);
+}
+
+static void my_outl(u16 addr, u32 val)
+{
+ outl(val, addr);
+}
+#endif
+
+#include <pc80/vga.h>
+#include <pc80/vga_io.h>
+
+static void fake_vbios(void)
+{
+#include "fake_vbios.c"
+}
+
+static unsigned char fake_vbt[] = {
+ 0x24, 0x56, 0x42, 0x54, 0x20, 0x49, 0x52, 0x4f, 0x4e, 0x4c, 0x41, 0x4b,
+ 0x45, 0x2d, 0x4d, 0x4f,
+ 0x42, 0x49, 0x4c, 0x45, 0x64, 0x00, 0x30, 0x00, 0x8e, 0x0f, 0x48, 0x00,
+ 0x30, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x42, 0x49, 0x4f, 0x53, 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f, 0x42, 0x4c,
+ 0x4f, 0x43, 0x4b, 0x20,
+ 0x9c, 0x00, 0x16, 0x00, 0x5e, 0x0f, 0xfe, 0xea, 0x00, 0x00, 0x64, 0x01,
+ 0x01, 0x0f, 0x0d, 0x32,
+ 0x30, 0x32, 0x36, 0x44, 0x43, 0x49, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x6c,
+ 0x28, 0x52, 0x29, 0x49,
+ 0x72, 0x6f, 0x6e, 0x6c, 0x61, 0x6b, 0x65, 0x20, 0x4d, 0x6f, 0x62, 0x69,
+ 0x6c, 0x65, 0x20, 0x50,
+ 0x43, 0x49, 0x20, 0x41, 0x63, 0x63, 0x65, 0x6c, 0x65, 0x72, 0x61, 0x74,
+ 0x65, 0x64, 0x20, 0x53,
+ 0x56, 0x47, 0x41, 0x20, 0x42, 0x49, 0x4f, 0x53, 0x0d, 0x0a, 0x42, 0x75,
+ 0x69, 0x6c, 0x64, 0x20,
+ 0x4e, 0x75, 0x6d, 0x62, 0x65, 0x72, 0x3a, 0x20, 0x32, 0x30, 0x32, 0x36,
+ 0x20, 0x50, 0x43, 0x20,
+ 0x31, 0x34, 0x2e, 0x33, 0x34, 0x20, 0x20, 0x30, 0x39, 0x2f, 0x32, 0x38,
+ 0x20, 0x2f, 0x32, 0x30,
+ 0x31, 0x30, 0x20, 0x20, 0x32, 0x32, 0x3a, 0x32, 0x30, 0x3a, 0x35, 0x32,
+ 0x0d, 0x0a, 0x44, 0x45,
+ 0x43, 0x4f, 0x4d, 0x50, 0x49, 0x4c, 0x41, 0x54, 0x49, 0x4f, 0x4e, 0x20,
+ 0x4f, 0x52, 0x20, 0x44,
+ 0x49, 0x53, 0x41, 0x53, 0x53, 0x45, 0x4d, 0x42, 0x4c, 0x59, 0x20, 0x50,
+ 0x52, 0x4f, 0x48, 0x49,
+ 0x42, 0x49, 0x54, 0x45, 0x44, 0x0d, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x43, 0x6f,
+ 0x70, 0x79, 0x72, 0x69, 0x67, 0x68, 0x74, 0x20, 0x28, 0x43, 0x29, 0x20,
+ 0x32, 0x30, 0x30, 0x30,
+ 0x2d, 0x32, 0x30, 0x30, 0x33, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x6c, 0x20,
+ 0x43, 0x6f, 0x72, 0x70,
+ 0x2e, 0x20, 0x41, 0x6c, 0x6c, 0x20, 0x52, 0x69, 0x67, 0x68, 0x74, 0x73,
+ 0x20, 0x52, 0x65, 0x73,
+ 0x65, 0x72, 0x76, 0x65, 0x64, 0x2e, 0x0d, 0x0a, 0x0d, 0x0a, 0x00, 0x00,
+ 0xc0, 0x03, 0x08, 0x04,
+ 0x00, 0x00, 0x00, 0x01, 0x05, 0x00, 0x07, 0x03, 0x00, 0x01, 0x19, 0xfe,
+ 0x32, 0x00, 0x44, 0x04,
+ 0x40, 0x06, 0x04, 0x02, 0x09, 0x01, 0x08, 0x0a, 0x02, 0x08, 0x0c, 0x04,
+ 0x08, 0x03, 0x01, 0x02,
+ 0x05, 0x01, 0x04, 0x0d, 0x01, 0x04, 0x0b, 0x01, 0x02, 0x07, 0x01, 0x04,
+ 0x15, 0x01, 0x04, 0x45,
+ 0x01, 0x04, 0x0e, 0x04, 0x08, 0x46, 0x04, 0x40, 0x28, 0x20, 0x08, 0x48,
+ 0x40, 0x08, 0x10, 0x00,
+ 0x02, 0x0d, 0x01, 0x02, 0x04, 0x00, 0x00, 0x21, 0x08, 0x00, 0x22, 0x10,
+ 0x00, 0x20, 0x00, 0x00,
+ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0xcd, 0x04, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0xc6,
+ 0x68, 0x00, 0x20, 0x00,
+ 0x01, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0xe3, 0x08, 0x00, 0x00,
+ 0x04, 0x00, 0x00, 0x00,
+ 0x00, 0x07, 0x20, 0x01, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x20,
+ 0x00, 0x01, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x20, 0x00, 0x01, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x20, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x01, 0x00, 0x00, 0x04, 0x1c, 0x00, 0x30, 0x32, 0x34, 0x36, 0x38,
+ 0x3a, 0x3c, 0x40, 0x42,
+ 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c,
+ 0x80, 0x81, 0x82, 0x83,
+ 0x84, 0x1a, 0x00, 0xfe, 0xad, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x01, 0x30, 0x00, 0xbf,
+ 0x06, 0x1e, 0x00, 0x59,
+ 0x03, 0x28, 0x00, 0x86, 0x03, 0x02, 0x00, 0x90, 0x03, 0x38, 0x00, 0xd1,
+ 0x03, 0xc8, 0x00, 0x1f,
+ 0x06, 0x30, 0x00, 0x52, 0x06, 0x18, 0x00, 0x6d, 0x06, 0x18, 0x00, 0x88,
+ 0x06, 0x18, 0x00, 0x8b,
+ 0x07, 0x08, 0x00, 0xcf, 0x07, 0x12, 0x00, 0xe1, 0x07, 0x12, 0x00, 0xf3,
+ 0x07, 0x12, 0x00, 0x05,
+ 0x08, 0x12, 0x00, 0x1a, 0x08, 0x0a, 0x00, 0x24, 0x08, 0x0a, 0x00, 0x2e,
+ 0x08, 0x0a, 0x00, 0x38,
+ 0x08, 0x0a, 0x00, 0x45, 0x08, 0x0a, 0x00, 0x4f, 0x08, 0x0a, 0x00, 0x59,
+ 0x08, 0x0a, 0x00, 0x63,
+ 0x08, 0x0a, 0x00, 0x75, 0x08, 0x0a, 0x00, 0x7f, 0x08, 0x0a, 0x00, 0x89,
+ 0x08, 0x0a, 0x00, 0x93,
+ 0x08, 0x0a, 0x00, 0x9d, 0x08, 0x0a, 0x00, 0xa7, 0x08, 0x0a, 0x00, 0xb1,
+ 0x08, 0x0a, 0x00, 0xbb,
+ 0x08, 0x0a, 0x00, 0xc5, 0x08, 0x0a, 0x00, 0xcf, 0x08, 0x0a, 0x00, 0xd9,
+ 0x08, 0x0a, 0x00, 0xe3,
+ 0x08, 0x0a, 0x00, 0xed, 0x08, 0x0a, 0x00, 0xf7, 0x08, 0x0a, 0x00, 0x01,
+ 0x09, 0x0a, 0x00, 0x0b,
+ 0x09, 0x0a, 0x00, 0x06, 0x5d, 0x00, 0xfc, 0xff, 0x02, 0x80, 0x00, 0x07,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x11, 0x07,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x04, 0x00, 0x8e, 0x29, 0x00, 0x80, 0x9c, 0x01, 0x07,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x9c, 0x11, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xff, 0xff, 0x07, 0x07, 0x00, 0xfe, 0xff, 0xce, 0x18, 0x00, 0xff,
+ 0xff, 0x08, 0x3d, 0x00,
+ 0xfc, 0xff, 0x02, 0x40, 0xf0, 0x04, 0x00, 0x01, 0x00, 0x00, 0x01, 0x44,
+ 0xf0, 0x04, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x48, 0xf0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4c,
+ 0xf0, 0x04, 0x00, 0x00,
+ 0x00, 0x03, 0x03, 0x50, 0xf0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54,
+ 0xf0, 0x04, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x58, 0xf0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
+ 0xff, 0x0a, 0xcb, 0x00,
+ 0x0a, 0x80, 0x04, 0x60, 0x03, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0x00,
+ 0x05, 0x58, 0x02, 0xff,
+ 0xff, 0xff, 0xbf, 0xff, 0xff, 0x00, 0x05, 0xc0, 0x03, 0xff, 0xff, 0xff,
+ 0xbf, 0xff, 0xff, 0x80,
+ 0x07, 0xa0, 0x05, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xff, 0xff, 0x40, 0x07, 0x70, 0x05, 0xff, 0xff, 0xff, 0xbf, 0xff,
+ 0xff, 0x00, 0x07, 0x40,
+ 0x05, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xff, 0x80, 0x02, 0xe0, 0x01, 0xff,
+ 0x1b, 0xfe, 0x07, 0xff,
+ 0xff, 0x20, 0x03, 0x58, 0x02, 0xff, 0x1b, 0xfe, 0x07, 0xff, 0xff, 0x00,
+ 0x04, 0x00, 0x03, 0xff,
+ 0x1b, 0xfe, 0x07, 0xff, 0xff, 0x40, 0x06, 0xb0, 0x04, 0xff, 0x1b, 0xff,
+ 0x07, 0xff, 0xff, 0x00,
+ 0x08, 0x00, 0x06, 0xff, 0xdb, 0xff, 0x07, 0xff, 0xff, 0x00, 0x05, 0x00,
+ 0x04, 0xff, 0x1b, 0xfe,
+ 0x07, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xff,
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xff, 0xff, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x0b,
+ 0xc7, 0x00, 0x21, 0x40,
+ 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x01,
+ 0x05, 0x70, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x40, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x05, 0x72, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x20, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x20, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x20,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00,
+ 0x20, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x11, 0x00, 0x4a, 0x00, 0x04, 0x00,
+ 0x03, 0x08, 0x3c, 0x84,
+ 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x00, 0x00, 0x0d, 0x03, 0x00,
+ 0xf7, 0x03, 0xc8, 0x0e,
+ 0x09, 0x00, 0x01, 0x90, 0x05, 0x5a, 0x00, 0xec, 0x05, 0x2d, 0x00, 0x0f,
+ 0x8b, 0x00, 0x09, 0x0a,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x05,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0xc4, 0x09, 0xfa, 0x00, 0x10, 0x72, 0x0c, 0x00, 0x03, 0x0f, 0x27, 0x00,
+ 0xff, 0xff, 0x64, 0x19,
+ 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, 0x36, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x1e,
+ 0x36, 0x7f, 0x03, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x04,
+ 0x00, 0x03, 0x80, 0x11,
+ 0x0e, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08, 0x72, 0x0c, 0x00, 0xc4, 0x09,
+ 0xfa, 0x00, 0x0c, 0x72,
+ 0x0c, 0x00, 0xc4, 0x09, 0xfa, 0x00, 0x10, 0x72, 0x0c, 0x00, 0x03, 0x0f,
+ 0x27, 0x00, 0xff, 0xff,
+ 0x64, 0x19, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, 0x36, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x1e, 0x36, 0x7f, 0x03, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x0c,
+ 0x00, 0x05, 0x20, 0x03,
+ 0x80, 0x11, 0x0e, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08, 0x72, 0x0c, 0x00,
+ 0xc4, 0x09, 0xfa, 0x00,
+ 0x0c, 0x72, 0x0c, 0x00, 0xc4, 0x09, 0xfa, 0x00, 0x10, 0x72, 0x0c, 0x00,
+ 0x03, 0x0f, 0x27, 0x00,
+ 0xff, 0xff, 0xea, 0x1a, 0x00, 0xa0, 0x50, 0x20, 0x17, 0x30, 0x0c, 0x30,
+ 0x43, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x1e, 0x36, 0x7f, 0x03, 0x00, 0x0e, 0x00, 0x00, 0x00,
+ 0x00, 0x0c, 0x00, 0x05,
+ 0x58, 0x02, 0x80, 0x11, 0x0e, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08, 0x72,
+ 0x0c, 0x00, 0xc4, 0x09,
+ 0xfa, 0x00, 0x0c, 0x72, 0x0c, 0x00, 0xc4, 0x09, 0xfa, 0x00, 0x10, 0x72,
+ 0x0c, 0x00, 0x03, 0x0f,
+ 0x27, 0x00, 0xff, 0xff, 0x06, 0x18, 0x00, 0x70, 0x51, 0x58, 0x15, 0x20,
+ 0x38, 0x80, 0x13, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x36, 0x7f, 0x03, 0x00, 0x0f, 0x00,
+ 0x00, 0x00, 0x00, 0x0c,
+ 0x00, 0x08, 0x00, 0x06, 0x80, 0x11, 0x0e, 0x00, 0x3c, 0x03, 0x00, 0x00,
+ 0x08, 0x72, 0x0c, 0x00,
+ 0xc4, 0x09, 0xfa, 0x00, 0x0c, 0x72, 0x0c, 0x00, 0xc4, 0x09, 0xfa, 0x00,
+ 0x10, 0x72, 0x0c, 0x00,
+ 0x03, 0x0f, 0x27, 0x00, 0xff, 0xff, 0x29, 0x40, 0x00, 0x60, 0x80, 0x00,
+ 0x13, 0x60, 0x10, 0x10,
+ 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x36, 0x7f, 0x03, 0x00,
+ 0x10, 0x00, 0x00, 0x00,
+ 0x00, 0x0c, 0x70, 0x61, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x4d,
+ 0x50, 0x57, 0x58, 0x47, 0x41, 0x32, 0x32, 0x30, 0x4e, 0x49, 0x54, 0x00,
+ 0x4d, 0x50, 0x57, 0x58,
+ 0x47, 0x41, 0x2b, 0x32, 0x35, 0x30, 0x4e, 0x49, 0x54, 0x43, 0x5f, 0x44,
+ 0x42, 0x34, 0x30, 0x30,
+ 0x4e, 0x49, 0x54, 0x00, 0x00, 0x00, 0x43, 0x5f, 0x4d, 0x54, 0x50, 0x33,
+ 0x30, 0x30, 0x4e, 0x49,
+ 0x54, 0x00, 0x00, 0x43, 0x5f, 0x50, 0x50, 0x32, 0x32, 0x30, 0x4e, 0x49,
+ 0x54, 0x00, 0x00, 0x00,
+ 0x4d, 0x50, 0x43, 0x5f, 0x43, 0x43, 0x46, 0x4c, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x70, 0x61, 0x6e,
+ 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x61,
+ 0x6e, 0x65, 0x6c, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x61, 0x6e, 0x65, 0x6c,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x70, 0x61, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x70, 0x61, 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x70, 0x61,
+ 0x6e, 0x65, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x61, 0x6e, 0x65, 0x6c,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x61, 0x6e, 0x65,
+ 0x6c, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x61, 0x6e, 0x65, 0x6c, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x2b, 0x61, 0x00, 0x06, 0x4e, 0xdc, 0x00, 0x00, 0x58, 0xaa,
+ 0x4a, 0x71, 0x02, 0x04,
+ 0x58, 0xaa, 0x4a, 0xa5, 0x00, 0x04, 0x58, 0xaa, 0x4a, 0x96, 0x00, 0x02,
+ 0x58, 0xaa, 0x4a, 0x5a,
+ 0x00, 0x04, 0x58, 0xaa, 0x4a, 0xff, 0x00, 0x05, 0x58, 0xaa, 0x4a, 0xa5,
+ 0x00, 0x16, 0x58, 0xaa,
+ 0x4e, 0xdc, 0x00, 0x00, 0x58, 0xaa, 0x4e, 0xdc, 0x00, 0x00, 0x58, 0xaa,
+ 0x4e, 0xdc, 0x00, 0x00,
+ 0x58, 0xaa, 0x4e, 0xdc, 0x00, 0x00, 0x58, 0xaa, 0x4e, 0xdc, 0x00, 0x00,
+ 0x58, 0xaa, 0x4e, 0xdc,
+ 0x00, 0x00, 0x58, 0xaa, 0x4e, 0xdc, 0x00, 0x00, 0x58, 0xaa, 0x4e, 0xdc,
+ 0x00, 0x00, 0x58, 0xaa,
+ 0x4e, 0xdc, 0x00, 0x00, 0x58, 0xaa, 0x2c, 0x15, 0x00, 0x09, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+static void gma_pm_init_post_vbios(struct device *dev)
+{
+ struct northbridge_intel_nehalem_config *conf = dev->chip_info;
+ u32 reg32;
+
+ /* Linux relies on VBT for panel info. */
+ if (read16(0xc0000) != 0xaa55) {
+ optionrom_header_t *oh = (void *)0xc0000;
+ optionrom_pcir_t *pcir;
+ int sz;
+
+ memset(oh->reserved, 0, 8192);
+
+ sz = (0x80 + sizeof(fake_vbt) + 511) / 512;
+ oh->signature = 0xaa55;
+ oh->size = sz;
+ oh->pcir_offset = 0x40;
+ oh->vbt_offset = 0x80;
+
+ pcir = (void *)0xc0040;
+ pcir->signature = 0x52494350; // PCIR
+ pcir->vendor = dev->vendor;
+ pcir->device = dev->device;
+ pcir->length = sizeof(*pcir);
+ pcir->revision = dev->class;
+ pcir->classcode[0] = dev->class >> 8;
+ pcir->classcode[1] = dev->class >> 16;
+ pcir->classcode[2] = dev->class >> 24;
+ pcir->imagelength = sz;
+ pcir->indicator = 0x80;
+
+ memcpy((void *)0xc0080, fake_vbt, sizeof(fake_vbt));
+ }
+
+ printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
+
+ /* 15: Deassert Force Wake */
+ gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
+ gtt_poll(0x130090, (1 << 0), (0 << 0));
+
+ /* 16: SW RC Control */
+ gtt_write(0xa094, 0x00060000);
+
+ /* Setup Digital Port Hotplug */
+ reg32 = gtt_read(0xc4030);
+ if (!reg32) {
+ reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
+ reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
+ reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
+ gtt_write(0xc4030, reg32);
+ }
+
+ /* Setup Panel Power On Delays */
+ reg32 = gtt_read(0xc7208);
+ if (!reg32) {
+ reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
+ reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
+ reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
+ gtt_write(0xc7208, reg32);
+ }
+
+ /* Setup Panel Power Off Delays */
+ reg32 = gtt_read(0xc720c);
+ if (!reg32) {
+ reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
+ reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
+ gtt_write(0xc720c, reg32);
+ }
+
+ /* Setup Panel Power Cycle Delay */
+ if (conf->gpu_panel_power_cycle_delay) {
+ reg32 = gtt_read(0xc7210);
+ reg32 &= ~0xff;
+ reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
+ gtt_write(0xc7210, reg32);
+ }
+
+ /* Enable Backlight if needed */
+ if (conf->gpu_cpu_backlight) {
+ gtt_write(0x48250, (1 << 31));
+ gtt_write(0x48254, conf->gpu_cpu_backlight);
+ }
+ if (conf->gpu_pch_backlight) {
+ gtt_write(0xc8250, (1 << 31));
+ gtt_write(0xc8254, conf->gpu_pch_backlight);
+ }
+}
+
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+struct lb_framebuffer;
+
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+int vbe_mode_info_valid(void);
+
+int vbe_mode_info_valid(void)
+{
+ return 0;
+}
+
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+{
+}
+
+#endif
+
+static void gma_func0_init(struct device *dev)
+{
+ u32 reg32;
+
+ /* IGD needs to be Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Init graphics power management */
+ gma_pm_init_pre_vbios(dev);
+
+#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* PCI Init, will run VBIOS */
+ pci_dev_init(dev);
+#endif
+
+ /* Post VBIOS init */
+ gma_pm_init_post_vbios(dev);
+
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* This should probably run before post VBIOS init. */
+ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
+ u32 iobase, mmiobase, physbase, graphics_base;
+ iobase = dev->resource_list[2].base;
+ mmiobase = dev->resource_list[0].base;
+ physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+ graphics_base = dev->resource_list[1].base;
+
+ fake_vbios();
+#endif
+}
+
+static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor &
+ 0xffff));
+ }
+}
+
+static void gma_read_resources(struct device *dev)
+{
+ pci_dev_read_resources(dev);
+
+#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
+ struct resource *res;
+
+ /* Set the graphics memory to write combining. */
+ res = find_resource(dev, PCI_BASE_ADDRESS_2);
+ if (res == NULL) {
+ printk(BIOS_DEBUG, "gma: memory resource not found.\n");
+ return;
+ }
+ res->flags |= IORESOURCE_WRCOMB;
+#endif
+}
+
+static struct pci_operations gma_pci_ops = {
+ .set_subsystem = gma_set_subsystem,
+};
+
+static struct device_operations gma_func0_ops = {
+ .read_resources = gma_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gma_func0_init,
+ .scan_bus = 0,
+ .enable = 0,
+ .ops_pci = &gma_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] =
+ { 0x0046,
+ 0
+};
+
+static const struct pci_driver gma __pci_driver = {
+ .ops = &gma_func0_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h
new file mode 100644
index 0000000..bfa43ef
--- /dev/null
+++ b/src/northbridge/intel/nehalem/gma.h
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mailbox 0: header */
+typedef struct {
+ u8 signature[16];
+ u32 size;
+ u32 version;
+ u8 sbios_version[32];
+ u8 vbios_version[16];
+ u8 driver_version[16];
+ u32 mailboxes;
+ u8 reserved[164];
+} __attribute__((packed)) opregion_header_t;
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION 2
+
+#define IGD_MBOX1 (1 << 0)
+#define IGD_MBOX2 (1 << 1)
+#define IGD_MBOX3 (1 << 2)
+#define IGD_MBOX4 (1 << 3)
+#define IGD_MBOX5 (1 << 4)
+
+#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+ IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+typedef struct {
+ u32 drdy;
+ u32 csts;
+ u32 cevt;
+ u8 reserved1[20];
+ u32 didl[8];
+ u32 cpdl[8];
+ u32 cadl[8];
+ u32 nadl[8];
+ u32 aslp;
+ u32 tidx;
+ u32 chpd;
+ u32 clid;
+ u32 cdck;
+ u32 sxsw;
+ u32 evts;
+ u32 cnot;
+ u32 nrdy;
+ u8 reserved2[60];
+} __attribute__((packed)) opregion_mailbox1_t;
+
+/* mailbox 2: software sci interface */
+typedef struct {
+ u32 scic;
+ u32 parm;
+ u32 dslp;
+ u8 reserved[244];
+} __attribute__((packed)) opregion_mailbox2_t;
+
+/* mailbox 3: power conservation */
+typedef struct {
+ u32 ardy;
+ u32 aslc;
+ u32 tche;
+ u32 alsi;
+ u32 bclp;
+ u32 pfit;
+ u32 cblv;
+ u16 bclm[20];
+ u32 cpfm;
+ u32 epfm;
+ u8 plut[74];
+ u32 pfmb;
+ u32 ccdv;
+ u32 pcft;
+ u8 reserved[94];
+} __attribute__((packed)) opregion_mailbox3_t;
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID (1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+typedef struct {
+ u8 gvd1[7168];
+} __attribute__((packed)) opregion_vbt_t;
+
+/* IGD OpRegion */
+typedef struct {
+ opregion_header_t header;
+ opregion_mailbox1_t mailbox1;
+ opregion_mailbox2_t mailbox2;
+ opregion_mailbox3_t mailbox3;
+ opregion_vbt_t vbt;
+} __attribute__((packed)) igd_opregion_t;
+
+/* Intel Video BIOS (Option ROM) */
+typedef struct {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+} __attribute__((packed)) optionrom_header_t;
+
+#define OPROM_SIGNATURE 0xaa55
+
+typedef struct {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+} __attribute__((packed)) optionrom_pcir_t;
+
+typedef struct {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+} __attribute__((packed)) optionrom_vbt_t;
+
+#define VBT_SIGNATURE 0x54425624
+
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
new file mode 100644
index 0000000..53e5d44
--- /dev/null
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -0,0 +1,609 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
+#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ 1
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+typedef enum {
+ FSB_CLOCK_1067MHz = 0,
+ FSB_CLOCK_800MHz = 1,
+ FSB_CLOCK_667MHz = 2,
+} fsb_clock_t;
+
+typedef enum { /* Steppings below B1 were pre-production,
+ conversion stepping A1 is... ?
+ We'll support B1, B2, B3, and conversion stepping A1. */
+ STEPPING_A0 = 0,
+ STEPPING_A1 = 1,
+ STEPPING_A2 = 2,
+ STEPPING_A3 = 3,
+ STEPPING_B0 = 4,
+ STEPPING_B1 = 5,
+ STEPPING_B2 = 6,
+ STEPPING_B3 = 7,
+ STEPPING_CONVERSION_A1 = 9,
+} stepping_t;
+
+typedef enum {
+ GMCH_GM45 = 0,
+ GMCH_GM47,
+ GMCH_GM49,
+ GMCH_GE45,
+ GMCH_GL40,
+ GMCH_GL43,
+ GMCH_GS40,
+ GMCH_GS45,
+ GMCH_PM45,
+ GMCH_UNKNOWN
+} gmch_gfx_t;
+
+typedef enum {
+ MEM_CLOCK_533MHz = 0,
+ MEM_CLOCK_400MHz = 1,
+ MEM_CLOCK_333MHz = 2,
+ MEM_CLOCK_1067MT = 0,
+ MEM_CLOCK_800MT = 1,
+ MEM_CLOCK_667MT = 2,
+} mem_clock_t;
+
+typedef enum {
+ DDR1 = 1,
+ DDR2 = 2,
+ DDR3 = 3,
+} ddr_t;
+
+typedef enum {
+ CHANNEL_MODE_SINGLE,
+ CHANNEL_MODE_DUAL_ASYNC,
+ CHANNEL_MODE_DUAL_INTERLEAVED,
+} channel_mode_t;
+
+typedef enum { /* as in DDR3 spd */
+ CHIP_WIDTH_x4 = 0,
+ CHIP_WIDTH_x8 = 1,
+ CHIP_WIDTH_x16 = 2,
+ CHIP_WIDTH_x32 = 3,
+} chip_width_t;
+
+typedef enum { /* as in DDR3 spd */
+ CHIP_CAP_256M = 0,
+ CHIP_CAP_512M = 1,
+ CHIP_CAP_1G = 2,
+ CHIP_CAP_2G = 3,
+ CHIP_CAP_4G = 4,
+ CHIP_CAP_8G = 5,
+ CHIP_CAP_16G = 6,
+} chip_capacity_t;
+
+typedef struct {
+ unsigned int CAS;
+ fsb_clock_t fsb_clock;
+ mem_clock_t mem_clock;
+ channel_mode_t channel_mode;
+ unsigned int tRAS;
+ unsigned int tRP;
+ unsigned int tRCD;
+ unsigned int tRFC;
+ unsigned int tWR;
+ unsigned int tRD;
+ unsigned int tRRD;
+ unsigned int tFAW;
+ unsigned int tWL;
+} timings_t;
+
+typedef struct {
+ unsigned int card_type; /* 0x0: unpopulated,
+ 0xa - 0xf: raw card type A - F */
+ chip_width_t chip_width;
+ chip_capacity_t chip_capacity;
+ unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
+ unsigned int banks;
+ unsigned int ranks;
+ unsigned int rank_capacity_mb; /* per rank in Mega Bytes */
+} dimminfo_t;
+
+/* The setup is one DIMM per channel, so there's no need to find a
+ common timing setup between multiple chips (but chip and controller
+ still need to be coordinated */
+typedef struct {
+ stepping_t stepping;
+ int txt_enabled;
+ int cores;
+ gmch_gfx_t gfx_type;
+ int gs45_low_power_mode; /* low power mode of GMCH_GS45 */
+ int max_ddr2_mhz;
+ int max_ddr3_mt;
+ fsb_clock_t max_fsb;
+ int max_fsb_mhz;
+ int max_render_mhz;
+
+ int spd_type;
+ timings_t selected_timings;
+ dimminfo_t dimms[2];
+} sysinfo_t;
+
+#define TOTAL_CHANNELS 2
+#define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
+#define CHANNEL_IS_CARDF(dimms, idx) (dimms[idx].card_type == 0xf)
+#define IF_CHANNEL_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)
+#define FOR_EACH_CHANNEL(idx) \
+ for (idx = 0; idx < TOTAL_CHANNELS; ++idx)
+#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \
+ FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx)
+
+#define RANKS_PER_CHANNEL 4 /* Only two may be populated */
+#define IF_RANK_POPULATED(dimms, ch, r) \
+ if (dimms[ch].card_type && ((r) < dimms[ch].ranks))
+#define FOR_EACH_RANK_IN_CHANNEL(r) \
+ for (r = 0; r < RANKS_PER_CHANNEL; ++r)
+#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \
+ FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r)
+#define FOR_EACH_RANK(ch, r) \
+ FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r)
+#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \
+ FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r)
+
+#define DDR3_MAX_CAS 18
+
+
+enum {
+ VCO_2666 = 4,
+ VCO_3200 = 0,
+ VCO_4000 = 1,
+ VCO_5333 = 2,
+};
+
+#endif
+
+/* Offsets of read/write training results in CMOS.
+ They will be restored upon S3 resumes. */
+#define CMOS_READ_TRAINING 0x80 /* 16 bytes */
+#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes
+ (could be reduced to 10 bytes) */
+
+
+#define DEFAULT_HECIBAR 0xfed17000
+
+ /* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
+
+#define IOMMU_BASE1 0xfed90000
+#define IOMMU_BASE2 0xfed91000
+#define IOMMU_BASE3 0xfed92000
+#define IOMMU_BASE4 0xfed93000
+
+/*
+ * D0:F0
+ */
+#define D0F0_EPBAR_LO 0x40
+#define D0F0_EPBAR_HI 0x44
+#define D0F0_MCHBAR_LO 0x48
+#define D0F0_MCHBAR_HI 0x4c
+#define D0F0_GGC 0x52
+#define D0F0_DEVEN 0x54
+#define DEVEN_PEG60 (1 << 13)
+#define DEVEN_IGD (1 << 4)
+#define DEVEN_PEG10 (1 << 3)
+#define DEVEN_PEG11 (1 << 2)
+#define DEVEN_PEG12 (1 << 1)
+#define DEVEN_HOST (1 << 0)
+#define D0F0_PCIEXBAR_LO 0x60
+#define D0F0_PCIEXBAR_HI 0x64
+#define D0F0_DMIBAR_LO 0x68
+#define D0F0_DMIBAR_HI 0x6c
+#define D0F0_PMBASE 0x78
+#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/
+#define D0F0_REMAPBASE 0x98
+#define D0F0_REMAPLIMIT 0x9a
+#define D0F0_SMRAM 0x9d
+#define D0F0_ESMRAMC 0x9e
+#define D0F0_TOM 0xa0
+#define D0F0_TOUUD 0xa2
+#define D0F0_IGD_BASE 0xa4
+#define D0F0_GTT_BASE 0xa8
+#define D0F0_TOLUD 0xb0
+#define D0F0_SKPD 0xdc /* Scratchpad Data */
+
+#define SKPAD_ACPI_S3_MAGIC 0xcafed00d
+#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
+
+
+#define D0F0_CAPID0 0xe0
+
+#define TSEG 0xac /* TSEG base */
+
+/*
+ * D1:F0 PEG
+ */
+#define PEG_CAP 0xa2
+#define SLOTCAP 0xb4
+#define PEGLC 0xec
+#define D1F0_VCCAP 0x104
+#define D1F0_VC0RCTL 0x114
+
+/*
+ * Graphics frequencies
+ */
+#define GCFGC_PCIDEV PCI_DEV(0, 2, 0)
+#define GCFGC_OFFSET 0xf0
+#define GCFGC_CR_SHIFT 0
+#define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT)
+#define GCFGC_CS_SHIFT 8
+#define GCFGC_CS_MASK (0xf << GCFGC_CS_SHIFT)
+#define GCFGC_CD_SHIFT 12
+#define GCFGC_CD_MASK (0x1 << GCFGC_CD_SHIFT)
+#define GCFGC_UPDATE_SHIFT 5
+#define GCFGC_UPDATE (0x1 << GCFGC_UPDATE_SHIFT)
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+
+#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */
+#define PMSTS_WARM_RESET (1 << 1)
+#define PMSTS_BOTH_SELFREFRESH (1 << 0)
+
+#define CLKCFG_MCHBAR 0x0c00
+#define CLKCFG_FSBCLK_SHIFT 0
+#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT)
+#define CLKCFG_MEMCLK_SHIFT 4
+#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT)
+#define CLKCFG_UPDATE (1 << 12)
+
+#define SSKPD_MCHBAR 0x0c1c
+#define SSKPD_CLK_SHIFT 0
+#define SSKPD_CLK_MASK (7 << SSKPD_CLK_SHIFT)
+
+#define DCC_MCHBAR 0x200
+#define DCC_NO_CHANXOR (1 << 10)
+#define DCC_INTERLEAVED (1 << 1)
+#define DCC_CMD_SHIFT 16
+#define DCC_CMD_MASK (7 << DCC_CMD_SHIFT)
+#define DCC_CMD_NOP (1 << DCC_CMD_SHIFT)
+ /* For mode register mr0: */
+#define DCC_SET_MREG (3 << DCC_CMD_SHIFT)
+ /* For extended mode registers mr1 to mr3: */
+#define DCC_SET_EREG (4 << DCC_CMD_SHIFT)
+#define DCC_SET_EREG_SHIFT 21
+#define DCC_SET_EREG_MASK (DCC_CMD_MASK | (3 << DCC_SET_EREG_SHIFT))
+#define DCC_SET_EREGx(x) ((DCC_SET_EREG | \
+ ((x - 1) << DCC_SET_EREG_SHIFT)) & \
+ DCC_SET_EREG_MASK)
+
+/* Per channel DRAM Row Attribute registers (32-bit) */
+#define CxDRA_MCHBAR(x) (0x1208 + (x * 0x0100))
+#define CxDRA_PAGESIZE_SHIFT(r) (r * 4) /* Per rank r */
+#define CxDRA_PAGESIZE_MASKr(r) (0x7 << CxDRA_PAGESIZE_SHIFT(r))
+#define CxDRA_PAGESIZE_MASK 0x0000ffff
+#define CxDRA_PAGESIZE(r, p) /* for log2(dimm page size in bytes) p */ \
+ (((p - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r))
+#define CxDRA_BANKS_SHIFT(r) ((r * 3) + 16)
+#define CxDRA_BANKS_MASKr(r) (0x3 << CxDRA_BANKS_SHIFT(r))
+#define CxDRA_BANKS_MASK 0x07ff0000
+#define CxDRA_BANKS(r, b) /* for number of banks b */ \
+ ((b << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r))
+
+/*
+ * Per channel DRAM Row Boundary registers (32-bit)
+ * Every two ranks share one register and must be programmed at the same time.
+ * All registers (4 ranks per channel) have to be set.
+ */
+#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r/2) * 4))
+#define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16)
+#define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r))
+#define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \
+ (((b >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r))
+
+#define CxDRC0_MCHBAR(x) (0x1230 + (x * 0x0100))
+#define CxDRC0_RANKEN0 (1 << 24) /* Rank Enable */
+#define CxDRC0_RANKEN1 (1 << 25)
+#define CxDRC0_RANKEN2 (1 << 26)
+#define CxDRC0_RANKEN3 (1 << 27)
+#define CxDRC0_RANKEN(r) (1 << (24 + r))
+#define CxDRC0_RANKEN_MASK (0xf << 24)
+#define CxDRC0_RMS_SHIFT 8 /* Refresh Mode Select */
+#define CxDRC0_RMS_MASK (7 << CxDRC0_RMS_SHIFT)
+#define CxDRC0_RMS_78US (2 << CxDRC0_RMS_SHIFT)
+#define CxDRC0_RMS_39US (3 << CxDRC0_RMS_SHIFT)
+
+#define CxDRC1_MCHBAR(x) (0x1234 + (x * 0x0100))
+#define CxDRC1_SSDS_SHIFT 24
+#define CxDRC1_SSDS_MASK (0xff << CxDRC1_SSDS_SHIFT)
+#define CxDRC1_DS (0x91 << CxDRC1_SSDS_SHIFT)
+#define CxDRC1_SS (0xb1 << CxDRC1_SSDS_SHIFT)
+#define CxDRC1_NOTPOP(r) (1 << (16 + r)) /* Write 1 for Not Populated */
+#define CxDRC1_NOTPOP_MASK (0xf << 16)
+#define CxDRC1_MUSTWR (3 << 11)
+
+#define CxDRC2_MCHBAR(x) (0x1238 + (x * 0x0100))
+#define CxDRC2_NOTPOP(r) (1 << (24 + r)) /* Write 1 for Not Populated */
+#define CxDRC2_NOTPOP_MASK (0xf << 24)
+#define CxDRC2_MUSTWR (1 << 12)
+#define CxDRC2_CLK1067MT (1 << 0)
+
+/* DRAM Timing registers (32-bit each) */
+#define CxDRT0_MCHBAR(x) (0x1210 + (x * 0x0100))
+#define CxDRT0_BtB_WtP_SHIFT 26
+#define CxDRT0_BtB_WtP_MASK (0x1f << CxDRT0_BtB_WtP_SHIFT)
+#define CxDRT0_BtB_WtR_SHIFT 20
+#define CxDRT0_BtB_WtR_MASK (0x1f << CxDRT0_BtB_WtR_SHIFT)
+#define CxDRT1_MCHBAR(x) (0x1214 + (x * 0x0100))
+#define CxDRT2_MCHBAR(x) (0x1218 + (x * 0x0100))
+#define CxDRT3_MCHBAR(x) (0x121c + (x * 0x0100))
+#define CxDRT4_MCHBAR(x) (0x1220 + (x * 0x0100))
+#define CxDRT5_MCHBAR(x) (0x1224 + (x * 0x0100))
+#define CxDRT6_MCHBAR(x) (0x1228 + (x * 0x0100))
+
+/* Clock disable registers (32-bit each) */
+#define CxDCLKDIS_MCHBAR(x) (0x120c + (x * 0x0100))
+#define CxDCLKDIS_MASK 3
+#define CxDCLKDIS_ENABLE 3 /* Always enable both clock pairs. */
+
+/* On-Die-Termination registers (2x 32-bit per channel) */
+#define CxODT_HIGH(x) (0x124c + (x * 0x0100))
+#define CxODT_LOW(x) (0x1248 + (x * 0x0100))
+
+/* Write Training registers. */
+#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4))
+
+#define CxGTEW(x) (0x1270+(x*0x100))
+#define CxGTC(x) (0x1274+(x*0x100))
+#define CxDTPEW(x) (0x1278+(x*0x100))
+#define CxDTAEW(x) (0x1280+(x*0x100))
+#define CxDTC(x) (0x1288+(x*0x100))
+
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+#define DMIVC0RCTL 0x14
+#define DMIESD 0x44
+
+
+/*
+ * EPBAR
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+
+#ifndef __ASSEMBLER__
+void gm45_early_init(void);
+void gm45_early_reset(void);
+
+void enter_raminit_or_reset(void);
+void get_gmch_info(sysinfo_t *);
+void raminit_thermal(const sysinfo_t *);
+void init_igd(const sysinfo_t *, int no_igd, int no_peg);
+void init_pm(const sysinfo_t *);
+
+int raminit_read_vco_index(void);
+u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
+
+void raminit_rcomp_calibration(stepping_t stepping);
+void raminit_reset_readwrite_pointers(void);
+void raminit_receive_enable_calibration(const timings_t *, const dimminfo_t *);
+void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
+void raminit_read_training(const dimminfo_t *, int s3resume);
+
+void gm45_late_init(stepping_t);
+
+u32 decode_igd_memory_size(u32 gms);
+u32 decode_igd_gtt_size(u32 gsm);
+
+void init_iommu(void);
+#endif
+
+/* Chipset types */
+#define NEHALEM_MOBILE 0
+#define NEHALEM_DESKTOP 1
+#define NEHALEM_SERVER 2
+
+/* Intel Enhanced Debug region must be 4MB */
+#define IED_SIZE 0x400000
+
+/* Northbridge BARs */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+#define DEFAULT_RCBABASE 0xfed1c000
+
+#define QUICKPATH_BUS 0xff
+
+#include <southbridge/intel/ibexpeak/pch.h>
+
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+
+#define EPBAR 0x40
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define DMIBAR 0x68
+#define X60BAR 0x60
+
+#define LAC 0x87 /* Legacy Access Control */
+#define SMRAM 0x88 /* System Management RAM Control */
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+
+#define SKPAD 0xdc /* Scratchpad Data */
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+
+#define BCTRL1 0x3e /* 16bit */
+
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define MSAC 0x62 /* Multi Size Aperture Control */
+#define SWSCI 0xe8 /* SWSCI enable */
+#define ASLS 0xfc /* OpRegion Base */
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))
+
+#define SSKPD 0x5d14 /* 16bit (scratchpad) */
+#define BIOS_RESET_CPL 0x5da8 /* 8bit */
+
+/*
+ * EPBAR - Egress Port Root Complex Register Block
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+#define EPPVCCAP1 0x004 /* 32bit */
+#define EPPVCCAP2 0x008 /* 32bit */
+
+#define EPVC0RCAP 0x010 /* 32bit */
+#define EPVC0RCTL 0x014 /* 32bit */
+#define EPVC0RSTS 0x01a /* 16bit */
+
+#define EPVC1RCAP 0x01c /* 32bit */
+#define EPVC1RCTL 0x020 /* 32bit */
+#define EPVC1RSTS 0x026 /* 16bit */
+
+#define EPVC1MTS 0x028 /* 32bit */
+#define EPVC1IST 0x038 /* 64bit */
+
+#define EPESD 0x044 /* 32bit */
+
+#define EPLE1D 0x050 /* 32bit */
+#define EPLE1A 0x058 /* 64bit */
+#define EPLE2D 0x060 /* 32bit */
+#define EPLE2A 0x068 /* 64bit */
+
+#define PORTARB 0x100 /* 256bit */
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+#define DMIVCECH 0x000 /* 32bit */
+#define DMIPVCCAP1 0x004 /* 32bit */
+#define DMIPVCCAP2 0x008 /* 32bit */
+
+#define DMIPVCCCTL 0x00c /* 16bit */
+
+#define DMIVC0RCAP 0x010 /* 32bit */
+#define DMIVC0RCTL0 0x014 /* 32bit */
+#define DMIVC0RSTS 0x01a /* 16bit */
+
+#define DMIVC1RCAP 0x01c /* 32bit */
+#define DMIVC1RCTL 0x020 /* 32bit */
+#define DMIVC1RSTS 0x026 /* 16bit */
+
+#define DMILE1D 0x050 /* 32bit */
+#define DMILE1A 0x058 /* 64bit */
+#define DMILE2D 0x060 /* 32bit */
+#define DMILE2A 0x068 /* 64bit */
+
+#define DMILCAP 0x084 /* 32bit */
+#define DMILCTL 0x088 /* 16bit */
+#define DMILSTS 0x08a /* 16bit */
+
+#define DMICTL1 0x0f0 /* 32bit */
+#define DMICTL2 0x0fc /* 32bit */
+
+#define DMICC 0x208 /* 32bit */
+
+#define DMIDRCCFG 0xeb4 /* 32bit */
+
+#ifndef __ASSEMBLER__
+static inline void barrier(void) { asm("" ::: "memory"); }
+
+struct ied_header {
+ char signature[10];
+ u32 size;
+ u8 reserved[34];
+} __attribute__ ((packed));
+
+#define PCI_DEVICE_ID_SB 0x0104
+#define PCI_DEVICE_ID_IB 0x0154
+
+#ifdef __SMM__
+void intel_nehalem_finalize_smm(void);
+#else /* !__SMM__ */
+int bridge_silicon_revision(void);
+void nehalem_early_initialization(int chipset_type);
+void nehalem_late_initialization(void);
+
+/* debugging functions */
+void print_pci_devices(void);
+void dump_pci_device(unsigned dev);
+void dump_pci_devices(void);
+void dump_spd_registers(void);
+void dump_mem(unsigned start, unsigned end);
+void report_platform_info(void);
+#endif /* !__SMM__ */
+
+
+#define MRC_DATA_ALIGN 0x1000
+#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
+
+struct mrc_data_container {
+ u32 mrc_signature; // "MRCD"
+ u32 mrc_data_size; // Actual total size of this structure
+ u32 mrc_checksum; // IP style checksum
+ u32 reserved; // For header alignment
+ u8 mrc_data[0]; // Variable size, platform/run time dependent.
+} __attribute__ ((packed));
+
+struct mrc_data_container *find_current_mrc_cache(void);
+#if !defined(__PRE_RAM__)
+#include "gma.h"
+int init_igd_opregion(igd_opregion_t *igd_opregion);
+#endif
+
+#endif
+#endif
+#endif
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
new file mode 100644
index 0000000..41eec9c
--- /dev/null
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -0,0 +1,381 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <delay.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cbmem.h>
+#include "chip.h"
+#include "nehalem.h"
+
+static int bridge_revision_id = -1;
+
+int bridge_silicon_revision(void)
+{
+ if (bridge_revision_id < 0) {
+ uint8_t stepping = cpuid_eax(1) & 0xf;
+ uint8_t bridge_id =
+ pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
+ PCI_DEVICE_ID) & 0xf0;
+ bridge_revision_id = bridge_id | stepping;
+ }
+ return bridge_revision_id;
+}
+
+/* Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 384;
+
+static int get_pcie_bar(u32 * base, u32 * len)
+{
+ device_t dev;
+ u32 pciexbar_reg;
+
+ *base = 0;
+ *len = 0;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (!dev)
+ return 0;
+
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: // 256MB
+ *base =
+ pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28));
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: // 128M
+ *base =
+ pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27));
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: // 64M
+ *base =
+ pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27) | (1 << 26));
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+static void add_fixed_resources(struct device *dev, int index)
+{
+ struct resource *resource;
+ u32 pcie_config_base, pcie_config_size;
+
+ if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
+ "size=0x%x\n", pcie_config_base, pcie_config_size);
+ resource = new_resource(dev, index++);
+ resource->base = (resource_t) pcie_config_base;
+ resource->size = (resource_t) pcie_config_size;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ }
+
+ mmio_resource(dev, index++, legacy_hole_base_k,
+ (0xc0000 >> 10) - legacy_hole_base_k);
+ reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+ (0x100000 - 0xc0000) >> 10);
+
+#if CONFIG_CHROMEOS_RAMOOPS
+ reserved_ram_resource(dev, index++,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
+ CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
+#endif
+ bad_ram_resource(dev, index++, 0x1fc000000ULL >> 10, 0x004000000 >> 10);
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+ uint32_t tseg_base;
+ uint64_t TOUUD;
+ uint16_t reg16;
+
+ tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
+ TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
+ D0F0_TOUUD);
+
+ printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
+ printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD);
+
+ /* Report the memory regions */
+ ram_resource(dev, 3, 0, 640);
+ ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768));
+
+ /* Using uma_resource() here would fail as base & size cannot
+ * be used as-is for a single MTRR. This would cause excessive
+ * use of MTRRs.
+ *
+ * Use of mmio_resource() instead does not create UC holes by using
+ * MTRRs, but making these regions uncacheable is taken care of by
+ * making sure they do not overlap with any ram_resource().
+ *
+ * The resources can be changed to use separate mmio_resource()
+ * calls after MTRR code is able to merge them wisely.
+ */
+ mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10);
+
+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);
+ const int uma_sizes_gtt[16] =
+ { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
+ /* Igd memory */
+ const int uma_sizes_igd[16] = {
+ 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512
+ };
+ u32 igd_base, gtt_base;
+ int uma_size_igd, uma_size_gtt;
+
+ uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF];
+ uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF];
+
+ igd_base =
+ pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE);
+ gtt_base =
+ pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE);
+ mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10);
+ mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10);
+
+ if (TOUUD > 4096 + 256)
+ ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10));
+
+ add_fixed_resources(dev, 9);
+
+ assign_resources(dev->link_list);
+
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = tseg_base - HIGH_MEMORY_SIZE;
+ high_tables_size = HIGH_MEMORY_SIZE;
+}
+
+ /* TODO We could determine how many PCIe busses we need in
+ * the bar. For now that number is hardcoded to a max of 64.
+ * See e7525/northbridge.c for an example.
+ */
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+ .ops_pci_bus = &pci_ops_mmconf,
+#else
+ .ops_pci_bus = &pci_cf8_conf1,
+#endif
+};
+
+static void mc_read_resources(device_t dev)
+{
+ struct resource *resource;
+
+ pci_dev_read_resources(dev);
+
+ /* So, this is one of the big mysteries in the coreboot resource
+ * allocator. This resource should make sure that the address space
+ * of the PCIe memory mapped config space bar. But it does not.
+ */
+
+ /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
+ resource = new_resource(dev, 0xcf);
+ resource->base = DEFAULT_PCIEXBAR;
+ resource->size = 256 * 1024 * 1024; /* 64MB hard coded PCIe config space */
+ resource->flags =
+ IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_ASSIGNED;
+ printk(BIOS_DEBUG,
+ "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+ (unsigned long)(resource->base),
+ (unsigned long)(resource->base + resource->size));
+}
+
+static void mc_set_resources(device_t dev)
+{
+ struct resource *resource;
+
+ /* Report the PCIe BAR */
+ resource = find_resource(dev, 0xcf);
+ if (resource) {
+ report_resource_stored(dev, resource, "<mmconfig>");
+ }
+
+ /* And call the normal set_resources */
+ pci_dev_set_resources(dev);
+}
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor &
+ 0xffff));
+ }
+}
+
+static void northbridge_dmi_init(struct device *dev)
+{
+ u32 reg32;
+
+ /* Clear error status bits */
+ DMIBAR32(0x1c4) = 0xffffffff;
+ DMIBAR32(0x1d0) = 0xffffffff;
+
+ /* Steps prior to DMI ASPM */
+ reg32 = DMIBAR32(0x250);
+ reg32 &= ~((1 << 22) | (1 << 20));
+ reg32 |= (1 << 21);
+ DMIBAR32(0x250) = reg32;
+
+ reg32 = DMIBAR32(0x238);
+ reg32 |= (1 << 29);
+ DMIBAR32(0x238) = reg32;
+
+ /* Enable ASPM on SNB link, should happen before PCH link */
+ reg32 = DMIBAR32(0xd04);
+ reg32 |= (1 << 4);
+ DMIBAR32(0xd04) = reg32;
+
+ reg32 = DMIBAR32(0x88);
+ reg32 |= (1 << 1) | (1 << 0);
+ DMIBAR32(0x88) = reg32;
+}
+
+static void northbridge_init(struct device *dev)
+{
+ u8 bios_reset_cpl;
+
+ northbridge_dmi_init(dev);
+
+ /*
+ * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
+ * that BIOS has initialized memory and power management
+ */
+ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
+ bios_reset_cpl |= 1;
+ MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
+ printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
+
+ /* Configure turbo power limits 1ms after reset complete bit */
+ mdelay(1);
+}
+
+static void northbridge_enable(device_t dev)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+ switch (pci_read_config32(dev, SKPAD)) {
+ case 0xcafebabe:
+ printk(BIOS_DEBUG, "Normal boot.\n");
+ acpi_slp_type = 0;
+ break;
+ case 0xcafed00d:
+ printk(BIOS_DEBUG, "S3 Resume.\n");
+ acpi_slp_type = 3;
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
+ acpi_slp_type = 0;
+ break;
+ }
+#endif
+}
+
+static struct pci_operations intel_pci_ops = {
+ .set_subsystem = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+ .read_resources = mc_read_resources,
+ .set_resources = mc_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init,
+ .enable = northbridge_enable,
+ .scan_bus = 0,
+ .ops_pci = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver_44 __pci_driver = {
+ .ops = &mc_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x0044, /* Nehalem */
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(dev->link_list);
+ /* Enable ROM caching if option was selected. */
+ x86_mtrr_enable_rom_caching();
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static void enable_dev(device_t dev)
+{
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
+struct chip_operations northbridge_intel_nehalem_ops = {
+ CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge")
+ .enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/nehalem/pcie_config.c b/src/northbridge/intel/nehalem/pcie_config.c
new file mode 100644
index 0000000..04f8c9b
--- /dev/null
+++ b/src/northbridge/intel/nehalem/pcie_config.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "nehalem.h"
+
+static inline __attribute__ ((always_inline))
+u8 pcie_read_config8(device_t dev, unsigned int where)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ return read8(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u16 pcie_read_config16(device_t dev, unsigned int where)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ return read16(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u32 pcie_read_config32(device_t dev, unsigned int where)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ return read32(addr);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config8(device_t dev, unsigned int where, u8 value)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ write8(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config16(device_t dev, unsigned int where, u16 value)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ write16(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config32(device_t dev, unsigned int where, u32 value)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ write32(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
+{
+ u8 value = pcie_read_config8(dev, where);
+ pcie_write_config8(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
+{
+ u16 value = pcie_read_config16(dev, where);
+ pcie_write_config16(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
+{
+ u32 value = pcie_read_config32(dev, where);
+ pcie_write_config32(dev, where, value | ormask);
+}
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
new file mode 100644
index 0000000..f06f6b4
--- /dev/null
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -0,0 +1,5282 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef REAL
+#define REAL 1
+#endif
+
+#if REAL
+#include <console/console.h>
+#include <string.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cbmem.h>
+#include <arch/cbfs.h>
+#include <cbfs.h>
+#include <ip_checksum.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include <arch/cpu.h>
+#include <spd.h>
+#include "raminit.h"
+#include <timestamp.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#endif
+
+#if !REAL
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+typedef u32 device_t;
+#endif
+
+#include "nehalem.h"
+
+#include "southbridge/intel/ibexpeak/me.h"
+
+#if REAL
+#include <delay.h>
+#endif
+
+#define NORTHBRIDGE 0, 0, 0
+#define SOUTHBRIDGE 0, 0x1f, 0
+#define HECIDEV 0, 0x16, 0
+#define HECIBAR 0x10
+
+#define FOR_ALL_RANKS \
+ for (channel = 0; channel < NUM_CHANNELS; channel++) \
+ for (slot = 0; slot < NUM_SLOTS; slot++) \
+ for (rank = 0; rank < NUM_RANKS; rank++)
+
+#define FOR_POPULATED_RANKS \
+ for (channel = 0; channel < NUM_CHANNELS; channel++) \
+ for (slot = 0; slot < NUM_SLOTS; slot++) \
+ for (rank = 0; rank < NUM_RANKS; rank++) \
+ if (info->populated_ranks[channel][slot][rank])
+
+#define FOR_POPULATED_RANKS_BACKWARDS \
+ for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) \
+ for (slot = 0; slot < NUM_SLOTS; slot++) \
+ for (rank = 0; rank < NUM_RANKS; rank++) \
+ if (info->populated_ranks[channel][slot][rank])
+
+/* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */
+typedef struct {
+ u8 smallest;
+ u8 largest;
+} timing_bounds_t[2][2][2][9];
+
+struct ram_training {
+ /* [TM][CHANNEL][SLOT][RANK][LANE] */
+ u16 lane_timings[4][2][2][2][9];
+ u16 reg_178;
+ u16 reg_10b;
+
+ u8 reg178_center;
+ u8 reg178_smallest;
+ u8 reg178_largest;
+ timing_bounds_t timing_bounds[2];
+ u16 timing_offset[2][2][2][9];
+ u16 timing2_offset[2][2][2][9];
+ u16 timing2_bounds[2][2][2][9][2];
+};
+
+#if !REAL
+#include "raminit_fake.c"
+#else
+
+#include <lib.h> /* Prototypes */
+#include "pcie_config.c"
+
+static void my_write_msr(u32 addr, u64 val)
+{
+ msr_t msr = {.lo = val,.hi = val >> 32 };
+
+ wrmsr(addr, msr);
+}
+
+static inline void write_mchbar32(u32 addr, u32 val)
+{
+ MCHBAR32(addr) = val;
+}
+
+static inline void write_mchbar16(u32 addr, u16 val)
+{
+ MCHBAR16(addr) = val;
+}
+
+static inline void write_mchbar8(u32 addr, u8 val)
+{
+ MCHBAR8(addr) = val;
+}
+
+
+static inline u32 read_mchbar32(u32 addr)
+{
+ return MCHBAR32(addr);
+}
+
+static inline u16 read_mchbar16(u32 addr)
+{
+ return MCHBAR16(addr);
+}
+
+static inline u8 read_mchbar8(u32 addr)
+{
+ return MCHBAR8(addr);
+}
+
+static inline u8 read_mchbar8_bypass(u32 addr)
+{
+ return MCHBAR8(addr);
+}
+
+static void pci_write8(int bus, int dev, int func, u32 addr, u8 val)
+{
+ pci_write_config8(PCI_DEV(bus, dev, func), addr, val);
+}
+
+static void pci_mm_write8(int bus, int dev, int func, u32 addr, u8 val)
+{
+ pcie_write_config8(PCI_DEV(bus, dev, func), addr, val);
+}
+
+static void pci_mm_write16(int bus, int dev, int func, u32 addr, u16 val)
+{
+ pcie_write_config16(PCI_DEV(bus, dev, func), addr, val);
+}
+
+static void pci_mm_write32(int bus, int dev, int func, u32 addr, u32 val)
+{
+ pcie_write_config32(PCI_DEV(bus, dev, func), addr, val);
+}
+
+static u32 pci_mm_read32(int bus, int dev, int func, u32 addr)
+{
+ return pcie_read_config32(PCI_DEV(bus, dev, func), addr);
+}
+
+static u16 pci_mm_read16(int bus, int dev, int func, u32 addr)
+{
+ return pcie_read_config16(PCI_DEV(bus, dev, func), addr);
+}
+
+static u8 pci_mm_read8(int bus, int dev, int func, u32 addr)
+{
+ return pcie_read_config8(PCI_DEV(bus, dev, func), addr);
+}
+
+static void clflush(u32 addr)
+{
+ asm volatile ("clflush (%0)"::"r" (addr));
+}
+
+typedef struct _u128 {
+ u64 lo;
+ u64 hi;
+} u128;
+
+static void read128(u32 addr, u64 * out)
+{
+ u128 ret;
+ u128 stor;
+ asm volatile ("movdqu %%xmm0, %0\n"
+ "movdqa (%2), %%xmm0\n"
+ "movdqu %%xmm0, %1\n"
+ "movdqu %0, %%xmm0":"+m" (stor), "=m"(ret):"r"(addr));
+ out[0] = ret.lo;
+ out[1] = ret.hi;
+}
+
+static u64 my_read_msr(u32 addr)
+{
+ msr_t m = rdmsr(addr);
+ return (((u64) m.hi) << 32) | m.lo;
+}
+
+#endif
+
+/* OK */
+static void write_1d0(u32 val, u16 addr, int bits, int flag)
+{
+ write_mchbar32(0x1d0, 0);
+ while (read_mchbar32(0x1d0) & 0x800000) ;
+ write_mchbar32(0x1d4,
+ (val & ((1 << bits) - 1)) | (2 << bits) | (flag <<
+ bits));
+ write_mchbar32(0x1d0, 0x40000000 | addr);
+ while (read_mchbar32(0x1d0) & 0x800000) ;
+}
+
+/* OK */
+static u16 read_1d0(u16 addr, int split)
+{
+ u32 val;
+ write_mchbar32(0x1d0, 0);
+ while (read_mchbar32(0x1d0) & 0x800000) ;
+ write_mchbar32(0x1d0,
+ 0x80000000 | (((read_mchbar8(0x246) >> 2) & 3) +
+ 0x361 - addr));
+ while (read_mchbar32(0x1d0) & 0x800000) ;
+ val = read_mchbar32(0x1d8);
+ write_1d0(0, 0x33d, 0, 0);
+ write_1d0(0, 0x33d, 0, 0);
+ val &= ((1 << split) - 1);
+ // printk (BIOS_ERR, "R1D0C [%x] => %x\n", addr, val);
+ return val;
+}
+
+static void sfence(void)
+{
+#if REAL
+ asm volatile ("sfence");
+#endif
+}
+
+static inline u16 get_lane_offset(int slot, int rank, int lane)
+{
+ return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot -
+ 0x452 * (lane == 8);
+}
+
+static inline u16 get_timing_register_addr(int lane, int tm, int slot, int rank)
+{
+ const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
+ return get_lane_offset(slot, rank, lane) + offs[(tm + 3) % 4];
+}
+
+#if REAL
+static u32 gav_real(int line, u32 in)
+{
+ // printk (BIOS_DEBUG, "%d: GAV: %x\n", line, in);
+ return in;
+}
+
+#define gav(x) gav_real (__LINE__, (x))
+#endif
+struct raminfo {
+ u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */
+ u16 fsb_frequency; /* in 1.(1)/2 MHz. */
+ u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */
+ u8 density[2][2]; /* [CHANNEL][SLOT] */
+ u8 populated_ranks[2][2][2]; /* [CHANNEL][SLOT][RANK] */
+ int rank_start[2][2][2];
+ u8 cas_latency;
+ u8 board_lane_delay[9];
+ u8 use_ecc;
+ u8 revision;
+ u8 max_supported_clock_speed_index;
+ u8 uma_enabled;
+ u8 spd[2][2][151]; /* [CHANNEL][SLOT][BYTE] */
+ u8 silicon_revision;
+ u8 populated_ranks_mask[2];
+ u8 max_slots_used_in_channel;
+ u8 mode4030[2];
+ u16 avg4044[2];
+ u16 max4048[2];
+ unsigned total_memory_mb;
+ unsigned interleaved_part_mb;
+ unsigned non_interleaved_part_mb;
+
+ u32 heci_bar;
+ u64 heci_uma_addr;
+ unsigned memory_reserved_for_heci_mb;
+
+ struct ram_training training;
+ u32 last_500_command[2];
+
+ u8 reg2ca9_bit0;
+ u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */
+ u32 delay46_ps[2];
+ u32 delay54_ps[2];
+ u8 revision_flag_1;
+ u8 some_delay_1_cycle_floor;
+ u8 some_delay_2_halfcycles_ceil;
+ u8 some_delay_3_ps_rounded;
+
+ const struct ram_training *cached_training;
+};
+
+static void
+write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
+ int flag);
+
+/* OK */
+static u16
+read_500(struct raminfo *info, int channel, u16 addr, int split)
+{
+ u32 val;
+ info->last_500_command[channel] = 0x80000000;
+ write_mchbar32(0x500 + (channel << 10), 0);
+ while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+ write_mchbar32(0x500 + (channel << 10),
+ 0x80000000 |
+ (((read_mchbar8(0x246 + (channel << 10)) >> 2) &
+ 3) + 0xb88 - addr));
+ while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+ val = read_mchbar32(0x508 + (channel << 10));
+ return val & ((1 << split) - 1);
+}
+
+/* OK */
+static void
+write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
+ int flag)
+{
+ if (info->last_500_command[channel] == 0x80000000) {
+ info->last_500_command[channel] = 0x40000000;
+ write_500(info, channel, 0, 0xb61, 0, 0);
+ }
+ write_mchbar32(0x500 + (channel << 10), 0);
+ while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+ write_mchbar32(0x504 + (channel << 10),
+ (val & ((1 << bits) - 1)) | (2 << bits) | (flag <<
+ bits));
+ write_mchbar32(0x500 + (channel << 10), 0x40000000 | addr);
+ while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ;
+}
+
+static int rw_test(int rank)
+{
+ const u32 mask = 0xf00fc33c;
+ int ok = 0xff;
+ int i;
+ for (i = 0; i < 64; i++)
+ write32((rank << 28) | (i << 2), 0);
+ sfence();
+ for (i = 0; i < 64; i++)
+ gav(read32((rank << 28) | (i << 2)));
+ sfence();
+ for (i = 0; i < 32; i++) {
+ u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0);
+ write32((rank << 28) | (i << 3), pat);
+ write32((rank << 28) | (i << 3) | 4, pat);
+ }
+ sfence();
+ for (i = 0; i < 32; i++) {
+ u8 pat = (((mask >> i) & 1) ? 0xff : 0);
+ int j;
+ u32 val;
+ gav(val = read32((rank << 28) | (i << 3)));
+ for (j = 0; j < 4; j++)
+ if (((val >> (j * 8)) & 0xff) != pat)
+ ok &= ~(1 << j);
+ gav(val = read32((rank << 28) | (i << 3) | 4));
+ for (j = 0; j < 4; j++)
+ if (((val >> (j * 8)) & 0xff) != pat)
+ ok &= ~(16 << j);
+ }
+ sfence();
+ for (i = 0; i < 64; i++)
+ write32((rank << 28) | (i << 2), 0);
+ sfence();
+ for (i = 0; i < 64; i++)
+ gav(read32((rank << 28) | (i << 2)));
+
+ return ok;
+}
+
+static void
+program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank)
+{
+ int lane;
+ for (lane = 0; lane < 8; lane++) {
+ write_500(info, channel,
+ base +
+ info->training.
+ lane_timings[2][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 2, slot, rank), 9, 0);
+ write_500(info, channel,
+ base +
+ info->training.
+ lane_timings[3][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 3, slot, rank), 9, 0);
+ }
+}
+
+static void write_26c(int channel, u16 si)
+{
+ write_mchbar32(0x26c + (channel << 10), 0x03243f35);
+ write_mchbar32(0x268 + (channel << 10), 0xcfc00000 | (si << 9));
+ write_mchbar16(0x2b9 + (channel << 10), si);
+}
+
+static u32 get_580(int channel, u8 addr)
+{
+ u32 ret;
+ gav(read_1d0(0x142, 3));
+ write_mchbar8(0x5ff, 0x0); /* OK */
+ write_mchbar8(0x5ff, 0x80); /* OK */
+ write_mchbar32(0x580 + (channel << 10), 0x8493c012 | addr);
+ write_mchbar8(0x580 + (channel << 10),
+ read_mchbar8(0x580 + (channel << 10)) | 1);
+ while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)) ;
+ write_mchbar8(0x580 + (channel << 10),
+ read_mchbar8(0x580 + (channel << 10)) & ~1);
+ return ret;
+}
+
+const int cached_config = 0;
+
+#define NUM_CHANNELS 2
+#define NUM_SLOTS 2
+#define NUM_RANKS 2
+#define RANK_SHIFT 28
+#define CHANNEL_SHIFT 10
+
+#include "raminit_tables.c"
+
+static void seq9(struct raminfo *info, int channel, int slot, int rank)
+{
+ int i, lane;
+
+ for (i = 0; i < 2; i++)
+ for (lane = 0; lane < 8; lane++)
+ write_500(info, channel,
+ info->training.lane_timings[i +
+ 1][channel][slot]
+ [rank][lane], get_timing_register_addr(lane,
+ i + 1,
+ slot,
+ rank),
+ 9, 0);
+
+ write_1d0(1, 0x103, 6, 1);
+ for (lane = 0; lane < 8; lane++)
+ write_500(info, channel,
+ info->training.
+ lane_timings[0][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 0, slot, rank), 9, 0);
+
+ for (i = 0; i < 2; i++) {
+ for (lane = 0; lane < 8; lane++)
+ write_500(info, channel,
+ info->training.lane_timings[i +
+ 1][channel][slot]
+ [rank][lane], get_timing_register_addr(lane,
+ i + 1,
+ slot,
+ rank),
+ 9, 0);
+ gav(get_580(channel, ((i + 1) << 2) | (rank << 5)));
+ }
+
+ gav(read_1d0(0x142, 3)); // = 0x10408118
+ write_mchbar8(0x5ff, 0x0); /* OK */
+ write_mchbar8(0x5ff, 0x80); /* OK */
+ write_1d0(0x2, 0x142, 3, 1);
+ for (lane = 0; lane < 8; lane++) {
+ // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]);
+ info->training.lane_timings[2][channel][slot][rank][lane] =
+ read_500(info, channel,
+ get_timing_register_addr(lane, 2, slot, rank), 9);
+ //printk (BIOS_ERR, "after: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]);
+ info->training.lane_timings[3][channel][slot][rank][lane] =
+ info->training.lane_timings[2][channel][slot][rank][lane] +
+ 0x20;
+ }
+}
+
+static int count_ranks_in_channel(struct raminfo *info, int channel)
+{
+ int slot, rank;
+ int res = 0;
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_SLOTS; rank++)
+ res += info->populated_ranks[channel][slot][rank];
+ return res;
+}
+
+static void
+config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank)
+{
+ int add;
+
+ write_1d0(0, 0x178, 7, 1);
+ seq9(info, channel, slot, rank);
+ program_timings(info, 0x80, channel, slot, rank);
+
+ if (channel == 0)
+ add = count_ranks_in_channel(info, 1);
+ else
+ add = 0;
+ if (!s3resume)
+ gav(rw_test(rank + add));
+ program_timings(info, 0x00, channel, slot, rank);
+ if (!s3resume)
+ gav(rw_test(rank + add));
+ if (!s3resume)
+ gav(rw_test(rank + add));
+ write_1d0(0, 0x142, 3, 1);
+ write_1d0(0, 0x103, 6, 1);
+
+ gav(get_580(channel, 0xc | (rank << 5)));
+ gav(read_1d0(0x142, 3));
+
+ write_mchbar8(0x5ff, 0x0); /* OK */
+ write_mchbar8(0x5ff, 0x80); /* OK */
+}
+
+static void set_4cf(struct raminfo *info, int channel, u8 val)
+{
+ gav(read_500(info, channel, 0x4cf, 4)); // = 0xc2300cf9
+ write_500(info, channel, val, 0x4cf, 4, 1);
+ gav(read_500(info, channel, 0x659, 4)); // = 0x80300839
+ write_500(info, channel, val, 0x659, 4, 1);
+ gav(read_500(info, channel, 0x697, 4)); // = 0x80300839
+ write_500(info, channel, val, 0x697, 4, 1);
+}
+
+static void set_334(int zero)
+{
+ int j, k, channel;
+ const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b };
+ u32 vd8[2][16];
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ for (j = 0; j < 4; j++) {
+ u32 a = (j == 1) ? 0x29292929 : 0x31313131;
+ u32 lmask = (j == 3) ? 0xffff : 0xffffffff;
+ u16 c;
+ if ((j == 0 || j == 3) && zero)
+ c = 0;
+ else if (j == 3)
+ c = 0x5f;
+ else
+ c = 0x5f5f;
+
+ for (k = 0; k < 2; k++) {
+ write_mchbar32(0x138 + 8 * k,
+ (channel << 26) | (j << 24));
+ gav(vd8[1][(channel << 3) | (j << 1) | k] =
+ read_mchbar32(0x138 + 8 * k));
+ gav(vd8[0][(channel << 3) | (j << 1) | k] =
+ read_mchbar32(0x13c + 8 * k));
+ }
+
+ write_mchbar32(0x334 + (channel << 10) + (j * 0x44),
+ zero ? 0 : val3[j]);
+ write_mchbar32(0x32c + (channel << 10) + (j * 0x44),
+ zero ? 0 : (0x18191819 & lmask));
+ write_mchbar16(0x34a + (channel << 10) + (j * 0x44), c);
+ write_mchbar32(0x33c + (channel << 10) + (j * 0x44),
+ zero ? 0 : (a & lmask));
+ write_mchbar32(0x344 + (channel << 10) + (j * 0x44),
+ zero ? 0 : (a & lmask));
+ }
+ }
+
+ write_mchbar32(0x130, read_mchbar32(0x130) | 1); /* OK */
+ while (read_mchbar8(0x130) & 1) ; /* OK */
+}
+
+static void rmw_1d0(u16 addr, u32 and, u32 or, int split, int flag)
+{
+ u32 v;
+ v = read_1d0(addr, split);
+ write_1d0((v & and) | or, addr, split, flag);
+}
+
+static int find_highest_bit_set(u16 val)
+{
+ int i;
+ for (i = 15; i >= 0; i--)
+ if (val & (1 << i))
+ return i;
+ return -1;
+}
+
+static int find_lowest_bit_set32(u32 val)
+{
+ int i;
+ for (i = 0; i < 32; i++)
+ if (val & (1 << i))
+ return i;
+ return -1;
+}
+
+#define max(a,b) (((a) > (b)) ? (a) : (b))
+#define min(a,b) (((a) < (b)) ? (a) : (b))
+
+enum {
+ DEVICE_TYPE = 2,
+ MODULE_TYPE = 3,
+ DENSITY = 4,
+ RANKS_AND_DQ = 7,
+ MEMORY_BUS_WIDTH = 8,
+ TIMEBASE_DIVIDEND = 10,
+ TIMEBASE_DIVISOR = 11,
+ CYCLETIME = 12,
+
+ CAS_LATENCIES_LSB = 14,
+ CAS_LATENCIES_MSB = 15,
+ CAS_LATENCY_TIME = 16,
+ THERMAL_AND_REFRESH = 31,
+ REFERENCE_RAW_CARD_USED = 62,
+ RANK1_ADDRESS_MAPPING = 63
+};
+
+static void calculate_timings(struct raminfo *info)
+{
+ unsigned cycletime;
+ unsigned cas_latency_time;
+ unsigned supported_cas_latencies;
+ unsigned channel, slot;
+ unsigned clock_speed_index;
+ unsigned min_cas_latency;
+ unsigned cas_latency;
+ unsigned max_clock_index;
+
+ /* Find common CAS latency */
+ supported_cas_latencies = 0x3fe;
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ if (info->populated_ranks[channel][slot][0])
+ supported_cas_latencies &=
+ 2 *
+ (info->
+ spd[channel][slot][CAS_LATENCIES_LSB] |
+ (info->
+ spd[channel][slot][CAS_LATENCIES_MSB] <<
+ 8));
+
+ max_clock_index = min(3, info->max_supported_clock_speed_index);
+
+ cycletime = min_cycletime[max_clock_index];
+ cas_latency_time = min_cas_latency_time[max_clock_index];
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ if (info->populated_ranks[channel][slot][0]) {
+ unsigned timebase;
+ timebase =
+ 1000 *
+ info->
+ spd[channel][slot][TIMEBASE_DIVIDEND] /
+ info->spd[channel][slot][TIMEBASE_DIVISOR];
+ cycletime =
+ max(cycletime,
+ timebase *
+ info->spd[channel][slot][CYCLETIME]);
+ cas_latency_time =
+ max(cas_latency_time,
+ timebase *
+ info->
+ spd[channel][slot][CAS_LATENCY_TIME]);
+ }
+ for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) {
+ if (cycletime == min_cycletime[clock_speed_index])
+ break;
+ if (cycletime > min_cycletime[clock_speed_index]) {
+ clock_speed_index--;
+ cycletime = min_cycletime[clock_speed_index];
+ break;
+ }
+ }
+ min_cas_latency = (cas_latency_time + cycletime - 1) / cycletime;
+ cas_latency = 0;
+ while (supported_cas_latencies) {
+ cas_latency = find_highest_bit_set(supported_cas_latencies) + 3;
+ if (cas_latency <= min_cas_latency)
+ break;
+ supported_cas_latencies &=
+ ~(1 << find_highest_bit_set(supported_cas_latencies));
+ }
+
+ if (cas_latency != min_cas_latency && clock_speed_index)
+ clock_speed_index--;
+
+ if (cas_latency * min_cycletime[clock_speed_index] > 20000)
+ die("Couldn't configure DRAM");
+ info->clock_speed_index = clock_speed_index;
+ info->cas_latency = cas_latency;
+}
+
+static void program_base_timings(struct raminfo *info)
+{
+ unsigned channel;
+ unsigned slot, rank, lane;
+ unsigned extended_silicon_revision;
+ int i;
+
+ extended_silicon_revision = info->silicon_revision;
+ if (info->silicon_revision == 0)
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ if ((info->
+ spd[channel][slot][MODULE_TYPE] & 0xF) ==
+ 3)
+ extended_silicon_revision = 4;
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_SLOTS; rank++) {
+ int card_timing_2;
+ if (!info->populated_ranks[channel][slot][rank])
+ continue;
+
+ for (lane = 0; lane < 9; lane++) {
+ int tm_reg;
+ int card_timing;
+
+ card_timing = 0;
+ if ((info->
+ spd[channel][slot][MODULE_TYPE] &
+ 0xF) == 3) {
+ int reference_card;
+ reference_card =
+ info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] &
+ 0x1f;
+ if (reference_card == 3)
+ card_timing =
+ u16_ffd1188[0][lane]
+ [info->
+ clock_speed_index];
+ if (reference_card == 5)
+ card_timing =
+ u16_ffd1188[1][lane]
+ [info->
+ clock_speed_index];
+ }
+
+ info->training.
+ lane_timings[0][channel][slot][rank]
+ [lane] =
+ u8_FFFD1218[info->
+ clock_speed_index];
+ info->training.
+ lane_timings[1][channel][slot][rank]
+ [lane] = 256;
+
+ for (tm_reg = 2; tm_reg < 4; tm_reg++)
+ info->training.
+ lane_timings[tm_reg]
+ [channel][slot][rank][lane]
+ =
+ u8_FFFD1240[channel]
+ [extended_silicon_revision]
+ [lane][2 * slot +
+ rank][info->
+ clock_speed_index]
+ + info->max4048[channel]
+ +
+ u8_FFFD0C78[channel]
+ [extended_silicon_revision]
+ [info->
+ mode4030[channel]][slot]
+ [rank][info->
+ clock_speed_index]
+ + card_timing;
+ for (tm_reg = 0; tm_reg < 4; tm_reg++)
+ write_500(info, channel,
+ info->training.
+ lane_timings[tm_reg]
+ [channel][slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, tm_reg, slot,
+ rank), 9, 0);
+ }
+
+ card_timing_2 = 0;
+ if (!(extended_silicon_revision != 4
+ || (info->
+ populated_ranks_mask[channel] & 5) ==
+ 5)) {
+ if ((info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] & 0x1F)
+ == 3)
+ card_timing_2 =
+ u16_FFFE0EB8[0][info->
+ clock_speed_index];
+ if ((info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] & 0x1F)
+ == 5)
+ card_timing_2 =
+ u16_FFFE0EB8[1][info->
+ clock_speed_index];
+ }
+
+ for (i = 0; i < 3; i++)
+ write_500(info, channel,
+ (card_timing_2 +
+ info->max4048[channel]
+ +
+ u8_FFFD0EF8[channel]
+ [extended_silicon_revision]
+ [info->
+ mode4030[channel]][info->
+ clock_speed_index]),
+ u16_fffd0c50[i][slot][rank],
+ 8, 1);
+ write_500(info, channel,
+ (info->max4048[channel] +
+ u8_FFFD0C78[channel]
+ [extended_silicon_revision][info->
+ mode4030
+ [channel]]
+ [slot][rank][info->
+ clock_speed_index]),
+ u16_fffd0c70[slot][rank], 7, 1);
+ }
+ if (!info->populated_ranks_mask[channel])
+ continue;
+ for (i = 0; i < 3; i++)
+ write_500(info, channel,
+ (info->max4048[channel] +
+ info->avg4044[channel]
+ +
+ u8_FFFD17E0[channel]
+ [extended_silicon_revision][info->
+ mode4030
+ [channel]][info->
+ clock_speed_index]),
+ u16_fffd0c68[i], 8, 1);
+ }
+}
+
+static unsigned int fsbcycle_ps(struct raminfo *info)
+{
+ return 900000 / info->fsb_frequency;
+}
+
+/* The time of DDR transfer in ps. */
+static unsigned int halfcycle_ps(struct raminfo *info)
+{
+ return 3750 / (info->clock_speed_index + 3);
+}
+
+/* The time of clock cycle in ps. */
+static unsigned int cycle_ps(struct raminfo *info)
+{
+ return 2 * halfcycle_ps(info);
+}
+
+/* Frequency in 1.(1)=10/9 MHz units. */
+static unsigned frequency_11(struct raminfo *info)
+{
+ return (info->clock_speed_index + 3) * 120;
+}
+
+/* Frequency in 0.1 MHz units. */
+static unsigned frequency_01(struct raminfo *info)
+{
+ return 100 * frequency_11(info) / 9;
+}
+
+static unsigned ps_to_halfcycles(struct raminfo *info, unsigned int ps)
+{
+ return (frequency_11(info) * 2) * ps / 900000;
+}
+
+static unsigned ns_to_cycles(struct raminfo *info, unsigned int ns)
+{
+ return (frequency_11(info)) * ns / 900;
+}
+
+static void compute_derived_timings(struct raminfo *info)
+{
+ unsigned channel, slot, rank;
+ int extended_silicon_revision;
+ int some_delay_1_ps;
+ int some_delay_2_ps;
+ int some_delay_2_halfcycles_ceil;
+ int some_delay_2_halfcycles_floor;
+ int some_delay_3_ps;
+ int some_delay_3_halfcycles;
+ int some_delay_3_ps_rounded;
+ int some_delay_1_cycle_ceil;
+ int some_delay_1_cycle_floor;
+
+ some_delay_3_halfcycles = 0;
+ some_delay_3_ps_rounded = 0;
+ extended_silicon_revision = info->silicon_revision;
+ if (!info->silicon_revision)
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ if ((info->
+ spd[channel][slot][MODULE_TYPE] & 0xF) ==
+ 3)
+ extended_silicon_revision = 4;
+ if (info->board_lane_delay[7] < 5)
+ info->board_lane_delay[7] = 5;
+ info->revision_flag_1 = 2;
+ if (info->silicon_revision == 2 || info->silicon_revision == 3)
+ info->revision_flag_1 = 0;
+ if (info->revision < 16)
+ info->revision_flag_1 = 0;
+
+ if (info->revision < 8)
+ info->revision_flag_1 = 0;
+ if (info->revision >= 8 && (info->silicon_revision == 0
+ || info->silicon_revision == 1))
+ some_delay_2_ps = 735;
+ else
+ some_delay_2_ps = 750;
+
+ if (info->revision >= 0x10 && (info->silicon_revision == 0
+ || info->silicon_revision == 1))
+ some_delay_1_ps = 3929;
+ else
+ some_delay_1_ps = 3490;
+
+ some_delay_1_cycle_floor = some_delay_1_ps / cycle_ps(info);
+ some_delay_1_cycle_ceil = some_delay_1_ps / cycle_ps(info);
+ if (some_delay_1_ps % cycle_ps(info))
+ some_delay_1_cycle_ceil++;
+ else
+ some_delay_1_cycle_floor--;
+ info->some_delay_1_cycle_floor = some_delay_1_cycle_floor;
+ if (info->revision_flag_1)
+ some_delay_2_ps = halfcycle_ps(info) >> 6;
+ some_delay_2_ps +=
+ max(some_delay_1_ps - 30,
+ 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) +
+ 375;
+ some_delay_3_ps =
+ halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info);
+ if (info->revision_flag_1) {
+ if (some_delay_3_ps < 150)
+ some_delay_3_halfcycles = 0;
+ else
+ some_delay_3_halfcycles =
+ (some_delay_3_ps << 6) / halfcycle_ps(info);
+ some_delay_3_ps_rounded =
+ halfcycle_ps(info) * some_delay_3_halfcycles >> 6;
+ }
+ some_delay_2_halfcycles_ceil =
+ (some_delay_2_ps + halfcycle_ps(info) - 1) / halfcycle_ps(info) -
+ 2 * (some_delay_1_cycle_ceil - 1);
+ if (info->revision_flag_1 && some_delay_3_ps < 150)
+ some_delay_2_halfcycles_ceil++;
+ some_delay_2_halfcycles_floor = some_delay_2_halfcycles_ceil;
+ if (info->revision < 0x10)
+ some_delay_2_halfcycles_floor =
+ some_delay_2_halfcycles_ceil - 1;
+ if (!info->revision_flag_1)
+ some_delay_2_halfcycles_floor++;
+ info->some_delay_2_halfcycles_ceil = some_delay_2_halfcycles_ceil;
+ info->some_delay_3_ps_rounded = some_delay_3_ps_rounded;
+ if ((info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0])
+ || (info->populated_ranks[1][0][0]
+ && info->populated_ranks[1][1][0]))
+ info->max_slots_used_in_channel = 2;
+ else
+ info->max_slots_used_in_channel = 1;
+ for (channel = 0; channel < 2; channel++)
+ write_mchbar32(0x244 + (channel << 10),
+ ((info->revision < 8) ? 1 : 0x200)
+ | ((2 - info->max_slots_used_in_channel) << 17) |
+ (channel << 21) | (info->
+ some_delay_1_cycle_floor <<
+ 18) | 0x9510);
+ if (info->max_slots_used_in_channel == 1) {
+ info->mode4030[0] = (count_ranks_in_channel(info, 0) == 2);
+ info->mode4030[1] = (count_ranks_in_channel(info, 1) == 2);
+ } else {
+ info->mode4030[0] = ((count_ranks_in_channel(info, 0) == 1) || (count_ranks_in_channel(info, 0) == 2)) ? 2 : 3; /* 2 if 1 or 2 ranks */
+ info->mode4030[1] = ((count_ranks_in_channel(info, 1) == 1)
+ || (count_ranks_in_channel(info, 1) ==
+ 2)) ? 2 : 3;
+ }
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ int max_of_unk;
+ int min_of_unk_2;
+
+ int i, count;
+ int sum;
+
+ if (!info->populated_ranks_mask[channel])
+ continue;
+
+ max_of_unk = 0;
+ min_of_unk_2 = 32767;
+
+ sum = 0;
+ count = 0;
+ for (i = 0; i < 3; i++) {
+ int unk1;
+ if (info->revision < 8)
+ unk1 =
+ u8_FFFD1891[0][channel][info->
+ clock_speed_index]
+ [i];
+ else if (!
+ (info->revision >= 0x10
+ || info->revision_flag_1))
+ unk1 =
+ u8_FFFD1891[1][channel][info->
+ clock_speed_index]
+ [i];
+ else
+ unk1 = 0;
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++) {
+ int a = 0;
+ int b = 0;
+
+ if (!info->
+ populated_ranks[channel][slot]
+ [rank])
+ continue;
+ if (extended_silicon_revision == 4
+ && (info->
+ populated_ranks_mask[channel] &
+ 5) != 5) {
+ if ((info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] &
+ 0x1F) == 3) {
+ a = u16_ffd1178[0]
+ [info->
+ clock_speed_index];
+ b = u16_fe0eb8[0][info->
+ clock_speed_index];
+ } else
+ if ((info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED]
+ & 0x1F) == 5) {
+ a = u16_ffd1178[1]
+ [info->
+ clock_speed_index];
+ b = u16_fe0eb8[1][info->
+ clock_speed_index];
+ }
+ }
+ min_of_unk_2 = min(min_of_unk_2, a);
+ min_of_unk_2 = min(min_of_unk_2, b);
+ if (rank == 0) {
+ sum += a;
+ count++;
+ }
+ {
+ int t;
+ t = b +
+ u8_FFFD0EF8[channel]
+ [extended_silicon_revision]
+ [info->
+ mode4030[channel]][info->
+ clock_speed_index];
+ if (unk1 >= t)
+ max_of_unk =
+ max(max_of_unk,
+ unk1 - t);
+ }
+ }
+ {
+ int t =
+ u8_FFFD17E0[channel]
+ [extended_silicon_revision][info->
+ mode4030
+ [channel]]
+ [info->clock_speed_index] + min_of_unk_2;
+ if (unk1 >= t)
+ max_of_unk = max(max_of_unk, unk1 - t);
+ }
+ }
+
+ info->avg4044[channel] = sum / count;
+ info->max4048[channel] = max_of_unk;
+ }
+}
+
+static void jedec_read(struct raminfo *info,
+ int channel, int slot, int rank,
+ int total_rank, u8 addr3, unsigned int value)
+{
+ /* Handle mirrored mapping. */
+ if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
+ addr3 =
+ (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | ((addr3 >> 1) &
+ 0x10);
+ write_mchbar8(0x271, addr3 | (read_mchbar8(0x271) & 0xC1));
+ write_mchbar8(0x671, addr3 | (read_mchbar8(0x671) & 0xC1));
+
+ /* Handle mirrored mapping. */
+ if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
+ value =
+ (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8)
+ << 1);
+
+ read32((value << 3) | (total_rank << 28));
+
+ write_mchbar8(0x271, (read_mchbar8(0x271) & 0xC3) | 2);
+ write_mchbar8(0x671, (read_mchbar8(0x671) & 0xC3) | 2);
+
+ read32(total_rank << 28);
+}
+
+enum {
+ MR1_RZQ12 = 512,
+ MR1_RZQ2 = 64,
+ MR1_RZQ4 = 4,
+ MR1_ODS34OHM = 2
+};
+
+enum {
+ MR0_BT_INTERLEAVED = 8,
+ MR0_DLL_RESET_ON = 256
+};
+
+enum {
+ MR2_RTT_WR_DISABLED = 0,
+ MR2_RZQ2 = 1 << 10
+};
+
+static void jedec_init(struct raminfo *info)
+{
+ int write_recovery;
+ int channel, slot, rank;
+ int total_rank;
+ int dll_on;
+ int self_refresh_temperature;
+ int auto_self_refresh;
+
+ auto_self_refresh = 1;
+ self_refresh_temperature = 1;
+ if (info->board_lane_delay[3] <= 10) {
+ if (info->board_lane_delay[3] <= 8)
+ write_recovery = info->board_lane_delay[3] - 4;
+ else
+ write_recovery = 5;
+ } else {
+ write_recovery = 6;
+ }
+ FOR_POPULATED_RANKS {
+ auto_self_refresh &=
+ (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1;
+ self_refresh_temperature &=
+ info->spd[channel][slot][THERMAL_AND_REFRESH] & 1;
+ }
+ if (auto_self_refresh == 1)
+ self_refresh_temperature = 0;
+
+ dll_on = ((info->silicon_revision != 2 && info->silicon_revision != 3)
+ || (info->populated_ranks[0][0][0]
+ && info->populated_ranks[0][1][0])
+ || (info->populated_ranks[1][0][0]
+ && info->populated_ranks[1][1][0]));
+
+ total_rank = 0;
+
+ for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) {
+ int rtt, rtt_wr = MR2_RTT_WR_DISABLED;
+ int rzq_reg58e;
+
+ if (info->silicon_revision == 2 || info->silicon_revision == 3) {
+ rzq_reg58e = 64;
+ rtt = MR1_RZQ2;
+ if (info->clock_speed_index != 0) {
+ rzq_reg58e = 4;
+ if (info->populated_ranks_mask[channel] == 3)
+ rtt = MR1_RZQ4;
+ }
+ } else {
+ if ((info->populated_ranks_mask[channel] & 5) == 5) {
+ rtt = MR1_RZQ12;
+ rzq_reg58e = 64;
+ rtt_wr = MR2_RZQ2;
+ } else {
+ rzq_reg58e = 4;
+ rtt = MR1_RZQ4;
+ }
+ }
+
+ write_mchbar16(0x588 + (channel << 10), 0x0);
+ write_mchbar16(0x58a + (channel << 10), 0x4);
+ write_mchbar16(0x58c + (channel << 10), rtt | MR1_ODS34OHM);
+ write_mchbar16(0x58e + (channel << 10), rzq_reg58e | 0x82);
+ write_mchbar16(0x590 + (channel << 10), 0x1282);
+
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ if (info->populated_ranks[channel][slot][rank]) {
+ jedec_read(info, channel, slot, rank,
+ total_rank, 0x28,
+ rtt_wr | (info->
+ clock_speed_index
+ << 3)
+ | (auto_self_refresh << 6) |
+ (self_refresh_temperature <<
+ 7));
+ jedec_read(info, channel, slot, rank,
+ total_rank, 0x38, 0);
+ jedec_read(info, channel, slot, rank,
+ total_rank, 0x18,
+ rtt | MR1_ODS34OHM);
+ jedec_read(info, channel, slot, rank,
+ total_rank, 6,
+ (dll_on << 12) |
+ (write_recovery << 9)
+ | ((info->cas_latency - 4) <<
+ 4) | MR0_BT_INTERLEAVED |
+ MR0_DLL_RESET_ON);
+ total_rank++;
+ }
+ }
+}
+
+static void program_modules_memory_map(struct raminfo *info, int pre_jedec)
+{
+ unsigned channel, slot, rank;
+ unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */
+ unsigned int channel_0_non_interleaved;
+
+ FOR_ALL_RANKS {
+ if (info->populated_ranks[channel][slot][rank]) {
+ total_mb[channel] +=
+ pre_jedec ? 256 : (256 << info->
+ density[channel][slot] >> info->
+ is_x16_module[channel][slot]);
+ write_mchbar8(0x208 + rank + 2 * slot + (channel << 10),
+ (pre_jedec ? (1 | ((1 + 1) << 1))
+ : (info->
+ is_x16_module[channel][slot] |
+ ((info->density[channel][slot] +
+ 1) << 1))) | 0x80);
+ }
+ write_mchbar16(0x200 + (channel << 10) + 4 * slot + 2 * rank,
+ total_mb[channel] >> 6);
+ }
+
+ info->total_memory_mb = total_mb[0] + total_mb[1];
+
+ info->interleaved_part_mb =
+ pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]);
+ info->non_interleaved_part_mb =
+ total_mb[0] + total_mb[1] - info->interleaved_part_mb;
+ channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2;
+ write_mchbar32(0x100,
+ channel_0_non_interleaved | (info->
+ non_interleaved_part_mb <<
+ 16));
+ if (!pre_jedec)
+ write_mchbar16(0x104, info->interleaved_part_mb);
+}
+
+static void program_board_delay(struct raminfo *info)
+{
+ int cas_latency_shift;
+ int some_delay_ns;
+ int some_delay_3_half_cycles;
+
+ unsigned channel, i;
+ int high_multiplier;
+ int lane_3_delay;
+ int cas_latency_derived;
+
+ high_multiplier = 0;
+ some_delay_ns = 200;
+ some_delay_3_half_cycles = 4;
+ cas_latency_shift = info->silicon_revision == 0
+ || info->silicon_revision == 1 ? 1 : 0;
+ if (info->revision < 8) {
+ some_delay_ns = 600;
+ cas_latency_shift = 0;
+ }
+ {
+ int speed_bit;
+ speed_bit =
+ ((info->clock_speed_index > 1
+ || (info->silicon_revision != 2
+ && info->silicon_revision != 3))) ^ (info->revision >=
+ 0x10);
+ write_500(info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e,
+ 3, 1);
+ write_500(info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e,
+ 3, 1);
+ if (info->revision >= 0x10 && info->clock_speed_index <= 1
+ && (info->silicon_revision == 2
+ || info->silicon_revision == 3))
+ rmw_1d0(0x116, 5, 2, 4, 1);
+ }
+ write_mchbar32(0x120,
+ (1 << (info->max_slots_used_in_channel + 28)) |
+ 0x188e7f9f);
+
+ write_mchbar8(0x124,
+ info->board_lane_delay[4] +
+ ((frequency_01(info) + 999) / 1000));
+ write_mchbar16(0x125, 0x1360);
+ write_mchbar8(0x127, 0x40);
+ if (info->fsb_frequency < frequency_11(info) / 2) {
+ unsigned some_delay_2_half_cycles;
+ high_multiplier = 1;
+ some_delay_2_half_cycles = ps_to_halfcycles(info,
+ ((3 *
+ fsbcycle_ps(info))
+ >> 1) +
+ (halfcycle_ps(info)
+ *
+ reg178_min[info->
+ clock_speed_index]
+ >> 6)
+ +
+ 4 *
+ halfcycle_ps(info)
+ + 2230);
+ some_delay_3_half_cycles =
+ min((some_delay_2_half_cycles +
+ (frequency_11(info) * 2) * (28 -
+ some_delay_2_half_cycles) /
+ (frequency_11(info) * 2 -
+ 4 * (info->fsb_frequency))) >> 3, 7);
+ }
+ if (read_mchbar8(0x2ca9) & 1)
+ some_delay_3_half_cycles = 3;
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar32(0x220 + (channel << 10),
+ read_mchbar32(0x220 +
+ (channel << 10)) | 0x18001117);
+ write_mchbar32(0x224 + (channel << 10),
+ (info->max_slots_used_in_channel - 1)
+ |
+ ((info->cas_latency - 5 -
+ info->clock_speed_index) << 21)
+ |
+ ((info->max_slots_used_in_channel +
+ info->cas_latency - cas_latency_shift -
+ 4) << 16)
+ | ((info->cas_latency - cas_latency_shift - 4) <<
+ 26)
+ |
+ ((info->cas_latency - info->clock_speed_index +
+ info->max_slots_used_in_channel - 6) << 8));
+ write_mchbar32(0x228 + (channel << 10),
+ info->max_slots_used_in_channel);
+ write_mchbar8(0x239 + (channel << 10), 32);
+ write_mchbar32(0x248 + (channel << 10),
+ (high_multiplier << 24) |
+ (some_delay_3_half_cycles << 25) | 0x840000);
+ write_mchbar32(0x278 + (channel << 10), 0xc362042);
+ write_mchbar32(0x27c + (channel << 10), 0x8b000062);
+ write_mchbar32(0x24c + (channel << 10),
+ ((! !info->
+ clock_speed_index) << 17) | (((2 +
+ info->
+ clock_speed_index
+ -
+ (! !info->
+ clock_speed_index)))
+ << 12) | 0x10200);
+
+ write_mchbar8(0x267 + (channel << 10), 0x4);
+ write_mchbar16(0x272 + (channel << 10), 0x155);
+ write_mchbar32(0x2bc + (channel << 10),
+ (read_mchbar32(0x2bc + (channel << 10)) &
+ 0xFF000000)
+ | 0x707070);
+
+ write_500(info, channel,
+ ((!info->populated_ranks[channel][1][1])
+ | (!info->populated_ranks[channel][1][0] << 1)
+ | (!info->populated_ranks[channel][0][1] << 2)
+ | (!info->populated_ranks[channel][0][0] << 3)),
+ 0x4c9, 4, 1);
+ }
+
+ write_mchbar8(0x2c4, ((1 + (info->clock_speed_index != 0)) << 6) | 0xC);
+ {
+ u8 freq_divisor = 2;
+ if (info->fsb_frequency == frequency_11(info))
+ freq_divisor = 3;
+ else if (2 * info->fsb_frequency < 3 * (frequency_11(info) / 2))
+ freq_divisor = 1;
+ else
+ freq_divisor = 2;
+ write_mchbar32(0x2c0, (freq_divisor << 11) | 0x6009c400);
+ }
+
+ if (info->board_lane_delay[3] <= 10) {
+ if (info->board_lane_delay[3] <= 8)
+ lane_3_delay = info->board_lane_delay[3];
+ else
+ lane_3_delay = 10;
+ } else {
+ lane_3_delay = 12;
+ }
+ cas_latency_derived = info->cas_latency - info->clock_speed_index + 2;
+ if (info->clock_speed_index > 1)
+ cas_latency_derived++;
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar32(0x240 + (channel << 10),
+ ((info->clock_speed_index ==
+ 0) * 0x11000) | 0x1002100 | ((2 +
+ info->
+ clock_speed_index)
+ << 4) | (info->
+ cas_latency
+ - 3));
+ write_500(info, channel, (info->clock_speed_index << 1) | 1,
+ 0x609, 6, 1);
+ write_500(info, channel,
+ info->clock_speed_index + 2 * info->cas_latency - 7,
+ 0x601, 6, 1);
+
+ write_mchbar32(0x250 + (channel << 10),
+ ((lane_3_delay + info->clock_speed_index +
+ 9) << 6)
+ | (info->board_lane_delay[7] << 2) | (info->
+ board_lane_delay
+ [4] << 16)
+ | (info->board_lane_delay[1] << 25) | (info->
+ board_lane_delay
+ [1] << 29)
+ | 1);
+ write_mchbar32(0x254 + (channel << 10),
+ (info->
+ board_lane_delay[1] >> 3) | ((info->
+ board_lane_delay
+ [8] +
+ 4 *
+ info->
+ use_ecc) << 6) |
+ 0x80 | (info->board_lane_delay[6] << 1) | (info->
+ board_lane_delay
+ [2] <<
+ 28) |
+ (cas_latency_derived << 16) | 0x4700000);
+ write_mchbar32(0x258 + (channel << 10),
+ ((info->board_lane_delay[5] +
+ info->clock_speed_index +
+ 9) << 12) | ((info->clock_speed_index -
+ info->cas_latency + 12) << 8)
+ | (info->board_lane_delay[2] << 17) | (info->
+ board_lane_delay
+ [4] << 24)
+ | 0x47);
+ write_mchbar32(0x25c + (channel << 10),
+ (info->board_lane_delay[1] << 1) | (info->
+ board_lane_delay
+ [0] << 8) |
+ 0x1da50000);
+ write_mchbar8(0x264 + (channel << 10), 0xff);
+ write_mchbar8(0x5f8 + (channel << 10),
+ (cas_latency_shift << 3) | info->use_ecc);
+ }
+
+ program_modules_memory_map(info, 1);
+
+ write_mchbar16(0x610,
+ (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9)
+ | (read_mchbar16(0x610) & 0x1C3) | 0x3C);
+ write_mchbar16(0x612, read_mchbar16(0x612) | 0x100);
+ write_mchbar16(0x214, read_mchbar16(0x214) | 0x3E00);
+ for (i = 0; i < 8; i++) {
+ pci_mm_write32(QUICKPATH_BUS, 0, 1, 0x80 + 4 * i,
+ (info->total_memory_mb - 64) | !i | 2);
+ pci_mm_write32(QUICKPATH_BUS, 0, 1, 0xc0 + 4 * i, 0);
+ }
+}
+
+#define BETTER_MEMORY_MAP 0
+
+static void program_total_memory_map(struct raminfo *info)
+{
+ unsigned int TOM, TOLUD, TOUUD;
+ unsigned int quickpath_reserved;
+ unsigned int REMAPbase;
+ unsigned int uma_base_igd;
+ unsigned int uma_base_gtt;
+ int memory_remap;
+ unsigned int memory_map[8];
+ int i;
+ unsigned int current_limit;
+ unsigned int tseg_base;
+ int uma_size_igd = 0, uma_size_gtt = 0;
+
+ memset(memory_map, 0, sizeof(memory_map));
+
+#if REAL
+ if (info->uma_enabled) {
+ u16 t = pci_mm_read16(NORTHBRIDGE, D0F0_GGC);
+ gav(t);
+ const int uma_sizes_gtt[16] =
+ { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
+ /* Igd memory */
+ const int uma_sizes_igd[16] = {
+ 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352,
+ 256, 512
+ };
+
+ uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];
+ uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
+ }
+#endif
+
+ TOM = info->total_memory_mb;
+ if (TOM == 4096)
+ TOM = 4032;
+ TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64);
+ TOLUD = ALIGN_DOWN(min(3072 + ALIGN_UP(uma_size_igd + uma_size_gtt, 64)
+ , TOUUD), 64);
+ memory_remap = 0;
+ if (TOUUD - TOLUD > 64) {
+ memory_remap = 1;
+ REMAPbase = max(4096, TOUUD);
+ TOUUD = TOUUD - TOLUD + 4096;
+ }
+ if (TOUUD > 4096)
+ memory_map[2] = TOUUD | 1;
+ quickpath_reserved = 0;
+
+ {
+ u32 t;
+
+ gav(t = pci_mm_read32(QUICKPATH_BUS, 0, 1, 0x68));
+ if (t & 0x800)
+ quickpath_reserved =
+ (1 << find_lowest_bit_set32(t >> 20));
+ }
+ if (memory_remap)
+ TOUUD -= quickpath_reserved;
+
+#if !REAL
+ if (info->uma_enabled) {
+ u16 t = pci_mm_read16(NORTHBRIDGE, D0F0_GGC);
+ gav(t);
+ const int uma_sizes_gtt[16] =
+ { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
+ /* Igd memory */
+ const int uma_sizes_igd[16] = {
+ 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352,
+ 256, 512
+ };
+
+ uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];
+ uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
+ }
+#endif
+
+ uma_base_igd = TOLUD - uma_size_igd;
+ uma_base_gtt = uma_base_igd - uma_size_gtt;
+ tseg_base = ALIGN_DOWN(uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20);
+ if (!memory_remap)
+ tseg_base -= quickpath_reserved;
+ tseg_base = ALIGN_DOWN(tseg_base, 8);
+
+ pci_mm_write16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4);
+ pci_mm_write16(NORTHBRIDGE, D0F0_TOM, TOM >> 6);
+ if (memory_remap) {
+ pci_mm_write16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6);
+ pci_mm_write16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6);
+ }
+ pci_mm_write16(NORTHBRIDGE, D0F0_TOUUD, TOUUD);
+
+ if (info->uma_enabled) {
+ pci_mm_write32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20);
+ pci_mm_write32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20);
+ }
+ pci_mm_write32(NORTHBRIDGE, TSEG, tseg_base << 20);
+
+ current_limit = 0;
+ memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1;
+ memory_map[1] = 4096;
+ for (i = 0; i < ARRAY_SIZE(memory_map); i++) {
+ current_limit = max(current_limit, memory_map[i] & ~1);
+ pci_mm_write32(QUICKPATH_BUS, 0, 1, 4 * i + 0x80,
+ (memory_map[i] & 1) | ALIGN_DOWN(current_limit -
+ 1, 64) | 2);
+ pci_mm_write32(QUICKPATH_BUS, 0, 1, 4 * i + 0xc0, 0);
+ }
+}
+
+static void collect_system_info(struct raminfo *info)
+{
+ u32 capid0[3];
+ int i;
+ unsigned channel;
+
+ /* Wait for some bit, maybe TXT clear. */
+ while (!(read8(0xfed40000) & (1 << 7))) ;
+
+ if (!info->heci_bar)
+ gav(info->heci_bar =
+ pci_mm_read32(HECIDEV, HECIBAR) & 0xFFFFFFF8);
+ if (!info->memory_reserved_for_heci_mb) {
+ /* Wait for ME to be ready */
+ intel_early_me_init();
+ info->memory_reserved_for_heci_mb = intel_early_me_uma_size();
+ }
+
+ for (i = 0; i < 3; i++)
+ gav(capid0[i] =
+ pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2)));
+ gav(info->revision = pci_mm_read8(NORTHBRIDGE, PCI_REVISION_ID));
+ info->max_supported_clock_speed_index = (~capid0[1] & 7);
+
+ if ((capid0[1] >> 11) & 1)
+ info->uma_enabled = 0;
+ else
+ gav(info->uma_enabled =
+ pci_mm_read8(NORTHBRIDGE, D0F0_DEVEN) & 8);
+ /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */
+ info->silicon_revision = 0;
+
+ if (capid0[2] & 2) {
+ info->silicon_revision = 0;
+ info->max_supported_clock_speed_index = 2;
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ if (info->populated_ranks[channel][0][0]
+ && (info->spd[channel][0][MODULE_TYPE] & 0xf) ==
+ 3) {
+ info->silicon_revision = 2;
+ info->max_supported_clock_speed_index = 1;
+ }
+ } else {
+ switch (((capid0[2] >> 18) & 1) + 2 * ((capid0[1] >> 3) & 1)) {
+ case 1:
+ case 2:
+ info->silicon_revision = 3;
+ break;
+ case 3:
+ info->silicon_revision = 0;
+ break;
+ case 0:
+ info->silicon_revision = 2;
+ break;
+ }
+ switch (pci_mm_read16(NORTHBRIDGE, PCI_DEVICE_ID)) {
+ case 0x40:
+ info->silicon_revision = 0;
+ break;
+ case 0x48:
+ info->silicon_revision = 1;
+ break;
+ }
+ }
+}
+
+static void write_training_data(struct raminfo *info)
+{
+ int tm, channel, slot, rank, lane;
+ if (info->revision < 8)
+ return;
+
+ for (tm = 0; tm < 4; tm++)
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ for (lane = 0; lane < 9; lane++)
+ write_500(info, channel,
+ info->
+ cached_training->
+ lane_timings[tm]
+ [channel][slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, tm, slot,
+ rank), 9, 0);
+ write_1d0(info->cached_training->reg_178, 0x178, 7, 1);
+ write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1);
+}
+
+static void dump_timings(struct raminfo *info)
+{
+#if REAL
+ int channel, slot, rank, lane, i;
+ printk(BIOS_DEBUG, "Timings:\n");
+ FOR_POPULATED_RANKS {
+ printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel,
+ slot, rank);
+ for (lane = 0; lane < 9; lane++) {
+ printk(BIOS_DEBUG, "lane %d: ", lane);
+ for (i = 0; i < 4; i++) {
+ printk(BIOS_DEBUG, "%x (%x) ",
+ read_500(info, channel,
+ get_timing_register_addr
+ (lane, i, slot, rank),
+ 9),
+ info->training.
+ lane_timings[i][channel][slot][rank]
+ [lane]);
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+ }
+ printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7),
+ info->training.reg_178);
+ printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),
+ info->training.reg_10b);
+#endif
+}
+
+static void save_timings(struct raminfo *info)
+{
+#if CONFIG_EARLY_CBMEM_INIT
+ struct ram_training train;
+ struct mrc_data_container *mrcdata;
+ int output_len = ALIGN(sizeof(train), 16);
+ int channel, slot, rank, lane, i;
+
+ train = info->training;
+ FOR_POPULATED_RANKS for (lane = 0; lane < 9; lane++)
+ for (i = 0; i < 4; i++)
+ train.lane_timings[i][channel][slot][rank][lane] =
+ read_500(info, channel,
+ get_timing_register_addr(lane, i, slot,
+ rank), 9);
+ train.reg_178 = read_1d0(0x178, 7);
+ train.reg_10b = read_1d0(0x10b, 6);
+
+ /* Save the MRC S3 restore data to cbmem */
+ cbmem_initialize();
+ mrcdata = cbmem_add
+ (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container));
+
+ printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
+ &train, mrcdata, output_len);
+
+ mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
+ mrcdata->mrc_data_size = output_len;
+ mrcdata->reserved = 0;
+ memcpy(mrcdata->mrc_data, &train, sizeof(train));
+
+ /* Zero the unused space in aligned buffer. */
+ if (output_len > sizeof(train))
+ memset(mrcdata->mrc_data + sizeof(train), 0,
+ output_len - sizeof(train));
+
+ mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
+ mrcdata->mrc_data_size);
+#endif
+}
+
+#if REAL
+static const struct ram_training *get_cached_training(void)
+{
+ struct mrc_data_container *cont;
+ cont = find_current_mrc_cache();
+ if (!cont)
+ return 0;
+ return (void *)cont->mrc_data;
+}
+#endif
+
+/* FIXME: add timeout. */
+static void wait_heci_ready(void)
+{
+ while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ; // = 0x8000000c
+ write32((DEFAULT_HECIBAR | 0x4),
+ (read32(DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc);
+}
+
+/* FIXME: add timeout. */
+static void wait_heci_cb_avail(int len)
+{
+ union {
+ struct mei_csr csr;
+ u32 raw;
+ } csr;
+
+ while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ;
+
+ do
+ csr.raw = read32(DEFAULT_HECIBAR | 0x4);
+ while (len >
+ csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
+ csr.csr.buffer_read_ptr));
+}
+
+static void send_heci_packet(struct mei_header *head, u32 * payload)
+{
+ int len = (head->length + 3) / 4;
+ int i;
+
+ wait_heci_cb_avail(len + 1);
+
+ /* FIXME: handle leftovers correctly. */
+ write32(DEFAULT_HECIBAR | 0, *(u32 *) head);
+ for (i = 0; i < len - 1; i++)
+ write32(DEFAULT_HECIBAR | 0, payload[i]);
+
+ write32(DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1));
+ write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 0x4);
+}
+
+static void
+send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)
+{
+ struct mei_header head;
+ int maxlen;
+
+ wait_heci_ready();
+ maxlen = (read32(DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4;
+
+ while (len) {
+ int cur = len;
+ if (cur > maxlen) {
+ cur = maxlen;
+ head.is_complete = 0;
+ } else
+ head.is_complete = 1;
+ head.length = cur;
+ head.reserved = 0;
+ head.client_address = clientaddress;
+ head.host_address = hostaddress;
+ send_heci_packet(&head, (u32 *) msg);
+ len -= cur;
+ msg += cur;
+ }
+}
+
+/* FIXME: Add timeout. */
+static int
+recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
+ u32 * packet_size)
+{
+ union {
+ struct mei_csr csr;
+ u32 raw;
+ } csr;
+ int i = 0;
+
+ write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 2);
+ do {
+ csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+#if !REAL
+ if (i++ > 346)
+ return -1;
+#endif
+ }
+ while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
+ *(u32 *) head = read32(DEFAULT_HECIBAR | 0x8);
+ if (!head->length) {
+ write32(DEFAULT_HECIBAR | 0x4,
+ read32(DEFAULT_HECIBAR | 0x4) | 2);
+ *packet_size = 0;
+ return 0;
+ }
+ if (head->length + 4 > 4 * csr.csr.buffer_depth
+ || head->length > *packet_size) {
+ *packet_size = 0;
+ return -1;
+ }
+
+ do
+ csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ while ((head->length + 3) >> 2 >
+ csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
+
+ for (i = 0; i < (head->length + 3) >> 2; i++)
+ packet[i++] = read32(DEFAULT_HECIBAR | 0x8);
+ *packet_size = head->length;
+ if (!csr.csr.ready)
+ *packet_size = 0;
+ write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 4);
+ return 0;
+}
+
+/* FIXME: Add timeout. */
+static int
+recv_heci_message(struct raminfo *info, u32 * message, u32 * message_size)
+{
+ struct mei_header head;
+ int current_position;
+
+ current_position = 0;
+ while (1) {
+ u32 current_size;
+ current_size = *message_size - current_position;
+ if (recv_heci_packet
+ (info, &head, message + (current_position >> 2),
+ ¤t_size) == -1)
+ break;
+ if (!current_size)
+ break;
+ current_position += current_size;
+ if (head.is_complete) {
+ *message_size = current_position;
+ return 0;
+ }
+
+ if (current_position >= *message_size)
+ break;
+ }
+ *message_size = 0;
+ return -1;
+}
+
+static void send_heci_uma_message(struct raminfo *info)
+{
+ struct uma_reply {
+ u8 group_id;
+ u8 command;
+ u8 reserved;
+ u8 result;
+ u8 field2;
+ u8 unk3[0x48 - 4 - 1];
+ } __attribute__ ((packed)) reply;
+ struct uma_message {
+ u8 group_id;
+ u8 cmd;
+ u8 reserved;
+ u8 result;
+ u32 c2;
+ u64 heci_uma_addr;
+ u32 memory_reserved_for_heci_mb;
+ u16 c3;
+ } __attribute__ ((packed)) msg = {
+ 0, MKHI_SET_UMA, 0, 0,
+ 0x82,
+ info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0};
+ u32 reply_size;
+
+ send_heci_message((u8 *) & msg, sizeof(msg), 0, 7);
+
+ reply_size = sizeof(reply);
+ if (recv_heci_message(info, (u32 *) & reply, &reply_size) == -1)
+ return;
+
+ if (reply.command != (MKHI_SET_UMA | (1 << 7)))
+ die("HECI init failed\n");
+}
+
+static void setup_heci_uma(struct raminfo *info)
+{
+ u32 reg44;
+
+ reg44 = pci_mm_read32(HECIDEV, 0x44); // = 0x80010020
+ info->memory_reserved_for_heci_mb = 0;
+ info->heci_uma_addr = 0;
+ if (!((reg44 & 0x10000) && !(pci_mm_read32(HECIDEV, 0x40) & 0x20)))
+ return;
+
+ info->heci_bar = pci_mm_read32(HECIDEV, 0x10) & 0xFFFFFFF0;
+ info->memory_reserved_for_heci_mb = reg44 & 0x3f;
+ info->heci_uma_addr =
+ ((u64)
+ ((((u64) pci_mm_read16(NORTHBRIDGE, D0F0_TOM)) << 6) -
+ info->memory_reserved_for_heci_mb)) << 20;
+
+ pci_mm_read32(NORTHBRIDGE, DMIBAR);
+ if (info->memory_reserved_for_heci_mb) {
+ write32(DEFAULT_DMIBAR | 0x14,
+ read32(DEFAULT_DMIBAR | 0x14) & ~0x80);
+ write32(DEFAULT_RCBA | 0x14,
+ read32(DEFAULT_RCBA | 0x14) & ~0x80);
+ write32(DEFAULT_DMIBAR | 0x20,
+ read32(DEFAULT_DMIBAR | 0x20) & ~0x80);
+ write32(DEFAULT_RCBA | 0x20,
+ read32(DEFAULT_RCBA | 0x20) & ~0x80);
+ write32(DEFAULT_DMIBAR | 0x2c,
+ read32(DEFAULT_DMIBAR | 0x2c) & ~0x80);
+ write32(DEFAULT_RCBA | 0x30,
+ read32(DEFAULT_RCBA | 0x30) & ~0x80);
+ write32(DEFAULT_DMIBAR | 0x38,
+ read32(DEFAULT_DMIBAR | 0x38) & ~0x80);
+ write32(DEFAULT_RCBA | 0x40,
+ read32(DEFAULT_RCBA | 0x40) & ~0x80);
+
+ write32(DEFAULT_RCBA | 0x40, 0x87000080); // OK
+ write32(DEFAULT_DMIBAR | 0x38, 0x87000080); // OK
+ while (read16(DEFAULT_RCBA | 0x46) & 2
+ && read16(DEFAULT_DMIBAR | 0x3e) & 2) ;
+ }
+
+ write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
+
+ send_heci_uma_message(info);
+
+ pci_mm_write32(HECIDEV, 0x10, 0x0);
+ pci_mm_write8(HECIDEV, 0x4, 0x0);
+
+}
+
+static int have_match_ranks(struct raminfo *info, int channel, int ranks)
+{
+ int ranks_in_channel;
+ ranks_in_channel = info->populated_ranks[channel][0][0]
+ + info->populated_ranks[channel][0][1]
+ + info->populated_ranks[channel][1][0]
+ + info->populated_ranks[channel][1][1];
+
+ /* empty channel */
+ if (ranks_in_channel == 0)
+ return 1;
+
+ if (ranks_in_channel != ranks)
+ return 0;
+ /* single slot */
+ if (info->populated_ranks[channel][0][0] !=
+ info->populated_ranks[channel][1][0])
+ return 1;
+ if (info->populated_ranks[channel][0][1] !=
+ info->populated_ranks[channel][1][1])
+ return 1;
+ if (info->is_x16_module[channel][0] != info->is_x16_module[channel][1])
+ return 0;
+ if (info->density[channel][0] != info->density[channel][1])
+ return 0;
+ return 1;
+}
+
+#define WTF1 1
+
+static void read_4090(struct raminfo *info)
+{
+ int i, channel, slot, rank, lane;
+ for (i = 0; i < 2; i++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ for (lane = 0; lane < 9; lane++)
+ info->training.
+ lane_timings[0][i][slot][rank][lane]
+ = 32;
+
+ for (i = 1; i < 4; i++)
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ for (lane = 0; lane < 9; lane++) {
+ info->training.
+ lane_timings[i][channel]
+ [slot][rank][lane] =
+ read_500(info, channel,
+ get_timing_register_addr
+ (lane, i, slot,
+ rank), 9)
+ + (i == 1) * 11; // !!!!
+ }
+
+}
+
+static u32 get_etalon2(int flip, u32 addr)
+{
+ const u16 invmask[] = {
+ 0xaaaa, 0x6db6, 0x4924, 0xeeee, 0xcccc, 0x8888, 0x7bde, 0x739c,
+ 0x6318, 0x4210, 0xefbe, 0xcf3c, 0x8e38, 0x0c30, 0x0820
+ };
+ u32 ret;
+ u32 comp4 = addr / 480;
+ addr %= 480;
+ u32 comp1 = addr & 0xf;
+ u32 comp2 = (addr >> 4) & 1;
+ u32 comp3 = addr >> 5;
+
+ if (comp4)
+ ret = 0x1010101 << (comp4 - 1);
+ else
+ ret = 0;
+ if (flip ^ (((invmask[comp3] >> comp1) ^ comp2) & 1))
+ ret = ~ret;
+
+ return ret;
+}
+
+static void disable_cache(void)
+{
+ my_write_msr(MTRRphysBase_MSR(3), 0);
+ my_write_msr(MTRRphysMask_MSR(3), 0);
+}
+
+static void enable_cache(unsigned int base, unsigned int size)
+{
+ my_write_msr(MTRRphysBase_MSR(3), base | MTRR_TYPE_WRPROT);
+ my_write_msr(MTRRphysMask_MSR(3), 0x0000000f00000000LL
+ | ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRRdefTypeEn)
+ & 0xffffffff));
+}
+
+static void flush_cache(u32 start, u32 size)
+{
+ u32 end;
+ u32 addr;
+
+ end = start + (ALIGN_DOWN(size + 4096, 4096));
+ for (addr = start; addr < end; addr += 64)
+ clflush(addr);
+}
+
+static void clear_errors(void)
+{
+ pci_mm_write8(NORTHBRIDGE, 0xc0, 0x01);
+}
+
+static void write_testing(struct raminfo *info, int totalrank, int flip)
+{
+ int nwrites = 0;
+ /* in 8-byte units. */
+ u32 offset;
+ u32 base;
+
+ base = totalrank << 28;
+ for (offset = 0; offset < 9 * 480; offset += 2) {
+ write32(base + offset * 8, get_etalon2(flip, offset));
+ write32(base + offset * 8 + 4, get_etalon2(flip, offset));
+ write32(base + offset * 8 + 8, get_etalon2(flip, offset + 1));
+ write32(base + offset * 8 + 12, get_etalon2(flip, offset + 1));
+ nwrites += 4;
+ if (nwrites >= 320) {
+ clear_errors();
+ nwrites = 0;
+ }
+ }
+}
+
+static u8 check_testing(struct raminfo *info, u8 total_rank, int flip)
+{
+ u8 failmask = 0;
+ int i;
+ int comp1, comp2, comp3;
+ u32 failxor[2] = { 0, 0 };
+
+ enable_cache((total_rank << 28), 1728 * 5 * 4);
+
+ for (comp3 = 0; comp3 < 9 && failmask != 0xff; comp3++) {
+ for (comp1 = 0; comp1 < 4; comp1++)
+ for (comp2 = 0; comp2 < 60; comp2++) {
+ u32 re[4];
+ u32 curroffset =
+ comp3 * 8 * 60 + 2 * comp1 + 8 * comp2;
+ read128((total_rank << 28) | (curroffset << 3),
+ (u64 *) re);
+ failxor[0] |=
+ get_etalon2(flip, curroffset) ^ re[0];
+ failxor[1] |=
+ get_etalon2(flip, curroffset) ^ re[1];
+ failxor[0] |=
+ get_etalon2(flip, curroffset | 1) ^ re[2];
+ failxor[1] |=
+ get_etalon2(flip, curroffset | 1) ^ re[3];
+ }
+ for (i = 0; i < 8; i++)
+ if ((0xff << (8 * (i % 4))) & failxor[i / 4])
+ failmask |= 1 << i;
+ }
+ disable_cache();
+ flush_cache((total_rank << 28), 1728 * 5 * 4);
+ return failmask;
+}
+
+const u32 seed1[0x18] = {
+ 0x3a9d5ab5, 0x576cb65b, 0x555773b6, 0x2ab772ee,
+ 0x555556ee, 0x3a9d5ab5, 0x576cb65b, 0x555773b6,
+ 0x2ab772ee, 0x555556ee, 0x5155a555, 0x5155a555,
+ 0x5155a555, 0x5155a555, 0x3a9d5ab5, 0x576cb65b,
+ 0x555773b6, 0x2ab772ee, 0x555556ee, 0x55d6b4a5,
+ 0x366d6b3a, 0x2ae5ddbb, 0x3b9ddbb7, 0x55d6b4a5,
+};
+
+static u32 get_seed2(int a, int b)
+{
+ const u32 seed2[5] = {
+ 0x55555555, 0x33333333, 0x2e555a55, 0x55555555,
+ 0x5b6db6db,
+ };
+ u32 r;
+ r = seed2[(a + (a >= 10)) / 5];
+ return b ? ~r : r;
+}
+
+static int make_shift(int comp2, int comp5, int x)
+{
+ const u8 seed3[32] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x38, 0x1c, 0x3c, 0x18, 0x38, 0x38,
+ 0x38, 0x38, 0x38, 0x38, 0x0f, 0x0f, 0x0f, 0x0f,
+ 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
+ };
+
+ return (comp2 - ((seed3[comp5] >> (x & 7)) & 1)) & 0x1f;
+}
+
+static u32 get_etalon(int flip, u32 addr)
+{
+ u32 mask_byte = 0;
+ int comp1 = (addr >> 1) & 1;
+ int comp2 = (addr >> 3) & 0x1f;
+ int comp3 = (addr >> 8) & 0xf;
+ int comp4 = (addr >> 12) & 0xf;
+ int comp5 = (addr >> 16) & 0x1f;
+ u32 mask_bit = ~(0x10001 << comp3);
+ u32 part1;
+ u32 part2;
+ int byte;
+
+ part2 =
+ ((seed1[comp5] >>
+ make_shift(comp2, comp5,
+ (comp3 >> 3) | (comp1 << 2) | 2)) & 1) ^ flip;
+ part1 =
+ ((seed1[comp5] >>
+ make_shift(comp2, comp5,
+ (comp3 >> 3) | (comp1 << 2) | 0)) & 1) ^ flip;
+
+ for (byte = 0; byte < 4; byte++)
+ if ((get_seed2(comp5, comp4) >>
+ make_shift(comp2, comp5, (byte | (comp1 << 2)))) & 1)
+ mask_byte |= 0xff << (8 * byte);
+
+ return (mask_bit & mask_byte) | (part1 << comp3) | (part2 <<
+ (comp3 + 16));
+}
+
+static void
+write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
+ char flip)
+{
+ int i;
+ for (i = 0; i < 2048; i++)
+ write32((totalrank << 28) | (region << 25) | (block << 16) |
+ (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
+}
+
+static u8
+check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
+ char flip)
+{
+ u8 failmask = 0;
+ u32 failxor[2];
+ int i;
+ int comp1, comp2, comp3;
+
+ failxor[0] = 0;
+ failxor[1] = 0;
+
+ enable_cache(totalrank << 28, 134217728);
+ for (comp3 = 0; comp3 < 2 && failmask != 0xff; comp3++) {
+ for (comp1 = 0; comp1 < 16; comp1++)
+ for (comp2 = 0; comp2 < 64; comp2++) {
+ u32 addr =
+ (totalrank << 28) | (region << 25) | (block
+ << 16)
+ | (comp3 << 12) | (comp2 << 6) | (comp1 <<
+ 2);
+ failxor[comp1 & 1] |=
+ read32(addr) ^ get_etalon(flip, addr);
+ }
+ for (i = 0; i < 8; i++)
+ if ((0xff << (8 * (i % 4))) & failxor[i / 4])
+ failmask |= 1 << i;
+ }
+ disable_cache();
+ flush_cache((totalrank << 28) | (region << 25) | (block << 16), 16384);
+ return failmask;
+}
+
+static int check_bounded(unsigned short *vals, u16 bound)
+{
+ int i;
+
+ for (i = 0; i < 8; i++)
+ if (vals[i] < bound)
+ return 0;
+ return 1;
+}
+
+enum state {
+ BEFORE_USABLE = 0, AT_USABLE = 1, AT_MARGIN = 2, COMPLETE = 3
+};
+
+static int validate_state(enum state *in)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ if (in[i] != COMPLETE)
+ return 0;
+ return 1;
+}
+
+static void
+do_fsm(enum state *state, u16 * counter,
+ u8 fail_mask, int margin, int uplimit,
+ u8 * res_low, u8 * res_high, u8 val)
+{
+ int lane;
+
+ for (lane = 0; lane < 8; lane++) {
+ int is_fail = (fail_mask >> lane) & 1;
+ switch (state[lane]) {
+ case BEFORE_USABLE:
+ if (!is_fail) {
+ counter[lane] = 1;
+ state[lane] = AT_USABLE;
+ break;
+ }
+ counter[lane] = 0;
+ state[lane] = BEFORE_USABLE;
+ break;
+ case AT_USABLE:
+ if (!is_fail) {
+ ++counter[lane];
+ if (counter[lane] >= margin) {
+ state[lane] = AT_MARGIN;
+ res_low[lane] = val - margin + 1;
+ break;
+ }
+ state[lane] = 1;
+ break;
+ }
+ counter[lane] = 0;
+ state[lane] = BEFORE_USABLE;
+ break;
+ case AT_MARGIN:
+ if (is_fail) {
+ state[lane] = COMPLETE;
+ res_high[lane] = val - 1;
+ } else {
+ counter[lane]++;
+ state[lane] = AT_MARGIN;
+ if (val == uplimit) {
+ state[lane] = COMPLETE;
+ res_high[lane] = uplimit;
+ }
+ }
+ break;
+ case COMPLETE:
+ break;
+ }
+ }
+}
+
+static void
+train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank,
+ u8 total_rank, u8 reg_178, int first_run, int niter,
+ timing_bounds_t * timings)
+{
+ int lane;
+ enum state state[8];
+ u16 count[8];
+ u8 lower_usable[8];
+ u8 upper_usable[8];
+ unsigned short num_sucessfully_checked[8];
+ u8 secondary_total_rank;
+ u8 reg1b3;
+
+ if (info->populated_ranks_mask[1]) {
+ if (channel == 1)
+ secondary_total_rank =
+ info->populated_ranks[1][0][0] +
+ info->populated_ranks[1][0][1]
+ + info->populated_ranks[1][1][0] +
+ info->populated_ranks[1][1][1];
+ else
+ secondary_total_rank = 0;
+ } else
+ secondary_total_rank = total_rank;
+
+ {
+ int i;
+ for (i = 0; i < 8; i++)
+ state[i] = BEFORE_USABLE;
+ }
+
+ if (!first_run) {
+ int is_all_ok = 1;
+ for (lane = 0; lane < 8; lane++)
+ if (timings[reg_178][channel][slot][rank][lane].
+ smallest ==
+ timings[reg_178][channel][slot][rank][lane].
+ largest) {
+ timings[reg_178][channel][slot][rank][lane].
+ smallest = 0;
+ timings[reg_178][channel][slot][rank][lane].
+ largest = 0;
+ is_all_ok = 0;
+ }
+ if (is_all_ok) {
+ int i;
+ for (i = 0; i < 8; i++)
+ state[i] = COMPLETE;
+ }
+ }
+
+ for (reg1b3 = 0; reg1b3 < 0x30 && !validate_state(state); reg1b3++) {
+ u8 failmask = 0;
+ write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1);
+ write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1);
+ failmask = check_testing(info, total_rank, 0);
+ write_mchbar32(0xfb0, read_mchbar32(0xfb0) | 0x00030000);
+ do_fsm(state, count, failmask, 5, 47, lower_usable,
+ upper_usable, reg1b3);
+ }
+
+ if (reg1b3) {
+ write_1d0(0, 0x1b3, 6, 1);
+ write_1d0(0, 0x1a3, 6, 1);
+ for (lane = 0; lane < 8; lane++) {
+ if (state[lane] == COMPLETE) {
+ timings[reg_178][channel][slot][rank][lane].
+ smallest =
+ lower_usable[lane] +
+ (info->training.
+ lane_timings[0][channel][slot][rank][lane]
+ & 0x3F) - 32;
+ timings[reg_178][channel][slot][rank][lane].
+ largest =
+ upper_usable[lane] +
+ (info->training.
+ lane_timings[0][channel][slot][rank][lane]
+ & 0x3F) - 32;
+ }
+ }
+ }
+
+ if (!first_run) {
+ for (lane = 0; lane < 8; lane++)
+ if (state[lane] == COMPLETE) {
+ write_500(info, channel,
+ timings[reg_178][channel][slot][rank]
+ [lane].smallest,
+ get_timing_register_addr(lane, 0,
+ slot, rank),
+ 9, 1);
+ write_500(info, channel,
+ timings[reg_178][channel][slot][rank]
+ [lane].smallest +
+ info->training.
+ lane_timings[1][channel][slot][rank]
+ [lane]
+ -
+ info->training.
+ lane_timings[0][channel][slot][rank]
+ [lane], get_timing_register_addr(lane,
+ 1,
+ slot,
+ rank),
+ 9, 1);
+ num_sucessfully_checked[lane] = 0;
+ } else
+ num_sucessfully_checked[lane] = -1;
+
+ do {
+ u8 failmask = 0;
+ int i;
+ for (i = 0; i < niter; i++) {
+ if (failmask == 0xFF)
+ break;
+ failmask |=
+ check_testing_type2(info, total_rank, 2, i,
+ 0);
+ failmask |=
+ check_testing_type2(info, total_rank, 3, i,
+ 1);
+ }
+ write_mchbar32(0xfb0,
+ read_mchbar32(0xfb0) | 0x00030000);
+ for (lane = 0; lane < 8; lane++)
+ if (num_sucessfully_checked[lane] != 0xffff) {
+ if ((1 << lane) & failmask) {
+ if (timings[reg_178][channel]
+ [slot][rank][lane].
+ largest <=
+ timings[reg_178][channel]
+ [slot][rank][lane].smallest)
+ num_sucessfully_checked
+ [lane] = -1;
+ else {
+ num_sucessfully_checked
+ [lane] = 0;
+ timings[reg_178]
+ [channel][slot]
+ [rank][lane].
+ smallest++;
+ write_500(info, channel,
+ timings
+ [reg_178]
+ [channel]
+ [slot][rank]
+ [lane].
+ smallest,
+ get_timing_register_addr
+ (lane, 0,
+ slot, rank),
+ 9, 1);
+ write_500(info, channel,
+ timings
+ [reg_178]
+ [channel]
+ [slot][rank]
+ [lane].
+ smallest +
+ info->
+ training.
+ lane_timings
+ [1][channel]
+ [slot][rank]
+ [lane]
+ -
+ info->
+ training.
+ lane_timings
+ [0][channel]
+ [slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, 1,
+ slot, rank),
+ 9, 1);
+ }
+ } else
+ num_sucessfully_checked[lane]++;
+ }
+ }
+ while (!check_bounded(num_sucessfully_checked, 2));
+
+ for (lane = 0; lane < 8; lane++)
+ if (state[lane] == COMPLETE) {
+ write_500(info, channel,
+ timings[reg_178][channel][slot][rank]
+ [lane].largest,
+ get_timing_register_addr(lane, 0,
+ slot, rank),
+ 9, 1);
+ write_500(info, channel,
+ timings[reg_178][channel][slot][rank]
+ [lane].largest +
+ info->training.
+ lane_timings[1][channel][slot][rank]
+ [lane]
+ -
+ info->training.
+ lane_timings[0][channel][slot][rank]
+ [lane], get_timing_register_addr(lane,
+ 1,
+ slot,
+ rank),
+ 9, 1);
+ num_sucessfully_checked[lane] = 0;
+ } else
+ num_sucessfully_checked[lane] = -1;
+
+ do {
+ int failmask = 0;
+ int i;
+ for (i = 0; i < niter; i++) {
+ if (failmask == 0xFF)
+ break;
+ failmask |=
+ check_testing_type2(info, total_rank, 2, i,
+ 0);
+ failmask |=
+ check_testing_type2(info, total_rank, 3, i,
+ 1);
+ }
+
+ write_mchbar32(0xfb0,
+ read_mchbar32(0xfb0) | 0x00030000);
+ for (lane = 0; lane < 8; lane++) {
+ if (num_sucessfully_checked[lane] != 0xffff) {
+ if ((1 << lane) & failmask) {
+ if (timings[reg_178][channel]
+ [slot][rank][lane].
+ largest <=
+ timings[reg_178][channel]
+ [slot][rank][lane].
+ smallest) {
+ num_sucessfully_checked
+ [lane] = -1;
+ } else {
+ num_sucessfully_checked
+ [lane] = 0;
+ timings[reg_178]
+ [channel][slot]
+ [rank][lane].
+ largest--;
+ write_500(info, channel,
+ timings
+ [reg_178]
+ [channel]
+ [slot][rank]
+ [lane].
+ largest,
+ get_timing_register_addr
+ (lane, 0,
+ slot, rank),
+ 9, 1);
+ write_500(info, channel,
+ timings
+ [reg_178]
+ [channel]
+ [slot][rank]
+ [lane].
+ largest +
+ info->
+ training.
+ lane_timings
+ [1][channel]
+ [slot][rank]
+ [lane]
+ -
+ info->
+ training.
+ lane_timings
+ [0][channel]
+ [slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, 1,
+ slot, rank),
+ 9, 1);
+ }
+ } else
+ num_sucessfully_checked[lane]++;
+ }
+ }
+ }
+ while (!check_bounded(num_sucessfully_checked, 3));
+
+ for (lane = 0; lane < 8; lane++) {
+ write_500(info, channel,
+ info->training.
+ lane_timings[0][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 0, slot, rank),
+ 9, 1);
+ write_500(info, channel,
+ info->training.
+ lane_timings[1][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 1, slot, rank),
+ 9, 1);
+ if (timings[reg_178][channel][slot][rank][lane].
+ largest <=
+ timings[reg_178][channel][slot][rank][lane].
+ smallest) {
+ timings[reg_178][channel][slot][rank][lane].
+ largest = 0;
+ timings[reg_178][channel][slot][rank][lane].
+ smallest = 0;
+ }
+ }
+ }
+}
+
+static void set_10b(struct raminfo *info, u8 val)
+{
+ int channel;
+ int slot, rank;
+ int lane;
+
+ if (read_1d0(0x10b, 6) == val)
+ return;
+
+ write_1d0(val, 0x10b, 6, 1);
+
+ FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 9; lane++) {
+ u16 reg_500;
+ reg_500 = read_500(info, channel,
+ get_timing_register_addr(lane, 0, slot,
+ rank), 9);
+ if (val == 1) {
+ if (lut16[info->clock_speed_index] <= reg_500)
+ reg_500 -= lut16[info->clock_speed_index];
+ else
+ reg_500 = 0;
+ } else {
+ reg_500 += lut16[info->clock_speed_index];
+ }
+ write_500(info, channel, reg_500,
+ get_timing_register_addr(lane, 0, slot, rank), 9, 1);
+ }
+}
+
+static void set_ecc(int onoff)
+{
+ int channel;
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ u8 t;
+ t = read_mchbar8((channel << 10) + 0x5f8);
+ if (onoff)
+ t |= 1;
+ else
+ t &= ~1;
+ write_mchbar8((channel << 10) + 0x5f8, t);
+ }
+}
+
+static void set_178(u8 val)
+{
+ if (val >= 31)
+ val = val - 31;
+ else
+ val = 63 - val;
+
+ write_1d0(2 * val, 0x178, 7, 1);
+}
+
+static void
+write_500_timings_type(struct raminfo *info, int channel, int slot, int rank,
+ int type)
+{
+ int lane;
+
+ for (lane = 0; lane < 8; lane++)
+ write_500(info, channel,
+ info->training.
+ lane_timings[type][channel][slot][rank][lane],
+ get_timing_register_addr(lane, type, slot, rank), 9,
+ 0);
+}
+
+static void
+try_timing_offsets(struct raminfo *info, int channel,
+ int slot, int rank, int totalrank)
+{
+ u16 count[8];
+ enum state state[8];
+ u8 lower_usable[8], upper_usable[8];
+ int lane;
+ int i;
+ int flip = 1;
+ int timing_offset;
+
+ for (i = 0; i < 8; i++)
+ state[i] = BEFORE_USABLE;
+
+ memset(count, 0, sizeof(count));
+
+ for (lane = 0; lane < 8; lane++)
+ write_500(info, channel,
+ info->training.
+ lane_timings[2][channel][slot][rank][lane] + 32,
+ get_timing_register_addr(lane, 3, slot, rank), 9, 1);
+
+ for (timing_offset = 0; !validate_state(state) && timing_offset < 64;
+ timing_offset++) {
+ u8 failmask;
+ write_1d0(timing_offset ^ 32, 0x1bb, 6, 1);
+ failmask = 0;
+ for (i = 0; i < 2 && failmask != 0xff; i++) {
+ flip = !flip;
+ write_testing(info, totalrank, flip);
+ failmask |= check_testing(info, totalrank, flip);
+ }
+ do_fsm(state, count, failmask, 10, 63, lower_usable,
+ upper_usable, timing_offset);
+ }
+ write_1d0(0, 0x1bb, 6, 1);
+ dump_timings(info);
+ if (!validate_state(state))
+ die("Couldn't discover DRAM timings (1)\n");
+
+ for (lane = 0; lane < 8; lane++) {
+ u8 bias = 0;
+
+ if (info->silicon_revision) {
+ int usable_length;
+
+ usable_length = upper_usable[lane] - lower_usable[lane];
+ if (usable_length >= 20) {
+ bias = usable_length / 2 - 10;
+ if (bias >= 2)
+ bias = 2;
+ }
+ }
+ write_500(info, channel,
+ info->training.
+ lane_timings[2][channel][slot][rank][lane] +
+ (upper_usable[lane] + lower_usable[lane]) / 2 - bias,
+ get_timing_register_addr(lane, 3, slot, rank), 9, 1);
+ info->training.timing2_bounds[channel][slot][rank][lane][0] =
+ info->training.lane_timings[2][channel][slot][rank][lane] +
+ lower_usable[lane];
+ info->training.timing2_bounds[channel][slot][rank][lane][1] =
+ info->training.lane_timings[2][channel][slot][rank][lane] +
+ upper_usable[lane];
+ info->training.timing2_offset[channel][slot][rank][lane] =
+ info->training.lane_timings[2][channel][slot][rank][lane];
+ }
+}
+
+static u8
+choose_training(struct raminfo *info, int channel, int slot, int rank,
+ int lane, timing_bounds_t * timings, u8 center_178)
+{
+ u16 central_weight;
+ u16 side_weight;
+ unsigned int sum = 0, count = 0;
+ u8 span;
+ u8 lower_margin, upper_margin;
+ u8 reg_178;
+ u8 result;
+
+ span = 12;
+ central_weight = 20;
+ side_weight = 20;
+ if (info->silicon_revision == 1 && channel == 1) {
+ central_weight = 5;
+ side_weight = 20;
+ if ((info->
+ populated_ranks_mask[1] ^ (info->
+ populated_ranks_mask[1] >> 2)) &
+ 1)
+ span = 18;
+ }
+ if ((info->populated_ranks_mask[0] & 5) == 5) {
+ central_weight = 20;
+ side_weight = 20;
+ }
+ if (info->clock_speed_index >= 2
+ && (info->populated_ranks_mask[0] & 5) == 5 && slot == 1) {
+ if (info->silicon_revision == 1) {
+ switch (channel) {
+ case 0:
+ if (lane == 1) {
+ central_weight = 10;
+ side_weight = 20;
+ }
+ break;
+ case 1:
+ if (lane == 6) {
+ side_weight = 5;
+ central_weight = 20;
+ }
+ break;
+ }
+ }
+ if (info->silicon_revision == 0 && channel == 0 && lane == 0) {
+ side_weight = 5;
+ central_weight = 20;
+ }
+ }
+ for (reg_178 = center_178 - span; reg_178 <= center_178 + span;
+ reg_178 += span) {
+ u8 smallest;
+ u8 largest;
+ largest = timings[reg_178][channel][slot][rank][lane].largest;
+ smallest = timings[reg_178][channel][slot][rank][lane].smallest;
+ if (largest - smallest + 1 >= 5) {
+ unsigned int weight;
+ if (reg_178 == center_178)
+ weight = central_weight;
+ else
+ weight = side_weight;
+ sum += weight * (largest + smallest);
+ count += weight;
+ }
+ }
+ dump_timings(info);
+ if (count == 0)
+ die("Couldn't discover DRAM timings (2)\n");
+ result = sum / (2 * count);
+ lower_margin =
+ result - timings[center_178][channel][slot][rank][lane].smallest;
+ upper_margin =
+ timings[center_178][channel][slot][rank][lane].largest - result;
+ if (upper_margin < 10 && lower_margin > 10)
+ result -= min(lower_margin - 10, 10 - upper_margin);
+ if (upper_margin > 10 && lower_margin < 10)
+ result += min(upper_margin - 10, 10 - lower_margin);
+ return result;
+}
+
+#define STANDARD_MIN_MARGIN 5
+
+static u8 choose_reg178(struct raminfo *info, timing_bounds_t * timings)
+{
+ u16 margin[64];
+ int lane, rank, slot, channel;
+ u8 reg178;
+ int count = 0, sum = 0;
+
+ for (reg178 = reg178_min[info->clock_speed_index];
+ reg178 < reg178_max[info->clock_speed_index];
+ reg178 += reg178_step[info->clock_speed_index]) {
+ margin[reg178] = -1;
+ FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) {
+ int curmargin =
+ timings[reg178][channel][slot][rank][lane].largest -
+ timings[reg178][channel][slot][rank][lane].
+ smallest + 1;
+ if (curmargin < margin[reg178])
+ margin[reg178] = curmargin;
+ }
+ if (margin[reg178] >= STANDARD_MIN_MARGIN) {
+ u16 weight;
+ weight = margin[reg178] - STANDARD_MIN_MARGIN;
+ sum += weight * reg178;
+ count += weight;
+ }
+ }
+ dump_timings(info);
+ if (count == 0)
+ die("Couldn't discover DRAM timings (3)\n");
+
+ u8 threshold;
+
+ for (threshold = 30; threshold >= 5; threshold--) {
+ int usable_length = 0;
+ int smallest_fount = 0;
+ for (reg178 = reg178_min[info->clock_speed_index];
+ reg178 < reg178_max[info->clock_speed_index];
+ reg178 += reg178_step[info->clock_speed_index])
+ if (margin[reg178] >= threshold) {
+ usable_length +=
+ reg178_step[info->clock_speed_index];
+ info->training.reg178_largest =
+ reg178 -
+ 2 * reg178_step[info->clock_speed_index];
+
+ if (!smallest_fount) {
+ smallest_fount = 1;
+ info->training.reg178_smallest =
+ reg178 +
+ reg178_step[info->
+ clock_speed_index];
+ }
+ }
+ if (usable_length >= 0x21)
+ break;
+ }
+
+ return sum / count;
+}
+
+static int check_cached_sanity(struct raminfo *info)
+{
+ int lane;
+ int slot, rank;
+ int channel;
+
+ if (!info->cached_training)
+ return 0;
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ for (lane = 0; lane < 8 + info->use_ecc; lane++) {
+ u16 cached_value, estimation_value;
+ cached_value =
+ info->cached_training->
+ lane_timings[1][channel][slot][rank]
+ [lane];
+ if (cached_value >= 0x18
+ && cached_value <= 0x1E7) {
+ estimation_value =
+ info->training.
+ lane_timings[1][channel]
+ [slot][rank][lane];
+ if (estimation_value <
+ cached_value - 24)
+ return 0;
+ if (estimation_value >
+ cached_value + 24)
+ return 0;
+ }
+ }
+ return 1;
+}
+
+static int try_cached_training(struct raminfo *info)
+{
+ u8 saved_243[2];
+ u8 tm;
+
+ int channel, slot, rank, lane;
+ int flip = 1;
+ int i, j;
+
+ if (!check_cached_sanity(info))
+ return 0;
+
+ info->training.reg178_center = info->cached_training->reg178_center;
+ info->training.reg178_smallest = info->cached_training->reg178_smallest;
+ info->training.reg178_largest = info->cached_training->reg178_largest;
+ memcpy(&info->training.timing_bounds,
+ &info->cached_training->timing_bounds,
+ sizeof(info->training.timing_bounds));
+ memcpy(&info->training.timing_offset,
+ &info->cached_training->timing_offset,
+ sizeof(info->training.timing_offset));
+
+ write_1d0(2, 0x142, 3, 1);
+ saved_243[0] = read_mchbar8(0x243);
+ saved_243[1] = read_mchbar8(0x643);
+ write_mchbar8(0x243, saved_243[0] | 2);
+ write_mchbar8(0x643, saved_243[1] | 2);
+ set_ecc(0);
+ pci_mm_write16(0, 0, 0, 0xc8, 3);
+ if (read_1d0(0x10b, 6) & 1)
+ set_10b(info, 0);
+ for (tm = 0; tm < 2; tm++) {
+ int totalrank;
+
+ set_178(tm ? info->cached_training->reg178_largest : info->
+ cached_training->reg178_smallest);
+
+ totalrank = 0;
+ /* Check timing ranges. With i == 0 we check smallest one and with
+ i == 1 the largest bound. With j == 0 we check that on the bound
+ it still works whereas with j == 1 we check that just outside of
+ bound we fail.
+ */
+ FOR_POPULATED_RANKS_BACKWARDS {
+ for (i = 0; i < 2; i++) {
+ for (lane = 0; lane < 8; lane++) {
+ write_500(info, channel,
+ info->cached_training->
+ timing2_bounds[channel][slot]
+ [rank][lane][i],
+ get_timing_register_addr(lane,
+ 3,
+ slot,
+ rank),
+ 9, 1);
+
+ if (!i)
+ write_500(info, channel,
+ info->
+ cached_training->
+ timing2_offset
+ [channel][slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, 2, slot, rank),
+ 9, 1);
+ write_500(info, channel,
+ i ? info->cached_training->
+ timing_bounds[tm][channel]
+ [slot][rank][lane].
+ largest : info->
+ cached_training->
+ timing_bounds[tm][channel]
+ [slot][rank][lane].smallest,
+ get_timing_register_addr(lane,
+ 0,
+ slot,
+ rank),
+ 9, 1);
+ write_500(info, channel,
+ info->cached_training->
+ timing_offset[channel][slot]
+ [rank][lane] +
+ (i ? info->cached_training->
+ timing_bounds[tm][channel]
+ [slot][rank][lane].
+ largest : info->
+ cached_training->
+ timing_bounds[tm][channel]
+ [slot][rank][lane].
+ smallest) - 64,
+ get_timing_register_addr(lane,
+ 1,
+ slot,
+ rank),
+ 9, 1);
+ }
+ for (j = 0; j < 2; j++) {
+ u8 failmask;
+ u8 expected_failmask;
+ char reg1b3;
+
+ reg1b3 = (j == 1) + 4;
+ reg1b3 =
+ j == i ? reg1b3 : (-reg1b3) & 0x3f;
+ write_1d0(reg1b3, 0x1bb, 6, 1);
+ write_1d0(reg1b3, 0x1b3, 6, 1);
+ write_1d0(reg1b3, 0x1a3, 6, 1);
+
+ flip = !flip;
+ write_testing(info, totalrank, flip);
+ failmask =
+ check_testing(info, totalrank,
+ flip);
+ expected_failmask =
+ j == 0 ? 0x00 : 0xff;
+ if (failmask != expected_failmask)
+ goto fail;
+ }
+ }
+ totalrank++;
+ }
+ }
+
+ set_178(info->cached_training->reg178_center);
+ if (info->use_ecc)
+ set_ecc(1);
+ write_training_data(info);
+ write_1d0(0, 322, 3, 1);
+ info->training = *info->cached_training;
+
+ write_1d0(0, 0x1bb, 6, 1);
+ write_1d0(0, 0x1b3, 6, 1);
+ write_1d0(0, 0x1a3, 6, 1);
+ write_mchbar8(0x243, saved_243[0]);
+ write_mchbar8(0x643, saved_243[1]);
+
+ return 1;
+
+fail:
+ FOR_POPULATED_RANKS {
+ write_500_timings_type(info, channel, slot, rank, 1);
+ write_500_timings_type(info, channel, slot, rank, 2);
+ write_500_timings_type(info, channel, slot, rank, 3);
+ }
+
+ write_1d0(0, 0x1bb, 6, 1);
+ write_1d0(0, 0x1b3, 6, 1);
+ write_1d0(0, 0x1a3, 6, 1);
+ write_mchbar8(0x243, saved_243[0]);
+ write_mchbar8(0x643, saved_243[1]);
+
+ return 0;
+}
+
+static void do_ram_training(struct raminfo *info)
+{
+ u8 saved_243[2];
+ int totalrank = 0;
+ u8 reg_178;
+ int niter;
+
+ timing_bounds_t timings[64];
+ int lane, rank, slot, channel;
+ u8 reg178_center;
+
+ write_1d0(2, 0x142, 3, 1);
+ saved_243[0] = read_mchbar8(0x243);
+ saved_243[1] = read_mchbar8(0x643);
+ write_mchbar8(0x243, saved_243[0] | 2);
+ write_mchbar8(0x643, saved_243[1] | 2);
+ switch (info->clock_speed_index) {
+ case 0:
+ niter = 5;
+ break;
+ case 1:
+ niter = 10;
+ break;
+ default:
+ niter = 19;
+ break;
+ }
+ set_ecc(0);
+
+ FOR_POPULATED_RANKS_BACKWARDS {
+ int i;
+
+ write_500_timings_type(info, channel, slot, rank, 0);
+
+ write_testing(info, totalrank, 0);
+ for (i = 0; i < niter; i++) {
+ write_testing_type2(info, totalrank, 2, i, 0);
+ write_testing_type2(info, totalrank, 3, i, 1);
+ }
+ pci_mm_write8(0, 0, 0, 0xc0, 0x01);
+ totalrank++;
+ }
+
+ if (reg178_min[info->clock_speed_index] <
+ reg178_max[info->clock_speed_index])
+ memset(timings[reg178_min[info->clock_speed_index]], 0,
+ sizeof(timings[0]) *
+ (reg178_max[info->clock_speed_index] -
+ reg178_min[info->clock_speed_index]));
+ for (reg_178 = reg178_min[info->clock_speed_index];
+ reg_178 < reg178_max[info->clock_speed_index];
+ reg_178 += reg178_step[info->clock_speed_index]) {
+ totalrank = 0;
+ set_178(reg_178);
+ for (channel = NUM_CHANNELS - 1; channel >= 0; channel--)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++) {
+ memset(&timings[reg_178][channel][slot]
+ [rank][0].smallest, 0, 16);
+ if (info->
+ populated_ranks[channel][slot]
+ [rank]) {
+ train_ram_at_178(info, channel,
+ slot, rank,
+ totalrank,
+ reg_178, 1,
+ niter,
+ timings);
+ totalrank++;
+ }
+ }
+ }
+
+ reg178_center = choose_reg178(info, timings);
+
+ FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) {
+ info->training.timing_bounds[0][channel][slot][rank][lane].
+ smallest =
+ timings[info->training.
+ reg178_smallest][channel][slot][rank][lane].
+ smallest;
+ info->training.timing_bounds[0][channel][slot][rank][lane].
+ largest =
+ timings[info->training.
+ reg178_smallest][channel][slot][rank][lane].largest;
+ info->training.timing_bounds[1][channel][slot][rank][lane].
+ smallest =
+ timings[info->training.
+ reg178_largest][channel][slot][rank][lane].smallest;
+ info->training.timing_bounds[1][channel][slot][rank][lane].
+ largest =
+ timings[info->training.
+ reg178_largest][channel][slot][rank][lane].largest;
+ info->training.timing_offset[channel][slot][rank][lane] =
+ info->training.lane_timings[1][channel][slot][rank][lane]
+ -
+ info->training.lane_timings[0][channel][slot][rank][lane] +
+ 64;
+ }
+
+ if (info->silicon_revision == 1
+ && (info->
+ populated_ranks_mask[1] ^ (info->
+ populated_ranks_mask[1] >> 2)) & 1) {
+ int ranks_after_channel1;
+
+ totalrank = 0;
+ for (reg_178 = reg178_center - 18;
+ reg_178 <= reg178_center + 18; reg_178 += 18) {
+ totalrank = 0;
+ set_178(reg_178);
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++) {
+ if (info->
+ populated_ranks[1][slot][rank]) {
+ train_ram_at_178(info, 1, slot,
+ rank,
+ totalrank,
+ reg_178, 0,
+ niter,
+ timings);
+ totalrank++;
+ }
+ }
+ }
+ ranks_after_channel1 = totalrank;
+
+ for (reg_178 = reg178_center - 12;
+ reg_178 <= reg178_center + 12; reg_178 += 12) {
+ totalrank = ranks_after_channel1;
+ set_178(reg_178);
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ if (info->
+ populated_ranks[0][slot][rank]) {
+ train_ram_at_178(info, 0, slot,
+ rank,
+ totalrank,
+ reg_178, 0,
+ niter,
+ timings);
+ totalrank++;
+ }
+
+ }
+ } else {
+ for (reg_178 = reg178_center - 12;
+ reg_178 <= reg178_center + 12; reg_178 += 12) {
+ totalrank = 0;
+ set_178(reg_178);
+ FOR_POPULATED_RANKS_BACKWARDS {
+ train_ram_at_178(info, channel, slot, rank,
+ totalrank, reg_178, 0, niter,
+ timings);
+ totalrank++;
+ }
+ }
+ }
+
+ set_178(reg178_center);
+ FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) {
+ u16 tm0;
+
+ tm0 =
+ choose_training(info, channel, slot, rank, lane, timings,
+ reg178_center);
+ write_500(info, channel, tm0,
+ get_timing_register_addr(lane, 0, slot, rank), 9, 1);
+ write_500(info, channel,
+ tm0 +
+ info->training.
+ lane_timings[1][channel][slot][rank][lane] -
+ info->training.
+ lane_timings[0][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 1, slot, rank), 9, 1);
+ }
+
+ totalrank = 0;
+ FOR_POPULATED_RANKS_BACKWARDS {
+ try_timing_offsets(info, channel, slot, rank, totalrank);
+ totalrank++;
+ }
+ write_mchbar8(0x243, saved_243[0]);
+ write_mchbar8(0x643, saved_243[1]);
+ write_1d0(0, 0x142, 3, 1);
+ info->training.reg178_center = reg178_center;
+}
+
+static void ram_training(struct raminfo *info)
+{
+ u16 saved_fc4;
+
+ saved_fc4 = read_mchbar16(0xfc4);
+ write_mchbar16(0xfc4, 0xffff);
+
+ if (info->revision >= 8)
+ read_4090(info);
+
+ if (!try_cached_training(info))
+ do_ram_training(info);
+ if ((info->silicon_revision == 2 || info->silicon_revision == 3)
+ && info->clock_speed_index < 2)
+ set_10b(info, 1);
+ write_mchbar16(0xfc4, saved_fc4);
+}
+
+static unsigned gcd(unsigned a, unsigned b)
+{
+ unsigned t;
+ if (a > b) {
+ t = a;
+ a = b;
+ b = t;
+ }
+ /* invariant a < b. */
+ while (a) {
+ t = b % a;
+ b = a;
+ a = t;
+ }
+ return b;
+}
+
+static inline int div_roundup(int a, int b)
+{
+ return (a + b - 1) / b;
+}
+
+static unsigned lcm(unsigned a, unsigned b)
+{
+ return (a * b) / gcd(a, b);
+}
+
+struct stru1 {
+ u8 freqs_reversed;
+ u8 freq_diff_reduced;
+ u8 freq_min_reduced;
+ u8 divisor_f4_to_fmax;
+ u8 divisor_f3_to_fmax;
+ u8 freq4_to_max_remainder;
+ u8 freq3_to_2_remainder;
+ u8 freq3_to_2_remaindera;
+ u8 freq4_to_2_remainder;
+ int divisor_f3_to_f1, divisor_f4_to_f2;
+ int common_time_unit_ps;
+ int freq_max_reduced;
+};
+
+static void
+compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2,
+ int num_cycles_2, int num_cycles_1, int round_it,
+ int add_freqs, struct stru1 *result)
+{
+ int g;
+ int common_time_unit_ps;
+ int freq1_reduced, freq2_reduced;
+ int freq_min_reduced;
+ int freq_max_reduced;
+ int freq3, freq4;
+
+ g = gcd(freq1, freq2);
+ freq1_reduced = freq1 / g;
+ freq2_reduced = freq2 / g;
+ freq_min_reduced = min(freq1_reduced, freq2_reduced);
+ freq_max_reduced = max(freq1_reduced, freq2_reduced);
+
+ common_time_unit_ps = div_roundup(900000, lcm(freq1, freq2));
+ freq3 = div_roundup(num_cycles_2, common_time_unit_ps) - 1;
+ freq4 = div_roundup(num_cycles_1, common_time_unit_ps) - 1;
+ if (add_freqs) {
+ freq3 += freq2_reduced;
+ freq4 += freq1_reduced;
+ }
+
+ if (round_it) {
+ result->freq3_to_2_remainder = 0;
+ result->freq3_to_2_remaindera = 0;
+ result->freq4_to_max_remainder = 0;
+ result->divisor_f4_to_f2 = 0;
+ result->divisor_f3_to_f1 = 0;
+ } else {
+ if (freq2_reduced < freq1_reduced) {
+ result->freq3_to_2_remainder =
+ result->freq3_to_2_remaindera =
+ freq3 % freq1_reduced - freq1_reduced + 1;
+ result->freq4_to_max_remainder =
+ -(freq4 % freq1_reduced);
+ result->divisor_f3_to_f1 = freq3 / freq1_reduced;
+ result->divisor_f4_to_f2 =
+ (freq4 -
+ (freq1_reduced - freq2_reduced)) / freq2_reduced;
+ result->freq4_to_2_remainder =
+ -(char)((freq1_reduced - freq2_reduced) +
+ ((u8) freq4 -
+ (freq1_reduced -
+ freq2_reduced)) % (u8) freq2_reduced);
+ } else {
+ if (freq2_reduced > freq1_reduced) {
+ result->freq4_to_max_remainder =
+ (freq4 % freq2_reduced) - freq2_reduced + 1;
+ result->freq4_to_2_remainder =
+ freq4 % freq_max_reduced -
+ freq_max_reduced + 1;
+ } else {
+ result->freq4_to_max_remainder =
+ -(freq4 % freq2_reduced);
+ result->freq4_to_2_remainder =
+ -(char)(freq4 % freq_max_reduced);
+ }
+ result->divisor_f4_to_f2 = freq4 / freq2_reduced;
+ result->divisor_f3_to_f1 =
+ (freq3 -
+ (freq2_reduced - freq1_reduced)) / freq1_reduced;
+ result->freq3_to_2_remainder = -(freq3 % freq2_reduced);
+ result->freq3_to_2_remaindera =
+ -(char)((freq_max_reduced - freq_min_reduced) +
+ (freq3 -
+ (freq_max_reduced -
+ freq_min_reduced)) % freq1_reduced);
+ }
+ }
+ result->divisor_f3_to_fmax = freq3 / freq_max_reduced;
+ result->divisor_f4_to_fmax = freq4 / freq_max_reduced;
+ if (round_it) {
+ if (freq2_reduced > freq1_reduced) {
+ if (freq3 % freq_max_reduced)
+ result->divisor_f3_to_fmax++;
+ }
+ if (freq2_reduced < freq1_reduced) {
+ if (freq4 % freq_max_reduced)
+ result->divisor_f4_to_fmax++;
+ }
+ }
+ result->freqs_reversed = (freq2_reduced < freq1_reduced);
+ result->freq_diff_reduced = freq_max_reduced - freq_min_reduced;
+ result->freq_min_reduced = freq_min_reduced;
+ result->common_time_unit_ps = common_time_unit_ps;
+ result->freq_max_reduced = freq_max_reduced;
+}
+
+static void
+set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
+ int num_cycles_2, int num_cycles_1, int num_cycles_3,
+ int num_cycles_4, int reverse)
+{
+ struct stru1 vv;
+ char multiplier;
+
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1,
+ 0, 1, &vv);
+
+ multiplier =
+ div_roundup(max
+ (div_roundup(num_cycles_2, vv.common_time_unit_ps) +
+ div_roundup(num_cycles_3, vv.common_time_unit_ps),
+ div_roundup(num_cycles_1,
+ vv.common_time_unit_ps) +
+ div_roundup(num_cycles_4, vv.common_time_unit_ps))
+ + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1;
+
+ u32 y =
+ (u8) ((vv.freq_max_reduced - vv.freq_min_reduced) +
+ vv.freq_max_reduced * multiplier)
+ | (vv.
+ freqs_reversed << 8) | ((u8) (vv.freq_min_reduced *
+ multiplier) << 16) | ((u8) (vv.
+ freq_min_reduced
+ *
+ multiplier)
+ << 24);
+ u32 x =
+ vv.freq3_to_2_remaindera | (vv.freq4_to_2_remainder << 8) | (vv.
+ divisor_f3_to_f1
+ << 16)
+ | (vv.divisor_f4_to_f2 << 20) | (vv.freq_min_reduced << 24);
+ if (reverse) {
+ write_mchbar32(reg, y);
+ write_mchbar32(reg + 4, x);
+ } else {
+ write_mchbar32(reg + 4, y);
+ write_mchbar32(reg, x);
+ }
+}
+
+static void
+set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
+ int num_cycles_1, int num_cycles_2, int num_cycles_3,
+ int num_cycles_4)
+{
+ struct stru1 ratios1;
+ struct stru1 ratios2;
+
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_1, num_cycles_2,
+ 0, 1, &ratios2);
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4,
+ 0, 1, &ratios1);
+ write_mchbar32(reg,
+ ratios1.freq4_to_max_remainder | (ratios2.
+ freq4_to_max_remainder
+ << 8)
+ | (ratios1.divisor_f4_to_fmax << 16) | (ratios2.
+ divisor_f4_to_fmax
+ << 20));
+}
+
+static void
+set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
+ int num_cycles_2, int num_cycles_1, int round_it, int add_freqs)
+{
+ struct stru1 ratios;
+
+ compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1,
+ round_it, add_freqs, &ratios);
+ switch (mode) {
+ case 0:
+ write_mchbar32(reg + 4,
+ ratios.freq_diff_reduced | (ratios.
+ freqs_reversed <<
+ 8));
+ write_mchbar32(reg,
+ ratios.freq3_to_2_remainder | (ratios.
+ freq4_to_max_remainder
+ << 8)
+ | (ratios.divisor_f3_to_fmax << 16) | (ratios.
+ divisor_f4_to_fmax
+ << 20) |
+ (ratios.freq_min_reduced << 24));
+ break;
+
+ case 1:
+ write_mchbar32(reg,
+ ratios.freq3_to_2_remainder | (ratios.
+ divisor_f3_to_fmax
+ << 16));
+ break;
+
+ case 2:
+ write_mchbar32(reg,
+ ratios.freq3_to_2_remainder | (ratios.
+ freq4_to_max_remainder
+ << 8) | (ratios.
+ divisor_f3_to_fmax
+ << 16) |
+ (ratios.divisor_f4_to_fmax << 20));
+ break;
+
+ case 4:
+ write_mchbar32(reg, (ratios.divisor_f3_to_fmax << 4)
+ | (ratios.divisor_f4_to_fmax << 8) | (ratios.
+ freqs_reversed
+ << 12) |
+ (ratios.freq_min_reduced << 16) | (ratios.
+ freq_diff_reduced
+ << 24));
+ break;
+ }
+}
+
+static void set_2dxx_series(struct raminfo *info)
+{
+ set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005,
+ 0, 1);
+ set_2dx8_reg(info, 0x2d08, 0, 0x78, 0x78, 3273, 5033, 1, 1);
+ set_2dx8_reg(info, 0x2d10, 0, 0x78, info->fsb_frequency, 1475, 1131, 0,
+ 1);
+ set_2dx8_reg(info, 0x2d18, 0, 2 * info->fsb_frequency,
+ frequency_11(info), 1231, 1524, 0, 1);
+ set_2dx8_reg(info, 0x2d20, 0, 2 * info->fsb_frequency,
+ frequency_11(info) / 2, 1278, 2008, 0, 1);
+ set_2dx8_reg(info, 0x2d28, 0, info->fsb_frequency, frequency_11(info),
+ 1167, 1539, 0, 1);
+ set_2dx8_reg(info, 0x2d30, 0, info->fsb_frequency,
+ frequency_11(info) / 2, 1403, 1318, 0, 1);
+ set_2dx8_reg(info, 0x2d38, 0, info->fsb_frequency, 0x78, 3460, 5363, 1,
+ 1);
+ set_2dx8_reg(info, 0x2d40, 0, info->fsb_frequency, 0x3c, 2792, 5178, 1,
+ 1);
+ set_2dx8_reg(info, 0x2d48, 0, 2 * info->fsb_frequency, 0x78, 2738, 4610,
+ 1, 1);
+ set_2dx8_reg(info, 0x2d50, 0, info->fsb_frequency, 0x78, 2819, 5932, 1,
+ 1);
+ set_2dx8_reg(info, 0x6d4, 1, info->fsb_frequency,
+ frequency_11(info) / 2, 4000, 0, 0, 0);
+ set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency,
+ frequency_11(info) / 2, 4000, 4000, 0, 0);
+
+ set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0,
+ info->delay46_ps[0], 0, info->delay54_ps[0]);
+ set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency,
+ frequency_11(info), 2500, 0, 0, 0);
+ set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency,
+ frequency_11(info) / 2, 3500, 0, 0, 0);
+ set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0,
+ info->delay46_ps[1], 0, info->delay54_ps[1]);
+ set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0);
+ set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455,
+ 470, 0);
+ set_2d5x_reg(info, 0x2d68, 0x195, 0x3c, 2707, 5632, 3277, 2207, 0);
+ set_2d5x_reg(info, 0x2d70, 0x195, frequency_11(info) / 2, 1276, 758,
+ 454, 459, 0);
+ set_2d5x_reg(info, 0x2d78, 0x195, 0x78, 1021, 799, 510, 513, 0);
+ set_2d5x_reg(info, 0x2d80, info->fsb_frequency, 0xe1, 0, 2862, 2579,
+ 2588, 0);
+ set_2d5x_reg(info, 0x2d88, info->fsb_frequency, 0xe1, 0, 2690, 2405,
+ 2405, 0);
+ set_2d5x_reg(info, 0x2da0, 0x78, 0xe1, 0, 2560, 2264, 2251, 0);
+ set_2d5x_reg(info, 0x2da8, 0x195, frequency_11(info), 1060, 775, 484,
+ 480, 0);
+ set_2d5x_reg(info, 0x2db0, 0x195, 0x78, 4183, 6023, 2217, 2048, 0);
+ write_mchbar32(0x2dbc, ((frequency_11(info) / 2) - 1) | 0xe00000);
+ write_mchbar32(0x2db8, ((info->fsb_frequency - 1) << 16) | 0x77);
+}
+
+static u16 get_max_timing(struct raminfo *info, int channel)
+{
+ int slot, rank, lane;
+ u16 ret = 0;
+
+ if ((read_mchbar8(0x2ca8) >> 2) < 1)
+ return 384;
+
+ if (info->revision < 8)
+ return 256;
+
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ if (info->populated_ranks[channel][slot][rank])
+ for (lane = 0; lane < 8 + info->use_ecc; lane++)
+ ret = max(ret, read_500(info, channel,
+ get_timing_register_addr
+ (lane, 0, slot,
+ rank), 9));
+ return ret;
+}
+
+static void set_274265(struct raminfo *info)
+{
+ int delay_a_ps, delay_b_ps, delay_c_ps, delay_d_ps;
+ int delay_e_ps, delay_e_cycles, delay_f_cycles;
+ int delay_e_over_cycle_ps;
+ int cycletime_ps;
+ int channel;
+
+ delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info);
+ info->reg2ca9_bit0 = 0;
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ cycletime_ps =
+ 900000 / lcm(2 * info->fsb_frequency, frequency_11(info));
+ delay_d_ps =
+ (halfcycle_ps(info) * get_max_timing(info, channel) >> 6)
+ - info->some_delay_3_ps_rounded + 200;
+ if (!
+ ((info->silicon_revision == 0
+ || info->silicon_revision == 1)
+ && (info->revision >= 8)))
+ delay_d_ps += halfcycle_ps(info) * 2;
+ delay_d_ps +=
+ halfcycle_ps(info) * (!info->revision_flag_1 +
+ info->some_delay_2_halfcycles_ceil +
+ 2 * info->some_delay_1_cycle_floor +
+ info->clock_speed_index +
+ 2 * info->cas_latency - 7 + 11);
+ delay_d_ps += info->revision >= 8 ? 2758 : 4428;
+
+ write_mchbar32(0x140,
+ (read_mchbar32(0x140) & 0xfaffffff) | 0x2000000);
+ write_mchbar32(0x138,
+ (read_mchbar32(0x138) & 0xfaffffff) | 0x2000000);
+ if ((read_mchbar8(0x144) & 0x1f) > 0x13)
+ delay_d_ps += 650;
+ delay_c_ps = delay_d_ps + 1800;
+ if (delay_c_ps <= delay_a_ps)
+ delay_e_ps = 0;
+ else
+ delay_e_ps =
+ cycletime_ps * div_roundup(delay_c_ps - delay_a_ps,
+ cycletime_ps);
+
+ delay_e_over_cycle_ps = delay_e_ps % (2 * halfcycle_ps(info));
+ delay_e_cycles = delay_e_ps / (2 * halfcycle_ps(info));
+ delay_f_cycles =
+ div_roundup(2500 - delay_e_over_cycle_ps,
+ 2 * halfcycle_ps(info));
+ if (delay_f_cycles > delay_e_cycles) {
+ info->delay46_ps[channel] = delay_e_ps;
+ delay_e_cycles = 0;
+ } else {
+ info->delay46_ps[channel] =
+ delay_e_over_cycle_ps +
+ 2 * halfcycle_ps(info) * delay_f_cycles;
+ delay_e_cycles -= delay_f_cycles;
+ }
+
+ if (info->delay46_ps[channel] < 2500) {
+ info->delay46_ps[channel] = 2500;
+ info->reg2ca9_bit0 = 1;
+ }
+ delay_b_ps = halfcycle_ps(info) + delay_c_ps;
+ if (delay_b_ps <= delay_a_ps)
+ delay_b_ps = 0;
+ else
+ delay_b_ps -= delay_a_ps;
+ info->delay54_ps[channel] =
+ cycletime_ps * div_roundup(delay_b_ps,
+ cycletime_ps) -
+ 2 * halfcycle_ps(info) * delay_e_cycles;
+ if (info->delay54_ps[channel] < 2500)
+ info->delay54_ps[channel] = 2500;
+ info->reg274265[channel][0] = delay_e_cycles;
+ if (delay_d_ps + 7 * halfcycle_ps(info) <=
+ 24 * halfcycle_ps(info))
+ info->reg274265[channel][1] = 0;
+ else
+ info->reg274265[channel][1] =
+ div_roundup(delay_d_ps + 7 * halfcycle_ps(info),
+ 4 * halfcycle_ps(info)) - 6;
+ write_mchbar32((channel << 10) + 0x274,
+ info->reg274265[channel][1] | (info->
+ reg274265[channel]
+ [0] << 16));
+ info->reg274265[channel][2] =
+ div_roundup(delay_c_ps + 3 * fsbcycle_ps(info),
+ 4 * halfcycle_ps(info)) + 1;
+ write_mchbar16((channel << 10) + 0x265,
+ info->reg274265[channel][2] << 8);
+ }
+ if (info->reg2ca9_bit0)
+ write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1);
+ else
+ write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1);
+}
+
+static void restore_274265(struct raminfo *info)
+{
+ int channel;
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar32((channel << 10) + 0x274,
+ (info->reg274265[channel][0] << 16) | info->
+ reg274265[channel][1]);
+ write_mchbar16((channel << 10) + 0x265,
+ info->reg274265[channel][2] << 8);
+ }
+ if (info->reg2ca9_bit0)
+ write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1);
+ else
+ write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1);
+}
+
+#if REAL
+static void dmi_setup(void)
+{
+ gav(read8(DEFAULT_DMIBAR | 0x254));
+ write8(DEFAULT_DMIBAR | 0x254, 0x1);
+ write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+ read_mchbar16(0x48);
+ write_mchbar16(0x48, 0x2);
+
+ write32(DEFAULT_DMIBAR | 0xd68, read32(DEFAULT_DMIBAR | 0xd68) | 0x08000000);
+
+ outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
+ DEFAULT_GPIOBASE | 0x38);
+ gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e
+}
+#endif
+
+static void
+set_fsb_frequency (void)
+{
+ u8 block[5];
+ u16 fsbfreq = 62879;
+ smbus_block_read(0x69, 0, 5, block);
+ block[0] = fsbfreq;
+ block[1] = fsbfreq >> 8;
+
+ smbus_block_write(0x69, 0, 5, block);
+}
+
+#if REAL
+void raminit(const int s3resume)
+#else
+void raminit(int s3resume)
+#endif
+{
+ unsigned channel, slot, lane, rank;
+ int i;
+ struct raminfo info;
+#if CONFIG_COLLECT_TIMESTAMPS
+ extern tsc_t before_spd, after_spd, before_training, after_training;
+#endif
+
+#if !REAL
+ pre_raminit1();
+#endif
+
+ if (s3resume) {
+ read_mchbar32(0x1e8);
+ write_mchbar32(0x1e8, 0x6);
+ read_mchbar32(0x1e8);
+ write_mchbar32(0x1e8, 0x4);
+ }
+
+#if !REAL
+ pre_raminit_2();
+#endif
+ u8 x2ca8;
+
+ gav(x2ca8 = read_mchbar8(0x2ca8));
+ if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) {
+ printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+ write_mchbar8(0x2ca8, 0);
+ outb(0xe, 0xcf9);
+#if REAL
+ while (1) {
+ asm volatile ("hlt");
+ }
+#else
+ printf("CP5\n");
+ exit(0);
+#endif
+ }
+#if !REAL
+ if (!s3resume) {
+ pre_raminit_3(x2ca8);
+ }
+#endif
+
+#if !REAL
+ pre_raminit_4a();
+#endif
+
+ dmi_setup();
+
+ write_mchbar16(0x1170, 0xa880);
+ write_mchbar8(0x11c1, 0x1);
+ write_mchbar16(0x1170, 0xb880);
+ read_mchbar8(0x1210);
+ write_mchbar8(0x1210, 0x84);
+ pci_mm_read8(NORTHBRIDGE, D0F0_GGC); // = 0x52
+ pci_mm_write8(NORTHBRIDGE, D0F0_GGC, 0x2);
+ pci_mm_read8(NORTHBRIDGE, D0F0_GGC); // = 0x2
+ pci_mm_write8(NORTHBRIDGE, D0F0_GGC, 0x52);
+ pci_mm_read16(NORTHBRIDGE, D0F0_GGC); // = 0xb52
+
+ pci_mm_write16(NORTHBRIDGE, D0F0_GGC, 0xb52);
+
+ u16 deven;
+ deven = pci_mm_read16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3
+
+ if (deven & 8) {
+ write_mchbar8(0x2c30, 0x20);
+ pci_mm_read8(0, 0x0, 0x0, 0x8); // = 0x18
+ write_mchbar16(0x2c30, read_mchbar16(0x2c30) | 0x200);
+ write_mchbar16(0x2c32, 0x434);
+ read_mchbar32(0x2c44);
+ write_mchbar32(0x2c44, 0x1053687);
+ pci_mm_read8(0, 0x2, 0x0, 0x62); // = 0x2
+ pci_mm_write8(0, 0x2, 0x0, 0x62, 0x2);
+ read8(DEFAULT_RCBA | 0x2318);
+ write8(DEFAULT_RCBA | 0x2318, 0x47);
+ read8(DEFAULT_RCBA | 0x2320);
+ write8(DEFAULT_RCBA | 0x2320, 0xfc);
+ }
+
+ read_mchbar32(0x30);
+ write_mchbar32(0x30, 0x40);
+
+ pci_mm_read8(SOUTHBRIDGE, 0x8); // = 0x6
+ pci_mm_read16(NORTHBRIDGE, D0F0_GGC); // = 0xb52
+ pci_mm_write16(NORTHBRIDGE, D0F0_GGC, 0xb50);
+ gav(read32(DEFAULT_RCBA | 0x3428));
+ write32(DEFAULT_RCBA | 0x3428, 0x1d);
+
+#if !REAL
+ pre_raminit_5(s3resume);
+#else
+ set_fsb_frequency();
+#endif
+
+ memset(&info, 0x5a, sizeof(info));
+
+ info.last_500_command[0] = 0;
+ info.last_500_command[1] = 0;
+
+ info.fsb_frequency = 135 * 2;
+ info.board_lane_delay[0] = 0x14;
+ info.board_lane_delay[1] = 0x07;
+ info.board_lane_delay[2] = 0x07;
+ info.board_lane_delay[3] = 0x08;
+ info.board_lane_delay[4] = 0x56;
+ info.board_lane_delay[5] = 0x04;
+ info.board_lane_delay[6] = 0x04;
+ info.board_lane_delay[7] = 0x05;
+ info.board_lane_delay[8] = 0x10;
+
+ info.training.reg_178 = 0;
+ info.training.reg_10b = 0;
+
+ info.heci_bar = 0;
+ info.memory_reserved_for_heci_mb = 0;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_spd = rdtsc();
+#endif
+
+ if (!s3resume || REAL) {
+ pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
+
+ collect_system_info(&info);
+
+#if REAL
+ /* Enable SMBUS. */
+ enable_smbus();
+#endif
+
+ memset(&info.populated_ranks, 0, sizeof(info.populated_ranks));
+
+ info.use_ecc = 1;
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_CHANNELS; slot++) {
+ int v;
+ int try;
+ int addr;
+ const u8 useful_addresses[] = {
+ DEVICE_TYPE,
+ MODULE_TYPE,
+ DENSITY,
+ RANKS_AND_DQ,
+ MEMORY_BUS_WIDTH,
+ TIMEBASE_DIVIDEND,
+ TIMEBASE_DIVISOR,
+ CYCLETIME,
+ CAS_LATENCIES_LSB,
+ CAS_LATENCIES_MSB,
+ CAS_LATENCY_TIME,
+ 0x11, 0x12, 0x13, 0x14, 0x15,
+ 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
+ 0x1c, 0x1d,
+ THERMAL_AND_REFRESH,
+ 0x20,
+ REFERENCE_RAW_CARD_USED,
+ RANK1_ADDRESS_MAPPING,
+ 0x75, 0x76, 0x77, 0x78,
+ 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e,
+ 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84,
+ 0x85, 0x86, 0x87, 0x88,
+ 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e,
+ 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94,
+ 0x95
+ };
+ if (slot)
+ continue;
+ for (try = 0; try < 5; try++) {
+ v = smbus_read_byte(0x50 + channel,
+ DEVICE_TYPE);
+ if (v >= 0)
+ break;
+ }
+ if (v < 0)
+ continue;
+ for (addr = 0;
+ addr <
+ sizeof(useful_addresses) /
+ sizeof(useful_addresses[0]); addr++)
+ gav(info.
+ spd[channel][0][useful_addresses
+ [addr]] =
+ smbus_read_byte(0x50 + channel,
+ useful_addresses
+ [addr]));
+ if (info.spd[channel][0][DEVICE_TYPE] != 11)
+ die("Only DDR3 is supported");
+
+ v = info.spd[channel][0][RANKS_AND_DQ];
+ info.populated_ranks[channel][0][0] = 1;
+ info.populated_ranks[channel][0][1] =
+ ((v >> 3) & 7);
+ if (((v >> 3) & 7) > 1)
+ die("At most 2 ranks are supported");
+ if ((v & 7) == 0 || (v & 7) > 2)
+ die("Only x8 and x16 modules are supported");
+ if ((info.
+ spd[channel][slot][MODULE_TYPE] & 0xF) != 2
+ && (info.
+ spd[channel][slot][MODULE_TYPE] & 0xF)
+ != 3)
+ die("Registered memory is not supported");
+ info.is_x16_module[channel][0] = (v & 7) - 1;
+ info.density[channel][slot] =
+ info.spd[channel][slot][DENSITY] & 0xF;
+ if (!
+ (info.
+ spd[channel][slot][MEMORY_BUS_WIDTH] &
+ 0x18))
+ info.use_ecc = 0;
+ }
+
+ gav(0x55);
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ int v = 0;
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ v |= info.
+ populated_ranks[channel][slot][rank]
+ << (2 * slot + rank);
+ info.populated_ranks_mask[channel] = v;
+ }
+
+ gav(0x55);
+
+ gav(pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0 + 4));
+ } else {
+ memset(info.populated_ranks, 0, sizeof(info.populated_ranks));
+#if 0
+ info.populated_ranks[0][0][0] = 1;
+ info.populated_ranks[0][0][1] = 1;
+ info.populated_ranks_mask[0] = 3;
+ info.populated_ranks_mask[1] = 0;
+ info.use_ecc = 0;
+ info.max_slots_used_in_channel = 1;
+
+ info.spd[0][0][0x02] = 0x0b;
+ info.spd[0][0][0x03] = 0x03;
+ info.spd[0][0][0x04] = 0x03;
+ info.spd[0][0][0x07] = 0x09;
+ info.spd[0][0][0x08] = 0x03;
+ info.spd[0][0][0x0a] = 0x01;
+ info.spd[0][0][0x0b] = 0x08;
+ info.spd[0][0][0x0c] = 0x0c;
+ info.spd[0][0][0x0e] = 0x3e;
+ info.spd[0][0][0x0f] = 0x00;
+ info.spd[0][0][0x10] = 0x69;
+ info.spd[0][0][0x11] = 0x78;
+ info.spd[0][0][0x12] = 0x69;
+ info.spd[0][0][0x13] = 0x30;
+ info.spd[0][0][0x14] = 0x69;
+ info.spd[0][0][0x15] = 0x11;
+ info.spd[0][0][0x16] = 0x20;
+ info.spd[0][0][0x17] = 0x89;
+ info.spd[0][0][0x18] = 0x00;
+ info.spd[0][0][0x19] = 0x05;
+ info.spd[0][0][0x1a] = 0x3c;
+ info.spd[0][0][0x1b] = 0x3c;
+ info.spd[0][0][0x1c] = 0x00;
+ info.spd[0][0][0x1d] = 0xf0;
+ info.spd[0][0][0x1f] = 0x05;
+ info.spd[0][0][0x20] = 0x00;
+ info.spd[0][0][0x3e] = 0x05;
+ info.spd[0][0][0x3f] = 0x00;
+ info.spd[0][0][0x75] = 0x80;
+ info.spd[0][0][0x76] = 0xad;
+ info.spd[0][0][0x77] = 0x01;
+ info.spd[0][0][0x78] = 0x10;
+ info.spd[0][0][0x79] = 0x52;
+ info.spd[0][0][0x7a] = 0x26;
+ info.spd[0][0][0x7b] = 0x50;
+ info.spd[0][0][0x7c] = 0xf4;
+ info.spd[0][0][0x7d] = 0x7d;
+ info.spd[0][0][0x7e] = 0xb0;
+ info.spd[0][0][0x7f] = 0xcf;
+ info.spd[0][0][0x80] = 0x48;
+ info.spd[0][0][0x81] = 0x4d;
+ info.spd[0][0][0x82] = 0x54;
+ info.spd[0][0][0x83] = 0x33;
+ info.spd[0][0][0x84] = 0x35;
+ info.spd[0][0][0x85] = 0x31;
+ info.spd[0][0][0x86] = 0x53;
+ info.spd[0][0][0x87] = 0x36;
+ info.spd[0][0][0x88] = 0x42;
+ info.spd[0][0][0x89] = 0x46;
+ info.spd[0][0][0x8a] = 0x52;
+ info.spd[0][0][0x8b] = 0x38;
+ info.spd[0][0][0x8c] = 0x43;
+ info.spd[0][0][0x8d] = 0x2d;
+ info.spd[0][0][0x8e] = 0x48;
+ info.spd[0][0][0x8f] = 0x39;
+ info.spd[0][0][0x90] = 0x20;
+ info.spd[0][0][0x91] = 0x20;
+ info.spd[0][0][0x92] = 0x4e;
+ info.spd[0][0][0x93] = 0x30;
+ info.spd[0][0][0x94] = 0x80;
+ info.spd[0][0][0x95] = 0xad;
+#else
+ info.populated_ranks[0][0][0] = 1;
+ info.populated_ranks[0][0][1] = 1;
+ info.populated_ranks[1][0][0] = 1;
+ info.populated_ranks[1][0][1] = 1;
+ info.populated_ranks_mask[0] = 3;
+ info.populated_ranks_mask[1] = 3;
+ info.use_ecc = 0;
+ info.max_slots_used_in_channel = 1;
+
+ info.spd[0][0][0x02] = 0x0b;
+ info.spd[0][0][0x03] = 0x03;
+ info.spd[0][0][0x04] = 0x03;
+ info.spd[0][0][0x07] = 0x09;
+ info.spd[0][0][0x08] = 0x03;
+ info.spd[0][0][0x0a] = 0x01;
+ info.spd[0][0][0x0b] = 0x08;
+ info.spd[0][0][0x0c] = 0x0c;
+ info.spd[0][0][0x0e] = 0x3e;
+ info.spd[0][0][0x0f] = 0x00;
+ info.spd[0][0][0x10] = 0x69;
+ info.spd[0][0][0x11] = 0x78;
+ info.spd[0][0][0x12] = 0x69;
+ info.spd[0][0][0x13] = 0x30;
+ info.spd[0][0][0x14] = 0x69;
+ info.spd[0][0][0x15] = 0x11;
+ info.spd[0][0][0x16] = 0x20;
+ info.spd[0][0][0x17] = 0x89;
+ info.spd[0][0][0x18] = 0x00;
+ info.spd[0][0][0x19] = 0x05;
+ info.spd[0][0][0x1a] = 0x3c;
+ info.spd[0][0][0x1b] = 0x3c;
+ info.spd[0][0][0x1c] = 0x00;
+ info.spd[0][0][0x1d] = 0xf0;
+ info.spd[0][0][0x1f] = 0x05;
+ info.spd[0][0][0x20] = 0x00;
+ info.spd[0][0][0x3e] = 0x05;
+ info.spd[0][0][0x3f] = 0x00;
+ info.spd[0][0][0x75] = 0x80;
+ info.spd[0][0][0x76] = 0xad;
+ info.spd[0][0][0x77] = 0x01;
+ info.spd[0][0][0x78] = 0x10;
+ info.spd[0][0][0x79] = 0x52;
+ info.spd[0][0][0x7a] = 0x26;
+ info.spd[0][0][0x7b] = 0x50;
+ info.spd[0][0][0x7c] = 0xf4;
+ info.spd[0][0][0x7d] = 0x7d;
+ info.spd[0][0][0x7e] = 0xb0;
+ info.spd[0][0][0x7f] = 0xcf;
+ info.spd[0][0][0x80] = 0x48;
+ info.spd[0][0][0x81] = 0x4d;
+ info.spd[0][0][0x82] = 0x54;
+ info.spd[0][0][0x83] = 0x33;
+ info.spd[0][0][0x84] = 0x35;
+ info.spd[0][0][0x85] = 0x31;
+ info.spd[0][0][0x86] = 0x53;
+ info.spd[0][0][0x87] = 0x36;
+ info.spd[0][0][0x88] = 0x42;
+ info.spd[0][0][0x89] = 0x46;
+ info.spd[0][0][0x8a] = 0x52;
+ info.spd[0][0][0x8b] = 0x38;
+ info.spd[0][0][0x8c] = 0x43;
+ info.spd[0][0][0x8d] = 0x2d;
+ info.spd[0][0][0x8e] = 0x48;
+ info.spd[0][0][0x8f] = 0x39;
+ info.spd[0][0][0x90] = 0x20;
+ info.spd[0][0][0x91] = 0x20;
+ info.spd[0][0][0x92] = 0x4e;
+ info.spd[0][0][0x93] = 0x30;
+ info.spd[0][0][0x94] = 0x80;
+ info.spd[0][0][0x95] = 0xad;
+
+ info.spd[1][0][0x02] = 0x0b;
+ info.spd[1][0][0x03] = 0x03;
+ info.spd[1][0][0x04] = 0x03;
+ info.spd[1][0][0x07] = 0x09;
+ info.spd[1][0][0x08] = 0x03;
+ info.spd[1][0][0x0a] = 0x01;
+ info.spd[1][0][0x0b] = 0x08;
+ info.spd[1][0][0x0c] = 0x0c;
+ info.spd[1][0][0x0e] = 0x3e;
+ info.spd[1][0][0x0f] = 0x00;
+ info.spd[1][0][0x10] = 0x69;
+ info.spd[1][0][0x11] = 0x78;
+ info.spd[1][0][0x12] = 0x69;
+ info.spd[1][0][0x13] = 0x30;
+ info.spd[1][0][0x14] = 0x69;
+ info.spd[1][0][0x15] = 0x11;
+ info.spd[1][0][0x16] = 0x20;
+ info.spd[1][0][0x17] = 0x89;
+ info.spd[1][0][0x18] = 0x00;
+ info.spd[1][0][0x19] = 0x05;
+ info.spd[1][0][0x1a] = 0x3c;
+ info.spd[1][0][0x1b] = 0x3c;
+ info.spd[1][0][0x1c] = 0x00;
+ info.spd[1][0][0x1d] = 0xf0;
+ info.spd[1][0][0x1f] = 0x05;
+ info.spd[1][0][0x20] = 0x00;
+ info.spd[1][0][0x3e] = 0x05;
+ info.spd[1][0][0x3f] = 0x00;
+ info.spd[1][0][0x75] = 0x80;
+ info.spd[1][0][0x76] = 0xad;
+ info.spd[1][0][0x77] = 0x01;
+ info.spd[1][0][0x78] = 0x10;
+ info.spd[1][0][0x79] = 0x52;
+ info.spd[1][0][0x7a] = 0x26;
+ info.spd[1][0][0x7b] = 0x50;
+ info.spd[1][0][0x7c] = 0xf4;
+ info.spd[1][0][0x7d] = 0x7d;
+ info.spd[1][0][0x7e] = 0xb0;
+ info.spd[1][0][0x7f] = 0xcf;
+ info.spd[1][0][0x80] = 0x48;
+ info.spd[1][0][0x81] = 0x4d;
+ info.spd[1][0][0x82] = 0x54;
+ info.spd[1][0][0x83] = 0x33;
+ info.spd[1][0][0x84] = 0x35;
+ info.spd[1][0][0x85] = 0x31;
+ info.spd[1][0][0x86] = 0x53;
+ info.spd[1][0][0x87] = 0x36;
+ info.spd[1][0][0x88] = 0x42;
+ info.spd[1][0][0x89] = 0x46;
+ info.spd[1][0][0x8a] = 0x52;
+ info.spd[1][0][0x8b] = 0x38;
+ info.spd[1][0][0x8c] = 0x43;
+ info.spd[1][0][0x8d] = 0x2d;
+ info.spd[1][0][0x8e] = 0x48;
+ info.spd[1][0][0x8f] = 0x39;
+ info.spd[1][0][0x90] = 0x20;
+ info.spd[1][0][0x91] = 0x20;
+ info.spd[1][0][0x92] = 0x4e;
+ info.spd[1][0][0x93] = 0x30;
+ info.spd[1][0][0x94] = 0x80;
+ info.spd[1][0][0x95] = 0xad;
+
+#endif
+ info.is_x16_module[0][0] =
+ (info.spd[0][0][RANKS_AND_DQ] & 7) - 1;
+ info.density[0][0] = info.spd[0][0][DENSITY] & 0xF;
+
+ info.is_x16_module[1][0] =
+ (info.spd[1][0][RANKS_AND_DQ] & 7) - 1;
+ info.density[1][0] = info.spd[1][0][DENSITY] & 0xF;
+ }
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_spd = rdtsc();
+#endif
+
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc);
+#if !REAL
+ my_read_msr (MTRRphysMask_MSR (3));
+#endif
+
+ collect_system_info(&info);
+ calculate_timings(&info);
+
+#if !REAL
+ pci_mm_write8(NORTHBRIDGE, 0xdf, 0x82);
+#endif
+
+ if (!s3resume) {
+ u8 reg8 = pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2);
+ if (x2ca8 == 0 && (reg8 & 0x80)) {
+ /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9.
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08);
+ */
+
+ /* Clear bit7. */
+ pci_write8(SOUTHBRIDGE, GEN_PMCON_2,
+ (reg8 & ~(1 << 7)));
+
+ printk(BIOS_INFO,
+ "Interrupted RAM init, reset required.\n");
+ outb(0x6, 0xcf9);
+#if REAL
+ while (1) {
+ asm volatile ("hlt");
+ }
+#endif
+ }
+ }
+#if !REAL
+ gav(read_mchbar8(0x2ca8)); ///!!!!
+#endif
+
+ if (!s3resume && x2ca8 == 0)
+ pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_2,
+ pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80);
+
+ compute_derived_timings(&info);
+
+ if (x2ca8 == 0) {
+ gav(read_mchbar8(0x164));
+ write_mchbar8(0x164, 0x26);
+ write_mchbar16(0x2c20, 0x10);
+ }
+
+ write_mchbar32(0x18b4, read_mchbar32(0x18b4) | 0x210000); /* OK */
+ write_mchbar32(0x1890, read_mchbar32(0x1890) | 0x2000000); /* OK */
+ write_mchbar32(0x18b4, read_mchbar32(0x18b4) | 0x8000);
+
+ gav(pci_mm_read32(0xff, 2, 1, 0x50)); // !!!!
+ pci_mm_write8(0xff, 2, 1, 0x54, 0x12);
+
+ gav(read_mchbar16(0x2c10)); // !!!!
+ write_mchbar16(0x2c10, 0x412);
+ gav(read_mchbar16(0x2c10)); // !!!!
+ write_mchbar16(0x2c12, read_mchbar16(0x2c12) | 0x100); /* OK */
+
+ gav(read_mchbar8(0x2ca8)); // !!!!
+ write_mchbar32(0x1804,
+ (read_mchbar32(0x1804) & 0xfffffffc) | 0x8400080);
+
+ pci_mm_read32(0xff, 2, 1, 0x6c); // !!!!
+ pci_mm_write32(0xff, 2, 1, 0x6c, 0x40a0a0);
+ gav(read_mchbar32(0x1c04)); // !!!!
+ gav(read_mchbar32(0x1804)); // !!!!
+
+ if (x2ca8 == 0) {
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1);
+ }
+
+ write_mchbar32(0x18d8, 0x120000);
+ write_mchbar32(0x18dc, 0x30a484a);
+ pci_mm_write32(0xff, 2, 1, 0xe0, 0x0);
+ pci_mm_write32(0xff, 2, 1, 0xf4, 0x9444a);
+ write_mchbar32(0x18d8, 0x40000);
+ write_mchbar32(0x18dc, 0xb000000);
+ pci_mm_write32(0xff, 2, 1, 0xe0, 0x60000);
+ pci_mm_write32(0xff, 2, 1, 0xf4, 0x0);
+ write_mchbar32(0x18d8, 0x180000);
+ write_mchbar32(0x18dc, 0xc0000142);
+ pci_mm_write32(0xff, 2, 1, 0xe0, 0x20000);
+ pci_mm_write32(0xff, 2, 1, 0xf4, 0x142);
+ write_mchbar32(0x18d8, 0x1e0000);
+
+ gav(read_mchbar32(0x18dc)); // !!!!
+ write_mchbar32(0x18dc, 0x3);
+ gav(read_mchbar32(0x18dc)); // !!!!
+
+ if (x2ca8 == 0) {
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess
+ }
+
+ write_mchbar32(0x188c, 0x20bc09);
+ pci_mm_write32(0xff, 2, 1, 0xd0, 0x40b0c09);
+ write_mchbar32(0x1a10, 0x4200010e);
+ write_mchbar32(0x18b8, read_mchbar32(0x18b8) | 0x200);
+ gav(read_mchbar32(0x1918)); // !!!!
+ write_mchbar32(0x1918, 0x332);
+
+ gav(read_mchbar32(0x18b8)); // !!!!
+ write_mchbar32(0x18b8, 0xe00);
+ gav(read_mchbar32(0x182c)); // !!!!
+ write_mchbar32(0x182c, 0x10202);
+ gav(pci_mm_read32(0xff, 2, 1, 0x94)); // !!!!
+ pci_mm_write32(0xff, 2, 1, 0x94, 0x10202);
+ write_mchbar32(0x1a1c, read_mchbar32(0x1a1c) & 0x8fffffff);
+ write_mchbar32(0x1a70, read_mchbar32(0x1a70) | 0x100000);
+
+ write_mchbar32(0x18b4, read_mchbar32(0x18b4) & 0xffff7fff);
+ gav(read_mchbar32(0x1a68)); // !!!!
+ write_mchbar32(0x1a68, 0x343800);
+ gav(read_mchbar32(0x1e68)); // !!!!
+ gav(read_mchbar32(0x1a68)); // !!!!
+
+ if (x2ca8 == 0) {
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess
+ }
+
+ pci_mm_read32(0xff, 2, 0, 0x048); // !!!!
+ pci_mm_write32(0xff, 2, 0, 0x048, 0x140000);
+ pci_mm_read32(0xff, 2, 0, 0x058); // !!!!
+ pci_mm_write32(0xff, 2, 0, 0x058, 0x64555);
+ pci_mm_read32(0xff, 2, 0, 0x058); // !!!!
+ pci_mm_read32(0xff, 0, 0, 0xd0); // !!!!
+ pci_mm_write32(0xff, 0, 0, 0xd0, 0x180);
+ gav(read_mchbar32(0x1af0)); // !!!!
+ gav(read_mchbar32(0x1af0)); // !!!!
+ write_mchbar32(0x1af0, 0x1f020003);
+ gav(read_mchbar32(0x1af0)); // !!!!
+
+ if (((x2ca8 == 0))) {
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess
+ }
+
+ gav(read_mchbar32(0x1890)); // !!!!
+ write_mchbar32(0x1890, 0x80102);
+ gav(read_mchbar32(0x18b4)); // !!!!
+ write_mchbar32(0x18b4, 0x216000);
+ write_mchbar32(0x18a4, 0x22222222);
+ write_mchbar32(0x18a8, 0x22222222);
+ write_mchbar32(0x18ac, 0x22222);
+
+ udelay(1000);
+
+ if (x2ca8 == 0) {
+ if (s3resume) {
+#if REAL && 0
+ info.reg2ca9_bit0 = 0;
+ info.reg274265[0][0] = 5;
+ info.reg274265[0][1] = 5;
+ info.reg274265[0][2] = 0xe;
+ info.reg274265[1][0] = 5;
+ info.reg274265[1][1] = 5;
+ info.reg274265[1][2] = 0xe;
+ info.delay46_ps[0] = 0xa86;
+ info.delay46_ps[1] = 0xa86;
+ info.delay54_ps[0] = 0xdc6;
+ info.delay54_ps[1] = 0xdc6;
+#else
+ info.reg2ca9_bit0 = 0;
+ info.reg274265[0][0] = 3;
+ info.reg274265[0][1] = 5;
+ info.reg274265[0][2] = 0xd;
+ info.reg274265[1][0] = 4;
+ info.reg274265[1][1] = 5;
+ info.reg274265[1][2] = 0xd;
+ info.delay46_ps[0] = 0x110a;
+ info.delay46_ps[1] = 0xb58;
+ info.delay54_ps[0] = 0x144a;
+ info.delay54_ps[1] = 0xe98;
+#endif
+ restore_274265(&info);
+ } else
+ set_274265(&info);
+ int j;
+ printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0);
+ for (i = 0; i < 2; i++)
+ for (j = 0; j < 3; j++)
+ printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n",
+ i, j, info.reg274265[i][j]);
+ for (i = 0; i < 2; i++)
+ printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i,
+ info.delay46_ps[i]);
+ for (i = 0; i < 2; i++)
+ printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i,
+ info.delay54_ps[i]);
+
+ set_2dxx_series(&info);
+
+ if (!(deven & 8)) {
+ read_mchbar32(0x2cb0);
+ write_mchbar32(0x2cb0, 0x40);
+ }
+
+ udelay(1000);
+
+ if (deven & 8) {
+ write_mchbar32(0xff8, 0x1800 | read_mchbar32(0xff8));
+ read_mchbar32(0x2cb0);
+ write_mchbar32(0x2cb0, 0x00);
+ pci_mm_read8(0, 0x2, 0x0, 0x4c);
+ pci_mm_read8(0, 0x2, 0x0, 0x4c);
+ pci_mm_read8(0, 0x2, 0x0, 0x4e);
+
+ read_mchbar8(0x1150);
+ read_mchbar8(0x1151);
+ read_mchbar8(0x1022);
+ read_mchbar8(0x16d0);
+ write_mchbar32(0x1300, 0x60606060);
+ write_mchbar32(0x1304, 0x60606060);
+ write_mchbar32(0x1308, 0x78797a7b);
+ write_mchbar32(0x130c, 0x7c7d7e7f);
+ write_mchbar32(0x1310, 0x60606060);
+ write_mchbar32(0x1314, 0x60606060);
+ write_mchbar32(0x1318, 0x60606060);
+ write_mchbar32(0x131c, 0x60606060);
+ write_mchbar32(0x1320, 0x50515253);
+ write_mchbar32(0x1324, 0x54555657);
+ write_mchbar32(0x1328, 0x58595a5b);
+ write_mchbar32(0x132c, 0x5c5d5e5f);
+ write_mchbar32(0x1330, 0x40414243);
+ write_mchbar32(0x1334, 0x44454647);
+ write_mchbar32(0x1338, 0x48494a4b);
+ write_mchbar32(0x133c, 0x4c4d4e4f);
+ write_mchbar32(0x1340, 0x30313233);
+ write_mchbar32(0x1344, 0x34353637);
+ write_mchbar32(0x1348, 0x38393a3b);
+ write_mchbar32(0x134c, 0x3c3d3e3f);
+ write_mchbar32(0x1350, 0x20212223);
+ write_mchbar32(0x1354, 0x24252627);
+ write_mchbar32(0x1358, 0x28292a2b);
+ write_mchbar32(0x135c, 0x2c2d2e2f);
+ write_mchbar32(0x1360, 0x10111213);
+ write_mchbar32(0x1364, 0x14151617);
+ write_mchbar32(0x1368, 0x18191a1b);
+ write_mchbar32(0x136c, 0x1c1d1e1f);
+ write_mchbar32(0x1370, 0x10203);
+ write_mchbar32(0x1374, 0x4050607);
+ write_mchbar32(0x1378, 0x8090a0b);
+ write_mchbar32(0x137c, 0xc0d0e0f);
+ write_mchbar8(0x11cc, 0x4e);
+ write_mchbar32(0x1110, 0x73970404);
+ write_mchbar32(0x1114, 0x72960404);
+ write_mchbar32(0x1118, 0x6f950404);
+ write_mchbar32(0x111c, 0x6d940404);
+ write_mchbar32(0x1120, 0x6a930404);
+ write_mchbar32(0x1124, 0x68a41404);
+ write_mchbar32(0x1128, 0x66a21404);
+ write_mchbar32(0x112c, 0x63a01404);
+ write_mchbar32(0x1130, 0x609e1404);
+ write_mchbar32(0x1134, 0x5f9c1404);
+ write_mchbar32(0x1138, 0x5c961404);
+ write_mchbar32(0x113c, 0x58a02404);
+ write_mchbar32(0x1140, 0x54942404);
+ write_mchbar32(0x1190, 0x900080a);
+ write_mchbar16(0x11c0, 0xc40b);
+ write_mchbar16(0x11c2, 0x303);
+ write_mchbar16(0x11c4, 0x301);
+ read_mchbar32(0x1190);
+ write_mchbar32(0x1190, 0x8900080a);
+ write_mchbar32(0x11b8, 0x70c3000);
+ write_mchbar8(0x11ec, 0xa);
+ write_mchbar16(0x1100, 0x800);
+ read_mchbar32(0x11bc);
+ write_mchbar32(0x11bc, 0x1e84800);
+ write_mchbar16(0x11ca, 0xfa);
+ write_mchbar32(0x11e4, 0x4e20);
+ write_mchbar8(0x11bc, 0xf);
+ write_mchbar16(0x11da, 0x19);
+ write_mchbar16(0x11ba, 0x470c);
+ write_mchbar32(0x1680, 0xe6ffe4ff);
+ write_mchbar32(0x1684, 0xdeffdaff);
+ write_mchbar32(0x1688, 0xd4ffd0ff);
+ write_mchbar32(0x168c, 0xccffc6ff);
+ write_mchbar32(0x1690, 0xc0ffbeff);
+ write_mchbar32(0x1694, 0xb8ffb0ff);
+ write_mchbar32(0x1698, 0xa8ff0000);
+ write_mchbar32(0x169c, 0xc00);
+ write_mchbar32(0x1290, 0x5000000);
+ }
+
+ write_mchbar32(0x124c, 0x15040d00);
+ write_mchbar32(0x1250, 0x7f0000);
+ write_mchbar32(0x1254, 0x1e220004);
+ write_mchbar32(0x1258, 0x4000004);
+ write_mchbar32(0x1278, 0x0);
+ write_mchbar32(0x125c, 0x0);
+ write_mchbar32(0x1260, 0x0);
+ write_mchbar32(0x1264, 0x0);
+ write_mchbar32(0x1268, 0x0);
+ write_mchbar32(0x126c, 0x0);
+ write_mchbar32(0x1270, 0x0);
+ write_mchbar32(0x1274, 0x0);
+ }
+
+ if ((deven & 8) && x2ca8 == 0) {
+ write_mchbar16(0x1214, 0x320);
+ write_mchbar32(0x1600, 0x40000000);
+ read_mchbar32(0x11f4);
+ write_mchbar32(0x11f4, 0x10000000);
+ read_mchbar16(0x1230);
+ write_mchbar16(0x1230, 0x8000);
+ write_mchbar32(0x1400, 0x13040020);
+ write_mchbar32(0x1404, 0xe090120);
+ write_mchbar32(0x1408, 0x5120220);
+ write_mchbar32(0x140c, 0x5120330);
+ write_mchbar32(0x1410, 0xe090220);
+ write_mchbar32(0x1414, 0x1010001);
+ write_mchbar32(0x1418, 0x1110000);
+ write_mchbar32(0x141c, 0x9020020);
+ write_mchbar32(0x1420, 0xd090220);
+ write_mchbar32(0x1424, 0x2090220);
+ write_mchbar32(0x1428, 0x2090330);
+ write_mchbar32(0x142c, 0xd090220);
+ write_mchbar32(0x1430, 0x1010001);
+ write_mchbar32(0x1434, 0x1110000);
+ write_mchbar32(0x1438, 0x11040020);
+ write_mchbar32(0x143c, 0x4030220);
+ write_mchbar32(0x1440, 0x1060220);
+ write_mchbar32(0x1444, 0x1060330);
+ write_mchbar32(0x1448, 0x4030220);
+ write_mchbar32(0x144c, 0x1010001);
+ write_mchbar32(0x1450, 0x1110000);
+ write_mchbar32(0x1454, 0x4010020);
+ write_mchbar32(0x1458, 0xb090220);
+ write_mchbar32(0x145c, 0x1090220);
+ write_mchbar32(0x1460, 0x1090330);
+ write_mchbar32(0x1464, 0xb090220);
+ write_mchbar32(0x1468, 0x1010001);
+ write_mchbar32(0x146c, 0x1110000);
+ write_mchbar32(0x1470, 0xf040020);
+ write_mchbar32(0x1474, 0xa090220);
+ write_mchbar32(0x1478, 0x1120220);
+ write_mchbar32(0x147c, 0x1120330);
+ write_mchbar32(0x1480, 0xa090220);
+ write_mchbar32(0x1484, 0x1010001);
+ write_mchbar32(0x1488, 0x1110000);
+ write_mchbar32(0x148c, 0x7020020);
+ write_mchbar32(0x1490, 0x1010220);
+ write_mchbar32(0x1494, 0x10210);
+ write_mchbar32(0x1498, 0x10320);
+ write_mchbar32(0x149c, 0x1010220);
+ write_mchbar32(0x14a0, 0x1010001);
+ write_mchbar32(0x14a4, 0x1110000);
+ write_mchbar32(0x14a8, 0xd040020);
+ write_mchbar32(0x14ac, 0x8090220);
+ write_mchbar32(0x14b0, 0x1111310);
+ write_mchbar32(0x14b4, 0x1111420);
+ write_mchbar32(0x14b8, 0x8090220);
+ write_mchbar32(0x14bc, 0x1010001);
+ write_mchbar32(0x14c0, 0x1110000);
+ write_mchbar32(0x14c4, 0x3010020);
+ write_mchbar32(0x14c8, 0x7090220);
+ write_mchbar32(0x14cc, 0x1081310);
+ write_mchbar32(0x14d0, 0x1081420);
+ write_mchbar32(0x14d4, 0x7090220);
+ write_mchbar32(0x14d8, 0x1010001);
+ write_mchbar32(0x14dc, 0x1110000);
+ write_mchbar32(0x14e0, 0xb040020);
+ write_mchbar32(0x14e4, 0x2030220);
+ write_mchbar32(0x14e8, 0x1051310);
+ write_mchbar32(0x14ec, 0x1051420);
+ write_mchbar32(0x14f0, 0x2030220);
+ write_mchbar32(0x14f4, 0x1010001);
+ write_mchbar32(0x14f8, 0x1110000);
+ write_mchbar32(0x14fc, 0x5020020);
+ write_mchbar32(0x1500, 0x5090220);
+ write_mchbar32(0x1504, 0x2071310);
+ write_mchbar32(0x1508, 0x2071420);
+ write_mchbar32(0x150c, 0x5090220);
+ write_mchbar32(0x1510, 0x1010001);
+ write_mchbar32(0x1514, 0x1110000);
+ write_mchbar32(0x1518, 0x7040120);
+ write_mchbar32(0x151c, 0x2090220);
+ write_mchbar32(0x1520, 0x70b1210);
+ write_mchbar32(0x1524, 0x70b1310);
+ write_mchbar32(0x1528, 0x2090220);
+ write_mchbar32(0x152c, 0x1010001);
+ write_mchbar32(0x1530, 0x1110000);
+ write_mchbar32(0x1534, 0x1010110);
+ write_mchbar32(0x1538, 0x1081310);
+ write_mchbar32(0x153c, 0x5041200);
+ write_mchbar32(0x1540, 0x5041310);
+ write_mchbar32(0x1544, 0x1081310);
+ write_mchbar32(0x1548, 0x1010001);
+ write_mchbar32(0x154c, 0x1110000);
+ write_mchbar32(0x1550, 0x1040120);
+ write_mchbar32(0x1554, 0x4051210);
+ write_mchbar32(0x1558, 0xd051200);
+ write_mchbar32(0x155c, 0xd051200);
+ write_mchbar32(0x1560, 0x4051210);
+ write_mchbar32(0x1564, 0x1010001);
+ write_mchbar32(0x1568, 0x1110000);
+ write_mchbar16(0x1222, 0x220a);
+ write_mchbar16(0x123c, 0x1fc0);
+ write_mchbar16(0x1220, 0x1388);
+ }
+
+ read_mchbar32(0x2c80); // !!!!
+ write_mchbar32(0x2c80, 0x1053688);
+ read_mchbar32(0x1c04); // !!!!
+ write_mchbar32(0x1804, 0x406080);
+
+ read_mchbar8(0x2ca8);
+
+ if (x2ca8 == 0) {
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & ~3);
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4);
+ write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10);
+#if REAL
+ while (1) {
+ asm volatile ("hlt");
+ }
+#else
+ printf("CP5\n");
+ exit(0);
+#endif
+ }
+
+ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8));
+ read_mchbar32(0x2c80); // !!!!
+ write_mchbar32(0x2c80, 0x53688);
+ pci_mm_write32(0xff, 0, 0, 0x60, 0x20220);
+ read_mchbar16(0x2c20); // !!!!
+ read_mchbar16(0x2c10); // !!!!
+ read_mchbar16(0x2c00); // !!!!
+ write_mchbar16(0x2c00, 0x8c0);
+ udelay(1000);
+ write_1d0(0, 0x33d, 0, 0);
+ write_500(&info, 0, 0, 0xb61, 0, 0);
+ write_500(&info, 1, 0, 0xb61, 0, 0);
+ write_mchbar32(0x1a30, 0x0);
+ write_mchbar32(0x1a34, 0x0);
+ write_mchbar16(0x614,
+ 0xb5b | (info.populated_ranks[1][0][0] *
+ 0x404) | (info.populated_ranks[0][0][0] *
+ 0xa0));
+ write_mchbar16(0x616, 0x26a);
+ write_mchbar32(0x134, 0x856000);
+ write_mchbar32(0x160, 0x5ffffff);
+ read_mchbar32(0x114); // !!!!
+ write_mchbar32(0x114, 0xc2024440);
+ read_mchbar32(0x118); // !!!!
+ write_mchbar32(0x118, 0x4);
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ write_mchbar32(0x260 + (channel << 10),
+ 0x30809ff |
+ ((info.
+ populated_ranks_mask[channel] & 3) << 20));
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar16(0x31c + (channel << 10), 0x101);
+ write_mchbar16(0x360 + (channel << 10), 0x909);
+ write_mchbar16(0x3a4 + (channel << 10), 0x101);
+ write_mchbar16(0x3e8 + (channel << 10), 0x101);
+ write_mchbar32(0x320 + (channel << 10), 0x29002900);
+ write_mchbar32(0x324 + (channel << 10), 0x0);
+ write_mchbar32(0x368 + (channel << 10), 0x32003200);
+ write_mchbar16(0x352 + (channel << 10), 0x505);
+ write_mchbar16(0x354 + (channel << 10), 0x3c3c);
+ write_mchbar16(0x356 + (channel << 10), 0x1040);
+ write_mchbar16(0x39a + (channel << 10), 0x73e4);
+ write_mchbar16(0x3de + (channel << 10), 0x77ed);
+ write_mchbar16(0x422 + (channel << 10), 0x1040);
+ }
+
+ write_1d0(0x4, 0x151, 4, 1);
+ write_1d0(0, 0x142, 3, 1);
+ my_read_msr(0x1ac); // !!!!
+ write_500(&info, 1, 1, 0x6b3, 4, 1);
+ write_500(&info, 1, 1, 0x6cf, 4, 1);
+
+ rmw_1d0(0x21c, 0x38, 0, 6, 1);
+
+ write_1d0(((!info.populated_ranks[1][0][0]) << 1) | ((!info.
+ populated_ranks[0]
+ [0][0]) << 0),
+ 0x1d1, 3, 1);
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar16(0x38e + (channel << 10), 0x5f5f);
+ write_mchbar16(0x3d2 + (channel << 10), 0x5f5f);
+ }
+
+ set_334(0);
+
+ program_base_timings(&info);
+
+ write_mchbar8(0x5ff, read_mchbar8(0x5ff) | 0x80); /* OK */
+
+ write_1d0(0x2, 0x1d5, 2, 1);
+ write_1d0(0x20, 0x166, 7, 1);
+ write_1d0(0x0, 0xeb, 3, 1);
+ write_1d0(0x0, 0xf3, 6, 1);
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (lane = 0; lane < 9; lane++) {
+ u16 addr = 0x125 + get_lane_offset(0, 0, lane);
+ u8 a;
+ a = read_500(&info, channel, addr, 6); // = 0x20040080 //!!!!
+ write_500(&info, channel, a, addr, 6, 1);
+ }
+
+ udelay(1000);
+
+ info.cached_training = get_cached_training();
+
+ if (s3resume) {
+ if (info.cached_training == NULL) {
+ u32 reg32;
+ printk(BIOS_ERR,
+ "Couldn't find training data. Rebooting\n");
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ outb(0xe, 0xcf9);
+
+#if REAL
+ while (1) {
+ asm volatile ("hlt");
+ }
+#else
+ printf("CP5\n");
+ exit(0);
+#endif
+ }
+ int tm;
+ info.training = *info.cached_training;
+ for (tm = 0; tm < 4; tm++)
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ for (lane = 0; lane < 9; lane++)
+ write_500(&info,
+ channel,
+ info.training.
+ lane_timings
+ [tm][channel]
+ [slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, tm,
+ slot, rank),
+ 9, 0);
+ write_1d0(info.cached_training->reg_178, 0x178, 7, 1);
+ write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1);
+ }
+
+ read_mchbar32(0x1f4); // !!!!
+ write_mchbar32(0x1f4, 0x20000);
+ write_mchbar32(0x1f0, 0x1d000200);
+ read_mchbar8(0x1f0); // !!!!
+ write_mchbar8(0x1f0, 0x1);
+ read_mchbar8(0x1f0); // !!!!
+
+ program_board_delay(&info);
+
+ write_mchbar8(0x5ff, 0x0); /* OK */
+ write_mchbar8(0x5ff, 0x80); /* OK */
+ write_mchbar8(0x5f4, 0x1); /* OK */
+
+ write_mchbar32(0x130, read_mchbar32(0x130) & 0xfffffffd); // | 2 when ?
+ while (read_mchbar32(0x130) & 1) ;
+ gav(read_1d0(0x14b, 7)); // = 0x81023100
+ write_1d0(0x30, 0x14b, 7, 1);
+ read_1d0(0xd6, 6); // = 0xfa008080 // !!!!
+ write_1d0(7, 0xd6, 6, 1);
+ read_1d0(0x328, 6); // = 0xfa018080 // !!!!
+ write_1d0(7, 0x328, 6, 1);
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ set_4cf(&info, channel,
+ info.populated_ranks[channel][0][0] ? 8 : 0);
+
+ read_1d0(0x116, 4); // = 0x4040432 // !!!!
+ write_1d0(2, 0x116, 4, 1);
+ read_1d0(0xae, 6); // = 0xe8088080 // !!!!
+ write_1d0(0, 0xae, 6, 1);
+ read_1d0(0x300, 4); // = 0x48088080 // !!!!
+ write_1d0(0, 0x300, 6, 1);
+ read_mchbar16(0x356); // !!!!
+ write_mchbar16(0x356, 0x1040);
+ read_mchbar16(0x756); // !!!!
+ write_mchbar16(0x756, 0x1040);
+ write_mchbar32(0x140, read_mchbar32(0x140) & ~0x07000000);
+ write_mchbar32(0x138, read_mchbar32(0x138) & ~0x07000000);
+ write_mchbar32(0x130, 0x31111301);
+ while (read_mchbar32(0x130) & 1) ;
+
+ {
+ u32 t;
+ u8 val_a1;
+ val_a1 = read_1d0(0xa1, 6); // = 0x1cf4040 // !!!!
+ t = read_1d0(0x2f3, 6); // = 0x10a4040 // !!!!
+ rmw_1d0(0x320, 0x07,
+ (t & 4) | ((t & 8) >> 2) | ((t & 0x10) >> 4), 6, 1);
+ rmw_1d0(0x14b, 0x78,
+ ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 &
+ 4), 7,
+ 1);
+ rmw_1d0(0xce, 0x38,
+ ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 &
+ 4), 6,
+ 1);
+ }
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ set_4cf(&info, channel,
+ info.populated_ranks[channel][0][0] ? 9 : 1);
+
+ rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!!
+ read_mchbar32(0x144); // !!!!
+ write_1d0(2, 0xae, 6, 1);
+ write_1d0(2, 0x300, 6, 1);
+ write_1d0(2, 0x121, 3, 1);
+ read_1d0(0xd6, 6); // = 0xfa00c0c7 // !!!!
+ write_1d0(4, 0xd6, 6, 1);
+ read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!!
+ write_1d0(4, 0x328, 6, 1);
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ set_4cf(&info, channel,
+ info.populated_ranks[channel][0][0] ? 9 : 0);
+
+ write_mchbar32(0x130,
+ 0x11111301 | (info.
+ populated_ranks[1][0][0] << 30) | (info.
+ populated_ranks
+ [0][0]
+ [0] <<
+ 29));
+ while (read_mchbar8(0x130) & 1) ; // !!!!
+ read_1d0(0xa1, 6); // = 0x1cf4054 // !!!!
+ read_1d0(0x2f3, 6); // = 0x10a4054 // !!!!
+ read_1d0(0x21c, 6); // = 0xafa00c0 // !!!!
+ write_1d0(0, 0x21c, 6, 1);
+ read_1d0(0x14b, 7); // = 0x810231b0 // !!!!
+ write_1d0(0x35, 0x14b, 7, 1);
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ set_4cf(&info, channel,
+ info.populated_ranks[channel][0][0] ? 0xb : 0x2);
+
+ set_334(1);
+
+ write_mchbar8(0x1e8, 0x4); /* OK */
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_500(&info, channel,
+ 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2,
+ 1);
+ write_500(&info, channel, 0x3, 0x69b, 2, 1);
+ }
+ write_mchbar32(0x2d0, (read_mchbar32(0x2d0) & 0xff2c01ff) | 0x200000); /* OK */
+ write_mchbar16(0x6c0, 0x14a0); /* OK */
+ write_mchbar32(0x6d0, (read_mchbar32(0x6d0) & 0xff0080ff) | 0x8000); /* OK */
+ write_mchbar16(0x232, 0x8);
+ write_mchbar32(0x234, (read_mchbar32(0x234) & 0xfffbfffb) | 0x40004); /* 0x40004 or 0 depending on ? */
+ write_mchbar32(0x34, (read_mchbar32(0x34) & 0xfffffffd) | 5); /* OK */
+ write_mchbar32(0x128, 0x2150d05);
+ write_mchbar8(0x12c, 0x1f); /* OK */
+ write_mchbar8(0x12d, 0x56); /* OK */
+ write_mchbar8(0x12e, 0x31);
+ write_mchbar8(0x12f, 0x0); /* OK */
+ write_mchbar8(0x271, 0x2); /* OK */
+ write_mchbar8(0x671, 0x2); /* OK */
+ write_mchbar8(0x1e8, 0x4); /* OK */
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ write_mchbar32(0x294 + (channel << 10),
+ (info.populated_ranks_mask[channel] & 3) << 16);
+ write_mchbar32(0x134, (read_mchbar32(0x134) & 0xfc01ffff) | 0x10000); /* OK */
+ write_mchbar32(0x134, (read_mchbar32(0x134) & 0xfc85ffff) | 0x850000); /* OK */
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ write_mchbar32(0x260 + (channel << 10),
+ (read_mchbar32(0x260 + (channel << 10)) &
+ ~0xf00000) | 0x8000000 | ((info.
+ populated_ranks_mask
+ [channel] & 3) <<
+ 20));
+
+ if (!s3resume)
+ jedec_init(&info);
+
+ int totalrank = 0;
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ if (info.populated_ranks[channel][slot][rank]) {
+ jedec_read(&info, channel, slot, rank,
+ totalrank, 0xa, 0x400);
+ totalrank++;
+ }
+
+ write_mchbar8(0x12c, 0x9f);
+
+ read_mchbar8(0x271); // 2 // !!!!
+ write_mchbar8(0x271, 0xe);
+ read_mchbar8(0x671); // !!!!
+ write_mchbar8(0x671, 0xe);
+
+ if (!s3resume) {
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar32(0x294 + (channel << 10),
+ (info.
+ populated_ranks_mask[channel] & 3) <<
+ 16);
+ write_mchbar16(0x298 + (channel << 10),
+ (info.
+ populated_ranks[channel][0][0]) | (info.
+ populated_ranks
+ [channel]
+ [0]
+ [1]
+ <<
+ 5));
+ write_mchbar32(0x29c + (channel << 10), 0x77a);
+ }
+ read_mchbar32(0x2c0); /// !!!
+ write_mchbar32(0x2c0, 0x6009cc00);
+
+ {
+ u8 a, b;
+ a = read_mchbar8(0x243); // !!!!
+ b = read_mchbar8(0x643); // !!!!
+ write_mchbar8(0x243, a | 2);
+ write_mchbar8(0x643, b | 2);
+ }
+
+ write_1d0(7, 0x19b, 3, 1);
+ write_1d0(7, 0x1c0, 3, 1);
+ write_1d0(4, 0x1c6, 4, 1);
+ write_1d0(4, 0x1cc, 4, 1);
+ read_1d0(0x151, 4); // = 0x408c6d74 // !!!!
+ write_1d0(4, 0x151, 4, 1);
+ write_mchbar32(0x584, 0xfffff);
+ write_mchbar32(0x984, 0xfffff);
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+ for (rank = 0; rank < NUM_RANKS; rank++)
+ if (info.
+ populated_ranks[channel][slot]
+ [rank])
+ config_rank(&info, s3resume,
+ channel, slot,
+ rank);
+
+ write_mchbar8(0x243, 0x1);
+ write_mchbar8(0x643, 0x1);
+ }
+
+ /* was == 1 but is common */
+ pci_mm_write16(NORTHBRIDGE, 0xc8, 3);
+ write_26c(0, 0x820);
+ write_26c(1, 0x820);
+ write_mchbar32(0x130, read_mchbar32(0x130) | 2);
+ /* end */
+
+ if (s3resume) {
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar32(0x294 + (channel << 10),
+ (info.
+ populated_ranks_mask[channel] & 3) <<
+ 16);
+ write_mchbar16(0x298 + (channel << 10),
+ (info.
+ populated_ranks[channel][0][0]) | (info.
+ populated_ranks
+ [channel]
+ [0]
+ [1]
+ <<
+ 5));
+ write_mchbar32(0x29c + (channel << 10), 0x77a);
+ }
+ read_mchbar32(0x2c0); /// !!!
+ write_mchbar32(0x2c0, 0x6009cc00);
+ }
+
+ write_mchbar32(0xfa4, read_mchbar32(0xfa4) & ~0x01000002);
+ write_mchbar32(0xfb0, 0x2000e019);
+
+#if !REAL
+ printf("CP16\n");
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_training = rdtsc();
+#endif
+
+ if (!s3resume)
+ ram_training(&info);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_training = rdtsc();
+#endif
+
+ dump_timings(&info);
+
+#if 0
+ ram_check(0x100000, 0x200000);
+#endif
+ program_modules_memory_map(&info, 0);
+ program_total_memory_map(&info);
+
+ if (info.non_interleaved_part_mb != 0 && info.interleaved_part_mb != 0)
+ write_mchbar8(0x111, 0x20 | (0 << 2) | (1 << 6) | (0 << 7));
+ else if (have_match_ranks(&info, 0, 4) && have_match_ranks(&info, 1, 4))
+ write_mchbar8(0x111, 0x20 | (3 << 2) | (0 << 6) | (1 << 7));
+ else if (have_match_ranks(&info, 0, 2) && have_match_ranks(&info, 1, 2))
+ write_mchbar8(0x111, 0x20 | (3 << 2) | (0 << 6) | (0 << 7));
+ else
+ write_mchbar8(0x111, 0x20 | (3 << 2) | (1 << 6) | (0 << 7));
+
+ write_mchbar32(0xfac, read_mchbar32(0xfac) & ~0x80000000); // OK
+ write_mchbar32(0xfb4, 0x4800); // OK
+ write_mchbar32(0xfb8, (info.revision < 8) ? 0x20 : 0x0); // OK
+ write_mchbar32(0xe94, 0x7ffff); // OK
+ write_mchbar32(0xfc0, 0x80002040); // OK
+ write_mchbar32(0xfc4, 0x701246); // OK
+ write_mchbar8(0xfc8, read_mchbar8(0xfc8) & ~0x70); // OK
+ write_mchbar32(0xe5c, 0x1000000 | read_mchbar32(0xe5c)); // OK
+ write_mchbar32(0x1a70, (read_mchbar32(0x1a70) | 0x00200000) & ~0x00100000); // OK
+ write_mchbar32(0x50, 0x700b0); // OK
+ write_mchbar32(0x3c, 0x10); // OK
+ write_mchbar8(0x1aa8, (read_mchbar8(0x1aa8) & ~0x35) | 0xa); // OK
+ write_mchbar8(0xff4, read_mchbar8(0xff4) | 0x2); // OK
+ write_mchbar32(0xff8, (read_mchbar32(0xff8) & ~0xe008) | 0x1020); // OK
+
+#if REAL
+ write_mchbar32(0xd00, IOMMU_BASE2 | 1);
+ write_mchbar32(0xd40, IOMMU_BASE1 | 1);
+ write_mchbar32(0xdc0, IOMMU_BASE4 | 1);
+
+ write32(IOMMU_BASE1 | 0xffc, 0x80000000);
+ write32(IOMMU_BASE2 | 0xffc, 0xc0000000);
+ write32(IOMMU_BASE4 | 0xffc, 0x80000000);
+
+#else
+ {
+ u32 eax;
+ eax = read32(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
+ write32(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK
+ eax = read32(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
+ write32(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK
+ }
+#endif
+
+ {
+ u32 eax;
+
+ eax = info.fsb_frequency / 9;
+ write_mchbar32(0xfcc, (read_mchbar32(0xfcc) & 0xfffc0000) | (eax * 0x280) | (eax * 0x5000) | eax | 0x40000); // OK
+ write_mchbar32(0x20, 0x33001); //OK
+ }
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar32(0x220 + (channel << 10), read_mchbar32(0x220 + (channel << 10)) & ~0x7770); //OK
+ if (info.max_slots_used_in_channel == 1)
+ write_mchbar16(0x237 + (channel << 10), (read_mchbar16(0x237 + (channel << 10)) | 0x0201)); //OK
+ else
+ write_mchbar16(0x237 + (channel << 10), (read_mchbar16(0x237 + (channel << 10)) & ~0x0201)); //OK
+
+ write_mchbar8(0x241 + (channel << 10), read_mchbar8(0x241 + (channel << 10)) | 1); // OK
+
+ if (info.clock_speed_index <= 1
+ && (info.silicon_revision == 2
+ || info.silicon_revision == 3))
+ write_mchbar32(0x248 + (channel << 10), (read_mchbar32(0x248 + (channel << 10)) | 0x00102000)); // OK
+ else
+ write_mchbar32(0x248 + (channel << 10), (read_mchbar32(0x248 + (channel << 10)) & ~0x00102000)); // OK
+ }
+
+ write_mchbar32(0x115, read_mchbar32(0x115) | 0x1000000); // OK
+
+ {
+ u8 al;
+ al = 0xd;
+ if (!(info.silicon_revision == 0 || info.silicon_revision == 1))
+ al += 2;
+ al |= ((1 << (info.max_slots_used_in_channel - 1)) - 1) << 4;
+ write_mchbar32(0x210, (al << 16) | 0x20); // OK
+ }
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ write_mchbar32(0x288 + (channel << 10), 0x70605040); // OK
+ write_mchbar32(0x28c + (channel << 10), 0xfffec080); // OK
+ write_mchbar32(0x290 + (channel << 10), 0x282091c | ((info.max_slots_used_in_channel - 1) << 0x16)); // OK
+ }
+ u32 reg1c;
+ pci_mm_read32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+ reg1c = read32(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
+ pci_mm_read32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+ write32(DEFAULT_EPBAR | 0x01c, reg1c); // OK
+ read_mchbar8(0xe08); // = 0x0
+ pci_mm_read32(NORTHBRIDGE, 0xe4); // = 0x316126
+ write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK
+ write_mchbar32(0x1200, 0x8800440); // OK
+ write_mchbar32(0x1204, 0x53ff0453); // OK
+ write_mchbar32(0x1208, 0x19002043); // OK
+ write_mchbar16(0x1214, 0x320); // OK
+
+ if (info.revision == 0x10 || info.revision == 0x11) {
+ write_mchbar16(0x1214, 0x220); // OK
+ write_mchbar8(0x1210, read_mchbar8(0x1210) | 0x40); // OK
+ }
+
+ write_mchbar8(0x1214, read_mchbar8(0x1214) | 0x4); // OK
+ write_mchbar8(0x120c, 0x1); // OK
+ write_mchbar8(0x1218, 0x3); // OK
+ write_mchbar8(0x121a, 0x3); // OK
+ write_mchbar8(0x121c, 0x3); // OK
+ write_mchbar16(0xc14, 0x0); // OK
+ write_mchbar16(0xc20, 0x0); // OK
+ write_mchbar32(0x1c, 0x0); // OK
+
+ /* revision dependent here. */
+
+ write_mchbar16(0x1230, read_mchbar16(0x1230) | 0x1f07); // OK
+
+ if (info.uma_enabled)
+ write_mchbar32(0x11f4, read_mchbar32(0x11f4) | 0x10000000); // OK
+
+ write_mchbar16(0x1230, read_mchbar16(0x1230) | 0x8000); // OK
+ write_mchbar8(0x1214, read_mchbar8(0x1214) | 1); // OK
+
+ u8 bl, ebpb;
+ u16 reg_1020;
+
+ reg_1020 = read_mchbar32(0x1020); // = 0x6c733c // OK
+ write_mchbar8(0x1070, 0x1); // OK
+
+ write_mchbar32(0x1000, 0x100); // OK
+ write_mchbar8(0x1007, 0x0); // OK
+
+ if (reg_1020 != 0) {
+ write_mchbar16(0x1018, 0x0); // OK
+ bl = reg_1020 >> 8;
+ ebpb = reg_1020 & 0xff;
+ } else {
+ ebpb = 0;
+ bl = 8;
+ }
+
+ my_read_msr(0x1a2);
+
+ write_mchbar32(0x1014, 0xffffffff); // OK
+
+ write_mchbar32(0x1010, ((((ebpb + 0x7d) << 7) / bl) & 0xff) * (! !reg_1020)); // OK
+
+ write_mchbar8(0x101c, 0xb8); // OK
+
+ write_mchbar8(0x123e, (read_mchbar8(0x123e) & 0xf) | 0x60); // OK
+ if (reg_1020 != 0) {
+ write_mchbar32(0x123c, (read_mchbar32(0x123c) & ~0x00900000) | 0x600000); // OK
+ write_mchbar8(0x101c, 0xb8); // OK
+ }
+
+ setup_heci_uma(&info);
+
+ if (info.uma_enabled) {
+ u16 ax;
+ write_mchbar32(0x11b0, read_mchbar32(0x11b0) | 0x4000); // OK
+ write_mchbar32(0x11b4, read_mchbar32(0x11b4) | 0x4000); // OK
+ write_mchbar16(0x1190, read_mchbar16(0x1190) | 0x4000); // OK
+
+ ax = read_mchbar16(0x1190) & 0xf00; // = 0x480a // OK
+ write_mchbar16(0x1170, ax | (read_mchbar16(0x1170) & 0x107f) | 0x4080); // OK
+ write_mchbar16(0x1170, read_mchbar16(0x1170) | 0x1000); // OK
+#if REAL
+ udelay(1000);
+#endif
+ u16 ecx;
+ for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--) ; // OK
+ write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK
+ }
+
+ pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_2,
+ pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80);
+ udelay(10000);
+ write_mchbar16(0x2ca8, 0x0);
+
+#if REAL
+ udelay(1000);
+ dump_timings(&info);
+ if (!s3resume)
+ save_timings(&info);
+#endif
+}
+
+#if REAL
+unsigned long get_top_of_ram(void)
+{
+ /* Base of TSEG is top of usable DRAM */
+ u32 tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
+ return (unsigned long)tom;
+}
+
+struct cbmem_entry *get_cbmem_toc(void)
+{
+ return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
+}
+#endif
+
+#if !REAL
+int main(void)
+{
+ raminit(0);
+ return 0;
+}
+#endif
diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h
new file mode 100644
index 0000000..f07e350
--- /dev/null
+++ b/src/northbridge/intel/nehalem/raminit.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#include "nehalem.h"
+
+void raminit(int s3resume);
+unsigned long get_top_of_ram(void);
+int fixup_nehalem_errata(void);
+
+#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/nehalem/raminit_fake.c b/src/northbridge/intel/nehalem/raminit_fake.c
new file mode 100644
index 0000000..df06040
--- /dev/null
+++ b/src/northbridge/intel/nehalem/raminit_fake.c
@@ -0,0 +1,2056 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static u32 gav_real(int line, u32 in)
+{
+ // printf ("%d: GAV: %x\n", line, in);
+ return in;
+}
+
+#define gav(x) gav_real (__LINE__, (x))
+
+#include <parse.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+static void pm_wait(u16 us);
+
+#define ARRAY_SIZE(array) (sizeof (array) / sizeof (array[0]))
+
+#define CONFIG_SMM_TSEG_SIZE (8 << 20)
+
+#define MTRR_TYPE_WRPROT 5
+#define MTRRdefTypeEn (1 << 11)
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+#define MTRRcap_MSR 0x0fe
+
+#include "include/cpu/intel/speedstep.h"
+#include "include/cpu/intel/turbo.h"
+
+#define PCI_VENDOR_ID 0x00 /* 16 bits */
+#define PCI_COMMAND 0x04 /* 16 bits */
+#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
+#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
+#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
+#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
+#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
+#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
+#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
+#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
+#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
+#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
+#define PCI_REVISION_ID 8
+#define PCI_DEVICE_ID 2
+
+#define CONFIG_MMCONF_BASE_ADDRESS 0xe0000000
+
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+
+static void write32(u32 addr, u32 val)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val
+ || op.type != MEM) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static void write16(u32 addr, u16 val)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val
+ || op.type != MEM) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static void write8(u32 addr, u8 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val
+ || op.type != MEM) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static int smbus_read_byte(u32 dev, u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != SMBUS || op.dev != dev) {
+ printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr, SMBUS,
+ addr, op.type);
+ exit(1);
+ }
+ return (signed short)op.val;
+}
+
+static int smbus_block_read(u32 dev, u32 addr, u32 len, u8 * block)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != len || op.addr != addr
+ || op.type != OPCODE_SMBUS_BLOCK || op.dev != dev) {
+ printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr,
+ OPCODE_SMBUS_BLOCK, addr, op.type);
+ exit(1);
+ }
+ memcpy(block, &op.val, len);
+ return 0;
+}
+
+static int smbus_block_write(u32 dev, u32 addr, u32 len, const u8 * block)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != len || op.addr != addr
+ || op.type != OPCODE_SMBUS_BLOCK || op.dev != dev
+ || memcmp(block, &op.val, len) != 0) {
+ printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr,
+ OPCODE_SMBUS_BLOCK, addr, op.type);
+ exit(1);
+ }
+ return 0;
+}
+
+static void smbus_write_byte(u32 dev, u32 addr, u8 val)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != SMBUS || op.dev != dev || op.val != val) {
+ printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, addr, SMBUS,
+ op.addr, op.type);
+ exit(1);
+ }
+}
+
+static void write_mchbar32(u32 addr, u32 val)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val
+ || op.type != OPCODE_MCHBAR) {
+ printf("Bad [%x] = %x vs [%x] = %llx\n", addr, val, op.addr,
+ op.val);
+ exit(1);
+ }
+}
+
+static void write_acpi32(u32 addr, u32 val)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val
+ || op.type != ACPI) {
+ printf("Bad [%x] = %x vs [%x] = %llx\n", addr, val, op.addr,
+ op.val);
+ exit(1);
+ }
+}
+
+static void write_mchbar16(u32 addr, u16 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val
+ || op.type != OPCODE_MCHBAR) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static void write_acpi16(u32 addr, u16 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val
+ || op.type != ACPI) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static void write_tco16(u32 addr, u16 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val
+ || op.type != TCO) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static void write_tco8(u32 addr, u8 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val
+ || op.type != TCO) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static void write_mchbar8(u32 addr, u8 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val
+ || op.type != OPCODE_MCHBAR) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static u32 read_mchbar32(u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != OPCODE_MCHBAR) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u32 read_mchbar32_bypass(u32 addr)
+{
+ return read_mchbar32(addr);
+}
+
+static u32 read_acpi32(u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != ACPI) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u16 read_mchbar16(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != OPCODE_MCHBAR) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u16 read_tco16(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != TCO) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u16 read_acpi16(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != ACPI) {
+ printf("Bad %d: %x, 16 vs %x, %d\n", __LINE__, addr, op.addr,
+ op.data_width);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u8 read_mchbar8(u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != OPCODE_MCHBAR) {
+ printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u8 read_tco8(u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != TCO) {
+ printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u32 read32(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != MEM) {
+ printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u64 read64(u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 64 || op.addr != addr
+ || op.type != MEM) {
+ printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+ exit(1);
+ }
+ return op.val;
+}
+
+static void clflush(u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+
+ if (op.addr != addr || op.type != CLFLUSH) {
+ printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+ exit(1);
+ }
+}
+
+static void read128(u32 addr, u64 * out)
+{
+ out[0] = read64(addr);
+ out[1] = read64(addr + 8);
+}
+
+static u16 read16(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != MEM) {
+ printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u8 read8(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != MEM) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u8 inb(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != PCIO) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static void outb(u8 val, u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCIO
+ || op.val != val) {
+ printf("Bad %d: %x, %x, 8, %d, 0 vs %x, %llx, %d, %d, %d\n",
+ __LINE__, addr, val, PCIO, op.addr, op.val,
+ op.data_width, op.type, op.is_in);
+ printf("%x, %llx, %d\n", val, op.val, op.val != val);
+ exit(1);
+ }
+}
+
+static void outw(u16 val, u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != PCIO || op.val != val) {
+ printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val,
+ op.addr, op.val);
+ exit(1);
+ }
+}
+
+static void outl(u32 val, u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != PCIO || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static u32 inl(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != PCIO) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u16 inw(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != PCIO) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static void pci_mm_write8(int bus, int dev, int func, u32 addr, u8 val)
+{
+ struct opcode op;
+ if (bus == 0xff) {
+ write8(DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) |
+ (func << 12) | addr, val);
+ return;
+ }
+
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != PCIMM || op.dev != dev || op.func != func
+ || op.bus != bus || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static void pci_write8(int bus, int dev, int func, u32 addr, u8 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCI
+ || op.dev != dev || op.func != func || op.bus != bus
+ || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static void pci_write16(int bus, int dev, int func, u32 addr, u16 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCI
+ || op.dev != dev || op.func != func || op.bus != bus
+ || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static void pci_mm_write16(int bus, int dev, int func, u32 addr, u16 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != PCIMM || op.dev != dev || op.func != func
+ || op.bus != bus || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static void pci_mm_write32(int bus, int dev, int func, u32 addr, u32 val)
+{
+ struct opcode op;
+ if (bus == 0xff) {
+ write32(DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) |
+ (func << 12) | addr, val);
+ return;
+ }
+
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+
+ if (op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != PCIMM || op.dev != dev || op.func != func
+ || op.bus != bus || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static void pci_write32(int bus, int dev, int func, u32 addr, u32 val)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCI
+ || op.dev != dev || op.func != func || op.bus != bus
+ || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static u8 pci_read8(int bus, int dev, int func, u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCI
+ || op.dev != dev || op.func != func || op.bus != bus) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u8 nvram_read(u8 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.addr != addr || op.type != NVRAM) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static void nvram_write(u8 addr, u8 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.addr != addr || op.type != NVRAM || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+}
+
+static u8 pci_mm_read8(int bus, int dev, int func, u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 8 || op.addr != addr
+ || op.type != PCIMM || op.dev != op.dev || op.func != op.func
+ || op.bus != op.bus) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u16 pci_mm_read16(int bus, int dev, int func, u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != PCIMM || op.dev != dev || op.func != func
+ || op.bus != bus) {
+ printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u16 pci_read16(int bus, int dev, int func, u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 16 || op.addr != addr
+ || op.type != PCI || op.dev != op.dev || op.func != op.func
+ || op.bus != op.bus) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u32 pci_mm_read32(int bus, int dev, int func, u32 addr)
+{
+ struct opcode op;
+
+ if (bus == 0xff)
+ return read32(DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) |
+ (func << 12) | addr);
+
+ fetch_opcode(&op);
+ if (!op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != PCIMM || op.dev != op.dev || op.func != op.func
+ || op.bus != op.bus) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u32 pci_read32(int bus, int dev, int func, u32 addr)
+{
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (!op.is_in || op.data_width != 32 || op.addr != addr
+ || op.type != PCI || op.dev != op.dev || op.func != op.func
+ || op.bus != op.bus) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+struct cpuid_result {
+ u32 eax, ebx;
+};
+
+struct cpuid_result cpuid_ext(u32 eax, u32 ecx)
+{
+ struct cpuid_result ret;
+ struct opcode op;
+ if (!fetch_opcode(&op)) {
+ printf("EOF\n");
+ exit(1);
+ }
+ if (op.addr != eax || op.type != CPUID || op.ecx != ecx) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ ret.eax = op.val;
+ ret.ebx = op.val >> 32;
+ return ret;
+}
+
+static u64 my_read_msr(u32 addr)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (!op.is_in || op.addr != addr || op.type != MSR) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static u64 my_write_msr(u32 addr, u64 val)
+{
+ struct opcode op;
+ fetch_opcode(&op);
+ if (op.is_in || op.addr != addr || op.type != MSR || op.val != val) {
+ printf("Bad %d\n", __LINE__);
+ exit(1);
+ }
+ return op.val;
+}
+
+static void die(const char *msg)
+{
+ printf("%s\n", msg);
+ exit(1);
+}
+
+static void intel_early_me_init(void)
+{
+}
+
+static unsigned intel_early_me_uma_size(void)
+{
+ u32 t;
+ t = pci_mm_read32(HECIDEV, 0x44);
+ if (t & 0x10000)
+ return t & 0x3F;
+ return 0;
+}
+
+static u8 read_mchbar8_bypass(u32 addr)
+{
+ return read_mchbar8(addr);
+}
+
+#define printk(condition, fmt, args...) printf(fmt, ## args)
+
+#define udelay(x)
+
+#if 1
+static const struct ram_training *get_cached_training(void)
+{
+ return NULL;
+#if 0
+ static const struct ram_training ret = {
+#if 1
+ .lane_timings = {
+ {
+ {
+ {
+ {5, 5, 3, 4, 4, 3, 4, 4, 21},
+ {5, 4, 2, 5, 4, 3, 4, 4, 21}
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ },
+ {
+ {
+ {
+ {0x6e, 0x64, 0x7b, 0x56, 0xbd, 0xa0, 0xae,
+ 0xad, 0x100},
+ {0x6e, 0x67, 0x7a, 0x54, 0xbd, 0x9f, 0xac,
+ 0xac, 0x100}
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ },
+ {
+ {
+ {
+ {0x59, 0x55, 0x6d, 0x44, 0xa3, 0x76, 0x90,
+ 0x81, 0x80},
+ {0x58, 0x51, 0x6b, 0x41, 0xa1, 0x75, 0x8e,
+ 0x7f, 0x80},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ },
+ {
+ {
+ {
+ {0x78, 0x74, 0x8b, 0x64, 0xc1, 0x94, 0xaf,
+ 0x9d, 0x80},
+ {0x76, 0x6e, 0x88, 0x60, 0xbe, 0x93, 0xae,
+ 0x9d, 0x80},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ }
+ },
+ .reg_178 = 0x42,
+ .reg_10b = 1,
+ .v775 = {19, 35},
+ .v777 = {
+ {
+ {
+ {
+ {0x01, 0x25},
+ {0x01, 0x25},
+ {0x01, 0x21},
+ {0x02, 0x22},
+ {0x00, 0x23},
+ {0x00, 0x21},
+ {0x01, 0x22},
+ {0x01, 0x22},
+ {0x00, 0x00}
+ },
+ {
+ {0x01, 0x24},
+ {0x02, 0x23},
+ {0x01, 0x20},
+ {0x01, 0x24},
+ {0x00, 0x22},
+ {0x01, 0x21},
+ {0x01, 0x21},
+ {0x02, 0x21},
+ {0x00, 0x00}
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ }
+ },
+ {
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ }
+ }
+ },
+ {
+ {
+ {
+ {0x00, 0x25},
+ {0x01, 0x24},
+ {0x01, 0x20},
+ {0x01, 0x22},
+ {0x00, 0x22},
+ {0x00, 0x21},
+ {0x01, 0x23},
+ {0x00, 0x22},
+ {0x00, 0x00}
+ },
+ {
+ {0x00, 0x26},
+ {0x01, 0x22},
+ {0x01, 0x20},
+ {0x01, 0x24},
+ {0x00, 0x23},
+ {0x00, 0x21},
+ {0x01, 0x22},
+ {0x01, 0x22},
+ {0x00, 0x00}
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ }
+ },
+ {
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ }
+ }
+ }
+ },
+ .v1065 = {
+ {
+ {0x9c, 0x92, 0xab, 0x85, 0xec, 0xd0, 0xdd, 0xdc,
+ 0x00},
+ {0x9c, 0x96, 0xab, 0x82, 0xec, 0xcf, 0xdb, 0xdb,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+ },
+ .v1209 = {
+ {
+ {0x59, 0x55, 0x6d, 0x44, 0xa3, 0x76, 0x90, 0x81,
+ 0x00},
+ {0x58, 0x51, 0x6b, 0x41, 0xa1, 0x75, 0x8e, 0x7f,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ }
+ },
+ .v1353 = {
+ {
+ {
+ {0x5d, 0x93},
+ {0x59, 0x90},
+ {0x70, 0xa6},
+ {0x49, 0x7f},
+ {0xa5, 0xdd},
+ {0x79, 0xb0},
+ {0x94, 0xca},
+ {0x83, 0xb8},
+ {0x00, 0x00},
+ },
+ {
+ {0x5c, 0x91},
+ {0x53, 0x89},
+ {0x6d, 0xa4},
+ {0x45, 0x7c},
+ {0xa3, 0xd9},
+ {0x77, 0xaf},
+ {0x94, 0xc9},
+ {0x82, 0xb8},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ }
+ },
+ {
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ },
+ {
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ }
+ }
+ },
+#else
+ .lane_timings = {
+ {
+ {
+ {
+ {5, 5, 3, 5, 4, 4, 5, 3, 21},
+ {6, 5, 4, 4, 4, 3, 4, 4, 21}
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {3, 4, 5, 3, 2, 4, 4, 4, 21},
+ {3, 3, 5, 4, 2, 5, 3, 4, 21},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ },
+ {
+ {
+ {
+ {0x6f, 0x66, 0x82, 0x58, 0xc5, 0xa6, 0xb4,
+ 0xb1, 0x100},
+ {0x70, 0x67, 0x84, 0x59, 0xc5, 0xa3, 0xb4,
+ 0xb2, 0x100}
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {0x91, 0x87, 0x98, 0x76, 0xdc, 0xb7, 0xcf,
+ 0xc5, 0x100},
+ {0x92, 0x8d, 0x9b, 0x76, 0xde, 0xb9, 0xce,
+ 0xc6, 0x100},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ },
+ {
+ {
+ {
+ {0x5f, 0x5b, 0x74, 0x4a, 0xa9, 0x7c, 0x95,
+ 0x85, 0x80},
+ {0x5d, 0x59, 0x72, 0x49, 0xa8, 0x7a, 0x96,
+ 0x85, 0x80},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {0x5b, 0x53, 0x6c, 0x49, 0xa8, 0x7a, 0x92,
+ 0x84, 0x80},
+ {0x5b, 0x51, 0x6c, 0x48, 0xa7, 0x79, 0x91,
+ 0x82, 0x80},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ },
+ {
+ {
+ {
+ {0x7e, 0x7a, 0x92, 0x6a, 0xc7, 0x9b, 0xb6,
+ 0xa4, 0x80},
+ {0x7d, 0x77, 0x8f, 0x69, 0xc6, 0x98, 0xb6,
+ 0xa4, 0x80},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ {
+ {
+ {0x78, 0x6f, 0x89, 0x65, 0xc4, 0x97, 0xaf,
+ 0x9f, 0x80},
+ {0x78, 0x6b, 0x89, 0x64, 0xc2, 0x96, 0xae,
+ 0x9d, 0x80},
+ },
+ {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+ }
+ },
+ }
+ },
+ .reg_178 = 0,
+ .reg_10b = 1,
+#endif
+ };
+ return &ret;
+#endif
+}
+#endif
+
+static void pre_raminit_3(int x2ca8)
+{
+ u8 t;
+ int i;
+
+ gav(t = nvram_read(0x33));
+ if (x2ca8 == 0) {
+ nvram_write(0x33, t & ~0x40);
+ gav(read32(DEFAULT_RCBA | 0x3598));
+ write32(DEFAULT_RCBA | 0x3598, 0x1);
+ pci_write16(0, 0x1d, 0x0, 0x20, 0x2000);
+ gav(pci_read8(0, 0x1d, 0x0, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x0, 0x4, 0xff);
+ pci_write16(0, 0x1d, 0x1, 0x20, 0x2020);
+ gav(pci_read8(0, 0x1d, 0x1, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x1, 0x4, 0xff);
+ pci_write16(0, 0x1d, 0x2, 0x20, 0x2040);
+ gav(pci_read8(0, 0x1d, 0x2, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x2, 0x4, 0xff);
+ pci_write16(0, 0x1d, 0x3, 0x20, 0x2060);
+ gav(pci_read8(0, 0x1d, 0x3, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x3, 0x4, 0xff);
+ pci_write16(0, 0x1a, 0x0, 0x20, 0x2080);
+ gav(pci_read8(0, 0x1a, 0x0, 0x4)); // = 0xff
+ pci_write8(0, 0x1a, 0x0, 0x4, 0xff);
+ pci_write16(0, 0x1a, 0x1, 0x20, 0x20a0);
+ gav(pci_read8(0, 0x1a, 0x1, 0x4)); // = 0xff
+ pci_write8(0, 0x1a, 0x1, 0x4, 0xff);
+ pci_write16(0, 0x1a, 0x2, 0x20, 0x20e0);
+ gav(pci_read8(0, 0x1a, 0x2, 0x4)); // = 0xff
+ pci_write8(0, 0x1a, 0x2, 0x4, 0xff);
+ for (i = 0; i < 15; i++) {
+ gav(inw(0x2010)); // = 0xff
+ gav(inw(0x2012)); // = 0xff
+ gav(inw(0x2030)); // = 0xff
+ gav(inw(0x2032)); // = 0xff
+ gav(inw(0x2050)); // = 0xff
+ gav(inw(0x2052)); // = 0xff
+ gav(inw(0x2070)); // = 0xff
+ gav(inw(0x2072)); // = 0xff
+ gav(inw(0x2090)); // = 0xff
+ gav(inw(0x2092)); // = 0xff
+ gav(inw(0x20b0)); // = 0xff
+ gav(inw(0x20b2)); // = 0xff
+ gav(inw(0x20f0)); // = 0xff
+ gav(inw(0x20f2)); // = 0xff
+ if (i != 14)
+ pm_wait(0x400); /* <10 */
+ }
+ pci_write16(0, 0x1d, 0x0, 0x20, 0x0);
+ gav(pci_read8(0, 0x1d, 0x0, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x0, 0x4, 0xfe);
+ pci_write16(0, 0x1d, 0x1, 0x20, 0x0);
+ gav(pci_read8(0, 0x1d, 0x1, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x1, 0x4, 0xfe);
+ pci_write16(0, 0x1d, 0x2, 0x20, 0x0);
+ gav(pci_read8(0, 0x1d, 0x2, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x2, 0x4, 0xfe);
+ pci_write16(0, 0x1d, 0x3, 0x20, 0x0);
+ gav(pci_read8(0, 0x1d, 0x3, 0x4)); // = 0xff
+ pci_write8(0, 0x1d, 0x3, 0x4, 0xfe);
+ pci_write16(0, 0x1a, 0x0, 0x20, 0x0);
+ gav(pci_read8(0, 0x1a, 0x0, 0x4)); // = 0xff
+ pci_write8(0, 0x1a, 0x0, 0x4, 0xfe);
+ pci_write16(0, 0x1a, 0x1, 0x20, 0x0);
+ gav(pci_read8(0, 0x1a, 0x1, 0x4)); // = 0xff
+ pci_write8(0, 0x1a, 0x1, 0x4, 0xfe);
+ pci_write16(0, 0x1a, 0x2, 0x20, 0x0);
+ gav(pci_read8(0, 0x1a, 0x2, 0x4)); // = 0xff
+ pci_write8(0, 0x1a, 0x2, 0x4, 0xfe);
+ write32(DEFAULT_RCBA | 0x3598, 0x0);
+ }
+}
+
+static void pm_wait(u16 us)
+{
+ u32 base = read_acpi32(8);
+ u32 ticks = (us * 358) / 100;
+ while (((read_acpi32(8) - base) & 0xffffff) < ticks) ;
+}
+
+static void pre_raminit1(void)
+{
+ u16 si;
+
+ outb(0x0, 0x62);
+
+ unsigned number_cores;
+ struct cpuid_result result;
+ unsigned threads_per_package, threads_per_core;
+
+ /* Logical processors (threads) per core */
+ result = cpuid_ext(0xb, 0);
+ threads_per_core = result.ebx & 0xffff;
+
+ /* Logical processors (threads) per package */
+ result = cpuid_ext(0xb, 1);
+ threads_per_package = result.ebx & 0xffff;
+
+ if (threads_per_package == 0 || threads_per_core == 0
+ || threads_per_package % threads_per_core)
+ number_cores = 1;
+ else
+ number_cores = threads_per_package / threads_per_core;
+
+ u8 al = nvram_read(0x4c);
+ if (number_cores <= 1)
+ si = 0;
+ else if (!(al & 1))
+ si = 1;
+ else if (number_cores <= 2)
+ si = 0;
+ else if (!(al & 2))
+ si = 2;
+ else
+ si = 0;
+ if (!(nvram_read(0x55) & 2))
+ si |= 0x100;
+ /* bit 0 = disable multicore,
+ bit 1 = disable quadcore,
+ bit 8 = disable hyperthreading. */
+ pci_write32(QUICKPATH_BUS, 0x0, 0x0, 0x80,
+ (pci_read32(0xff, 0x0, 0x0, 0x80) & 0xfffffefc) | 0x10000 |
+ si);
+
+ outb(0x1, 0x62);
+ outb(0x4, 0x62);
+ pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+ gav(read32(DEFAULT_RCBA | 0x3410));
+ write32(DEFAULT_RCBA | 0x3410, 0xc61);
+ gav(read32(DEFAULT_RCBA | 0x3410));
+ pci_write32(SOUTHBRIDGE, PMBASE, 0x400);
+ pci_write8(SOUTHBRIDGE, ACPI_CNTL, 0x80);
+
+ u16 t4041 = read_tco16(0x8);
+ gav(t4041);
+ write_tco16(0x8, t4041);
+
+ pci_write32(SOUTHBRIDGE, 0xd0, 0x0);
+
+ pci_write16(SOUTHBRIDGE, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMA_LPC_EN);
+
+ u32 t4046 = pci_read32(SOUTHBRIDGE, 0xdc);
+ gav(t4046);
+ pci_write32(SOUTHBRIDGE, BIOS_CNTL, t4046);
+ pci_write32(QUICKPATH_BUS, 0x0, 0x1, 0x50, DEFAULT_PCIEXBAR | 1);
+ pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+ gav(read32(DEFAULT_RCBA | 0x3410));
+ write32(DEFAULT_RCBA | 0x3410, 0xc61);
+
+ pci_write32(SOUTHBRIDGE, LPC_GEN1_DEC, 0x7c1601);
+ pci_write32(SOUTHBRIDGE, LPC_GEN3_DEC, 0x1c1681);
+ outb(0x2, 0x62);
+
+ my_write_msr(0x79, 0xffec1410);
+ //Unrecognised: [ffff000:fc22] 00c0.00c1 Microcode Update: ERROR: Cannot fake write in a post-hook.
+
+ //Unrecognised: [ffff000:fb6a] 00c8.00c9 CPUID: eax: 00000006; ecx: 0000008b => 00000005.00000002.00000001.00000000
+
+ {
+ u8 reg8;
+ struct cpuid_result result;
+ result = cpuid_ext(0x6, 0x8b);
+ if (!(result.eax & 0x2)) {
+ reg8 = ((my_read_msr(MSR_FSB_CLOCK_VCC) & 0xff00) >> 8) + 1;
+ my_write_msr(IA32_PERF_CTL,
+ (my_read_msr(IA32_PERF_CTL) & ~0xffULL) | reg8);
+ my_write_msr(MSR_IA32_MISC_ENABLES,
+ (my_read_msr(MSR_IA32_MISC_ENABLES) &
+ ~0x0000004000000000ULL) | 0x10000);
+ }
+
+ reg8 = ((my_read_msr(MSR_FSB_CLOCK_VCC) & 0xff00) >> 8);
+ my_write_msr(IA32_PERF_CTL, (my_read_msr(IA32_PERF_CTL) & ~0xffULL) | reg8);
+ my_write_msr(MSR_IA32_MISC_ENABLES, my_read_msr(MSR_IA32_MISC_ENABLES) | 0x10000);
+ my_write_msr(0x1f1, my_read_msr(0x1f1) | 1);
+ }
+
+ outb(0x5, 0x62);
+
+ /*Unrecognised: [ffff000:fc9f] 00ed.00ee LAPIC: [00000300] <= 000c4500
+
+ Unrecognised: [ffff000:fc9f] 00ed.00ef LAPIC: [00000300] => 000c0500
+ */
+ outb(0x3, 0x62);
+
+ outb(0x0, 0x62);
+ outb(0x2, 0x62);
+ outb(0x2c, 0x62);
+ outb(0x12, 0x62);
+ outb(0x30, 0x62);
+ /*Unrecognised: addr ff7ff7da val ff7ff856 */
+
+ outb(0x13, 0x62);
+ outb(0x28, 0x62);
+ outb(0x29, 0x62);
+ outb(0x17, 0x62);
+ outb(0x27, 0x62);
+ outb(0x4a, 0x62);
+ /*Unrecognised: addr ff7ff7da val ff7ff856 */
+
+ gav(pci_mm_read16(SOUTHBRIDGE, PMBASE)); // = 0x1001
+
+ outb(0x11, 0x62);
+ outb(0x40, 0x62);
+
+ pci_write32(NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+
+ pci_write32(0, 0x1f, 0x3, SMB_BASE, SMBUS_IO_BASE);
+ pci_write32(0, 0x1f, 0x3, HOSTC, 0x1);
+ gav(pci_read16(0, 0x1f, 0x3, 0x4)); // = 0x1
+ pci_write16(0, 0x1f, 0x3, 0x4, 0x1);
+
+ pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+ pci_mm_write32(NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+ pci_mm_write32(NORTHBRIDGE, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
+ gav(pci_mm_read8(HECIDEV, PCI_VENDOR_ID)); // = 0x86
+ pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+ gav(pci_read32(SOUTHBRIDGE, PMBASE)); // = 0x1001
+ pci_write32(SOUTHBRIDGE, PMBASE, 0x1001);
+ gav(pci_read8(SOUTHBRIDGE, ACPI_CNTL)); // = 0x80
+ pci_write8(SOUTHBRIDGE, ACPI_CNTL, 0x80);
+ gav(pci_read8(SOUTHBRIDGE, 0xa6)); // = 0x2
+ pci_write8(SOUTHBRIDGE, 0xa6, 0x2);
+ gav(pci_read32(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+ pci_write32(SOUTHBRIDGE, GPIOBASE, DEFAULT_GPIOBASE | 1);
+ gav(pci_read8(SOUTHBRIDGE, GPIO_CNTL)); // = 0x10
+ pci_write8(SOUTHBRIDGE, GPIO_CNTL, 0x10);
+ gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6
+ gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6
+ gav(read32(DEFAULT_RCBA | 0x3598));
+ gav(pci_read32(0, 0x1d, 0x0, 0xfc)); // = 0x20191708
+ pci_write32(0, 0x1d, 0x0, 0xfc, 0x20191708);
+ gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6
+ gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6
+ gav(pci_read8(0, 0x1d, 0x0, 0x88)); // = 0xa0
+ pci_write8(0, 0x1d, 0x0, 0x88, 0xa0);
+ gav(pci_read32(0, 0x1a, 0x0, 0xfc)); // = 0x20191708
+ pci_write32(0, 0x1a, 0x0, 0xfc, 0x20191708);
+ gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6
+ gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6
+ gav(pci_read8(0, 0x1a, 0x0, 0x88)); // = 0xa0
+ pci_write8(0, 0x1a, 0x0, 0x88, 0xa0);
+ write8(DEFAULT_RCBA | 0x14, 0x11);
+ write16(DEFAULT_RCBA | 0x50, 0x7654);
+ enable_hpet();
+ u32 t4143 = read32(0xfed00010);
+ gav(t4143);
+ write32(0xfed00010, t4143 | 1);
+
+
+ gav(read8(DEFAULT_RCBA | 0x3428));
+ write8(DEFAULT_RCBA | 0x3428, 0x1d);
+ pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x40000000);
+ pci_mm_write32(0, 0x1f, 0x6, 0x44, 0x0);
+ gav(pci_mm_read32(0, 0x1f, 0x6, 0x40)); // = 0x40000004
+ pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x40000005);
+ u16 t4;
+ t4 = read16(0x4000001a);
+ gav(t4);
+ write16(0x4000001a, (t4 & ~0xf) | 0x10f0);
+ gav(pci_mm_read32(0, 0x1f, 0x6, 0x40)); // = 0x40000005
+ pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x40000004);
+ pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x0);
+
+ pci_read16(SOUTHBRIDGE, PMBASE); // = 0x1001
+ pci_read16(SOUTHBRIDGE, GPIOBASE); // = DEFAULT_GPIOBASE | 1
+ gav(read8(DEFAULT_RCBA | 0x3414));
+ gav(read_acpi16(0x0));
+
+ u16 pm1cnt;
+ gav(pm1cnt = read_acpi16(0x4));
+ s3resume = ((pm1cnt >> 10) & 7) == 5;
+ if (s3resume) {
+ u8 ra2, ra4;
+ gav(ra2 = pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2)); // = 0xa0
+ gav(ra4 = pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3)); // = 0x9
+ if (!(ra2 & 0x20)) {
+ s3resume = 0;
+ write_acpi16(0x4, 0);
+ }
+ }
+
+ pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_3,
+ (gav(pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3)) & ~2) | 1);
+
+ pci_mm_write8(0, 0x3, 0x0, 0x4, 0x0);
+ write16(DEFAULT_RCBA | 0x3124, 0x2321);
+ pci_mm_write8(SOUTHBRIDGE, 0xdc, 0x0);
+
+ pci_mm_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+ gav(pci_mm_read16(SOUTHBRIDGE, LPC_IO_DEC)); // = 0x10
+ pci_mm_write16(SOUTHBRIDGE, LPC_IO_DEC, 0x10);
+ pci_mm_write16(SOUTHBRIDGE, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ GAMEH_LPC_EN | GAMEL_LPC_EN | LPT_LPC_EN | COMB_LPC_EN |
+ COMA_LPC_EN);
+}
+
+static void pre_raminit_2(void)
+{
+ pci_mm_write16(SOUTHBRIDGE, GPIOBASE, DEFAULT_GPIOBASE);
+ pci_mm_read8(SOUTHBRIDGE, GPIO_CNTL); // = 0x10
+ pci_mm_write8(SOUTHBRIDGE, GPIO_CNTL, 0x10);
+ gav(inw(DEFAULT_GPIOBASE | 0x38)); // = 0x10
+
+ outl(0x1963a5ff, DEFAULT_GPIOBASE);
+ outl(0xffffffff, DEFAULT_GPIOBASE | 0xc);
+ outl(0x87bf6aff, DEFAULT_GPIOBASE | 0x4);
+ outl(0x0, DEFAULT_GPIOBASE | 0x18);
+ outl(0x120c6, DEFAULT_GPIOBASE | 0x2c);
+ outl(0x27706fe, DEFAULT_GPIOBASE | 0x30);
+ outl(0x29fffff, DEFAULT_GPIOBASE | 0x38);
+ outl(0x1b01f9f4, DEFAULT_GPIOBASE | 0x34);
+ outl(0x0, DEFAULT_GPIOBASE | 0x40);
+ outl(0x0, DEFAULT_GPIOBASE | 0x48);
+ outl(0xf00, DEFAULT_GPIOBASE | 0x44);
+
+ pci_mm_write16(SOUTHBRIDGE, PMBASE, DEFAULT_PMBASE);
+ gav(pci_mm_read8(SOUTHBRIDGE, ACPI_CNTL)); // = 0x80
+ pci_mm_write8(SOUTHBRIDGE, ACPI_CNTL, 0x80);
+ pci_mm_write32(SOUTHBRIDGE, ETR3, gav(pci_mm_read32(SOUTHBRIDGE, ETR3)) & ~ETR3_CF9GR); // OK
+ pci_mm_write32(SOUTHBRIDGE, LPC_GEN1_DEC, 0xc0681);
+
+ gav(read32(DEFAULT_RCBA | 0x3400));
+ write32(DEFAULT_RCBA | 0x3400, 0x1c);
+ gav(read32(DEFAULT_RCBA | 0x3410));
+ write32(DEFAULT_RCBA | 0x3410, 0xc61);
+
+ gav(read_tco16(0x8));
+ write_tco16(0x8, 0x800);
+ write_tco8(0x6, gav(read_tco8(0x6)) | 0x2);
+
+ gav(inb(0x61)); // = 0x2
+ outb(0x3c, 0x61);
+
+ enable_hpet();
+
+ if (pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3) & 4) {
+ nvram_write(0xa, nvram_read(0xa) | 0x70);
+ nvram_write(0xb, nvram_read(0xb) | 0x80);
+ nvram_write(0xa, nvram_read(0xa) & ~0x50);
+ nvram_write(0xb, nvram_read(0xb) & ~0x80);
+ }
+ gav(read32(DEFAULT_RCBA | 0x3410));
+ write32(DEFAULT_RCBA | 0x3410, 0xc61);
+ gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6
+ gav(inl(DEFAULT_GPIOBASE)); // = 0x6
+ outl(0x7963a5ff, DEFAULT_GPIOBASE);
+ gav(inl(DEFAULT_GPIOBASE | 0x4)); // = 0x7963a5ff
+ outl(0x87bf6aff, DEFAULT_GPIOBASE | 0x4);
+ outl(gav(inl(DEFAULT_GPIOBASE | 0xc)) | 0x40000000,
+ DEFAULT_GPIOBASE | 0xc);
+ gav(inl(DEFAULT_GPIOBASE | 0x60)); // = 0xfffbfffb
+ outl(0x41000000, DEFAULT_GPIOBASE | 0x60);
+ pci_write32(SOUTHBRIDGE, LPC_GEN3_DEC, 0x1c1681);
+ pci_write32(SOUTHBRIDGE, LPC_GEN2_DEC, 0xc15e1);
+ pci_write32(SOUTHBRIDGE, LPC_GEN1_DEC, 0x7c1601);
+ gav(inl(DEFAULT_GPIOBASE | 0xc)); // = 0x7c1601
+ outb(0x15, 0x62);
+ outb(0x16, 0x62);
+
+
+ gav(pci_read32(NORTHBRIDGE, D0F0_MCHBAR_LO)); // = DEFAULT_MCHBAR | 1
+}
+
+static void enable_hpet(void)
+{
+#if REAL
+ u32 reg32;
+
+ /* Move HPET to default address 0xfed00000 and enable it */
+ reg32 = RCBA32(HPTC);
+ reg32 |= (1 << 7); // HPET Address Enable
+ reg32 &= ~(3 << 0);
+ RCBA32(HPTC) = reg32;
+#else
+ write32(DEFAULT_RCBA | HPTC, 0x80);
+#endif
+}
+
+static void pre_raminit_4a(void)
+{
+#if !REAL
+ int i;
+
+ outb(0x55, 0x62);
+
+ outb(0x32, 0x62);
+ /*Unrecognised: addr ff7ff7da val ff7ff856 */
+
+ gav(pci_read32(0, 0x1f, 0x3, 0x0)); // = 0x3b308086
+ pci_write32(0, 0x1f, 0x3, 0x20, 0x1100);
+ gav(pci_read8(0, 0x1f, 0x3, 0x4)); // = 0x1
+ pci_write8(0, 0x1f, 0x3, 0x4, 0x1);
+ gav(pci_read8(0, 0x1f, 0x3, 0x40)); // = 0x1
+ pci_write8(0, 0x1f, 0x3, 0x40, 0x9);
+ gav(pci_read8(0, 0x1f, 0x3, 0x40)); // = 0x1
+ pci_write8(0, 0x1f, 0x3, 0x40, 0x1);
+
+ outb(0x4f, 0x62);
+ outb(0x50, 0x62);
+ /*Unrecognised: addr ff7ff7da val ff7ff856 */
+
+ gav(pci_read8(NORTHBRIDGE, D0F0_CAPID0 + 8)); // = 0x88
+ my_read_msr(0x17); // !!!
+ /*Unrecognised: [0000:fffaf715] 1a183.1a184 Microcode Update: ERROR: Cannot fake write in a post-hook. */
+
+ my_read_msr(0x17); // !!!
+ /*Unrecognised: [0000:fffaf715] 1a25d.1a25e Microcode Update: ERROR: Cannot fake write in a post-hook. */
+
+ outb(0x48, 0x62);
+ if (x2ca8 != 0) {
+ outb(0x42, 0x15ec);
+ gav(inb(0x15ee)); // = 0x42
+ }
+#endif
+ u16 t3;
+
+ if (x2ca8 == 0) {
+ gav(t3 = inw(DEFAULT_GPIOBASE | 0x38));
+ outw(t3 & ~0x400, DEFAULT_GPIOBASE | 0x38);
+ gav(smbus_read_byte(0x5c, 0x06));
+ smbus_write_byte(0x5c, 0x06, 0x8f);
+
+#if !REAL
+ for (i = 0; i < 5; i++)
+ pm_wait(0x3e8);
+#endif
+
+ gav(smbus_read_byte(0x5c, 0x07));
+ smbus_write_byte(0x5c, 0x07, 0x8f);
+
+#if !REAL
+ for (i = 0; i < 5; i++)
+ pm_wait(0x3e8);
+#endif
+ gav(pci_mm_read16(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+ outw(t3 | 0x400, DEFAULT_GPIOBASE | 0x38);
+#if !REAL
+ outb(0x42, 0x15ec);
+ gav(inb(0x15ee)); // = 0x42
+ gav(pci_mm_read16(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+#endif
+ }
+
+ gav(t3 = inw(DEFAULT_GPIOBASE | 0x38));
+ outw(t3 & ~0x400, DEFAULT_GPIOBASE | 0x38);
+
+ gav(smbus_read_byte(0x57, 0x55));
+ gav(pci_mm_read16(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+ outw(t3 | 0x400, DEFAULT_GPIOBASE | 0x38);
+
+#if !REAL
+ outb(0x42, 0x62);
+ gav(read_tco16(0x6));
+ pci_mm_write32(NORTHBRIDGE, PCI_SUBSYSTEM_VENDOR_ID, 0x219317aa);
+ pci_mm_write32(0, 0x1, 0x0, 0x8c, 0x219417aa);
+ pci_mm_write32(0xff, 0, 0, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+ pci_mm_write32(0xff, 0, 1, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+ pci_mm_write32(0xff, 2, 0, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+ pci_mm_write32(0xff, 2, 1, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+ pci_mm_write32(NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+ pci_mm_write32(NORTHBRIDGE, D0F0_MCHBAR_HI, 0x0);
+ pci_mm_write32(NORTHBRIDGE, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
+ pci_mm_write32(NORTHBRIDGE, D0F0_DMIBAR_HI, 0x0);
+ pci_mm_write32(NORTHBRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
+ pci_mm_write32(NORTHBRIDGE, D0F0_EPBAR_HI, 0x0);
+ pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_LO); // = DEFAULT_MCHBAR | 1
+ pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_HI); // = 0x0
+#endif
+}
+
+static void dmi_setup(void)
+{
+ gav(read8(DEFAULT_DMIBAR | 0x254));
+ write8(DEFAULT_DMIBAR | 0x254, 0x1);
+ gav(pci_mm_read32(SOUTHBRIDGE, 0xec)); // = 0x2b83806
+ write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+ pci_mm_write16(NORTHBRIDGE, D0F0_DEVEN,
+ pci_mm_read16(NORTHBRIDGE, D0F0_DEVEN) & 0xfeff);
+ read_mchbar16(0x48);
+ write_mchbar16(0x48, 0x2);
+ my_read_msr(0x17);
+
+ pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1
+ if (pci_mm_read16(0, 0x1, 0x0, 0x0) != 0xffff) {
+ gav(pci_mm_read16(0, 0x1, 0x0, 0xac));
+ pci_mm_write32(0, 0x1, 0x0, 0x200,
+ pci_mm_read32(0, 0x1, 0x0, 0x200) & ~0x100);
+ pci_mm_write8(0, 0x1, 0x0, 0x1f8,
+ (pci_mm_read8(0, 0x1, 0x0, 0x1f8) & ~1) | 4);
+ u32 t4431 = read32(DEFAULT_DMIBAR | 0xd68);
+ gav(t4431);
+ write32(DEFAULT_DMIBAR | 0xd68, t4431 | 0x08000000);
+ pci_mm_write32(0, 0x1, 0x0, 0x200,
+ pci_mm_read32(0, 0x1, 0x0, 0x200) & ~0x00200000);
+ gav(pci_mm_read8(0, 0x1, 0x0, 0xd60)); // = 0x0
+ gav(pci_mm_read8(0, 0x1, 0x0, 0xd60)); // = 0x0
+ pci_mm_write8(0, 0x1, 0x0, 0xd60, 0x3);
+ gav(pci_mm_read16(0, 0x1, 0x0, 0xda8)); // = 0xbf9
+ gav(pci_mm_read16(0, 0x1, 0x0, 0xda8)); // = 0xbf9
+ pci_mm_write16(0, 0x1, 0x0, 0xda8, 0xf9);
+ pci_mm_read16(0, 0x1, 0x0, 0xda8); // = 0xf9
+ pci_mm_read16(0, 0x1, 0x0, 0xda8); // = 0xf9
+ pci_mm_write16(0, 0x1, 0x0, 0xda8, 0x79);
+ pci_mm_read8(0, 0x1, 0x0, 0xd0); // = 0x2
+ pci_mm_read8(0, 0x1, 0x0, 0xd0); // = 0x2
+ pci_mm_write8(0, 0x1, 0x0, 0xd0, 0x1);
+ pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0xd
+ pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0); // = 0x10c0009
+ pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0 + 4); // = 0x316126
+ pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0xd
+ pci_mm_write16(0, 0x1, 0x0, 0x224, 0x1d);
+ pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff
+ pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0x1d
+ pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff
+ pci_mm_write16(0, 0x1, 0x0, 0xac, 0x4d01);
+ pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0x1d
+ pci_mm_read8(0, 0x1, 0x0, 0xba); // = 0x0
+ pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0x8086
+ pci_mm_read32(0, 0x1, 0x0, 0xc00); // = 0xffffffff
+ pci_mm_write32(0, 0x1, 0x0, 0xc00, 0xffffc0fc);
+ pci_mm_read32(0, 0x1, 0x0, 0xc04); // = 0x9600000f
+ pci_mm_write32(0, 0x1, 0x0, 0xc04, 0x96000000);
+ pci_mm_read32(0, 0x1, 0x0, 0xc04); // = 0x96000000
+ pci_mm_write32(0, 0x1, 0x0, 0xc04, 0x16000000);
+ pci_mm_write32(0, 0x1, 0x0, 0xc08, 0x0);
+ } else
+ pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0xffff
+
+
+ pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1
+ pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff
+ pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff
+ pci_mm_write32(HECIDEV, HECIBAR, DEFAULT_HECIBAR);
+ pci_mm_write32(HECIDEV, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
+ DEFAULT_GPIOBASE | 0x38);
+ gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e
+
+ pci_mm_write32(0, 0x2, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x215a17aa);
+ pci_mm_write8(NORTHBRIDGE, D0F0_DEVEN,
+ pci_mm_read8(NORTHBRIDGE, D0F0_DEVEN) | 2);
+
+ pci_mm_write16(0, 0x1, 0x0, 0x224,
+ pci_mm_read16(0, 0x1, 0x0, 0x224) | 1);
+ pci_mm_write16(NORTHBRIDGE, D0F0_GGC,
+ pci_mm_read16(NORTHBRIDGE, D0F0_GGC) | 2);
+
+ pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_LO); // = DEFAULT_MCHBAR | 1
+ pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_HI); // = 0x0
+ pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1
+ pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_HI); // = 0x0
+
+ const struct {
+ int dev, func;
+ } bridges[] = { {
+ 0x1e, 0}, {
+ 0x1c, 0}, {
+ 0x1c, 1}, {
+ 0x1c, 2}, {
+ 0x1c, 3}, {
+ 0x1c, 4}, {
+ 0x1c, 5}, {
+ 0x1c, 6}, {
+ 0x1c, 7}};
+ for (i = 0; i < sizeof(bridges) / sizeof(bridges[0]); i++) {
+ u16 dev;
+ pci_mm_write32(0, bridges[i].dev, bridges[i].func, 0x18,
+ 0x20200);
+ for (dev = 0; dev < 0x20; dev++) {
+ u16 vendor = pci_mm_read16(2, dev, 0x0, 0x0);
+ if (vendor == 0xffff)
+ continue;
+ pci_mm_read16(2, dev, 0x0, 0xa);
+ }
+ pci_mm_write32(0, bridges[i].dev, bridges[i].func, 0x18, 0x0);
+ }
+
+ pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0x8086
+ pci_mm_read8(NORTHBRIDGE, D0F0_CAPID0 + 6); // = 0x31
+ pci_mm_read8(0, 0x1, 0x0, 0xba); // = 0x0
+ pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff
+ pci_mm_read8(NORTHBRIDGE, D0F0_CAPID0 + 6); // = 0x31
+ pci_mm_read8(0, 0x6, 0x0, 0xba); // = 0xff
+ pci_mm_read16(0, 0x1, 0x0, 0x11a); // = 0x2
+ pci_mm_read16(0, 0x6, 0x0, 0x11a); // = 0xffff
+ pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0x8086
+ pci_mm_read32(0, 0x1, 0x0, 0x18); // = 0x0
+ pci_mm_write32(0, 0x1, 0x0, 0x18, 0x0);
+ pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff
+}
+
+static void pre_raminit_5(int s3resume)
+{
+ int i;
+
+ for (i = 0x10; i < 0x28;) {
+ u32 s;
+ pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff
+ pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff
+ pci_mm_write32(0, 0x2, 0x0, i, 0x0);
+ pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff
+ pci_mm_write32(0, 0x2, 0x0, i, 0xffffffff);
+ s = pci_mm_read32(0, 0x2, 0x0, i);
+ if (s != 0xffffffff && s != 0) {
+ if (s & 1) {
+ pci_mm_write32(0, 0x2, 0x0, i, s & 0x7);
+ i += 4;
+ } else {
+ pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff
+ pci_mm_write32(0, 0x2, 0x0, i, s & 0xf);
+ i += 8;
+ }
+ } else
+ i += 4;
+ }
+ pci_mm_read8(0, 0x1d, 0x0, 0x80); // = 0x0
+ pci_mm_write8(0, 0x1d, 0x0, 0x80, 0x1);
+ pci_mm_read8(0, 0x1a, 0x0, 0x80); // = 0x0
+ pci_mm_write8(0, 0x1a, 0x0, 0x80, 0x1);
+ pci_mm_write32(HECIDEV, PCI_SUBSYSTEM_VENDOR_ID, 0x215f17aa);
+ pci_mm_write32(0, 0x16, 0x2, PCI_SUBSYSTEM_VENDOR_ID, 0x216117aa);
+ pci_mm_write32(0, 0x16, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x216217aa);
+ pci_mm_write32(0, 0x1a, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x216317aa);
+ pci_mm_write32(0, 0x1b, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x215e17aa);
+ pci_mm_write32(0, 0x1c, 0x0, 0x94, 0x216417aa);
+ pci_mm_write32(0, 0x1c, 0x1, 0x94, 0x216417aa);
+ pci_mm_write32(0, 0x1c, 0x2, 0x94, 0x216417aa);
+ pci_mm_write32(0, 0x1c, 0x3, 0x94, 0x216417aa);
+ pci_mm_write32(0, 0x1c, 0x4, 0x94, 0x216417aa);
+ pci_mm_write32(0, 0x1d, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x216317aa);
+ pci_mm_write32(0, 0x1e, 0x0, 0x54, 0x216517aa);
+ pci_mm_write32(SOUTHBRIDGE, PCI_SUBSYSTEM_VENDOR_ID, 0x216617aa);
+ pci_mm_write32(0, 0x1f, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x216717aa);
+ pci_mm_write32(0, 0x1f, 0x5, PCI_SUBSYSTEM_VENDOR_ID, 0x216a17aa);
+ pci_mm_write32(0, 0x1f, 0x6, PCI_SUBSYSTEM_VENDOR_ID, 0x219017aa);
+ pci_mm_read8(0, 0x1d, 0x0, 0x80); // = 0x1
+ pci_mm_write8(0, 0x1d, 0x0, 0x80, 0x0);
+ pci_mm_read8(0, 0x1a, 0x0, 0x80); // = 0x1
+ pci_mm_write8(0, 0x1a, 0x0, 0x80, 0x0);
+ pci_mm_write32(13, 0x0, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x213317aa);
+ pci_mm_write32(13, 0x0, 0x1, PCI_SUBSYSTEM_VENDOR_ID, 0x213417aa);
+ pci_mm_write32(13, 0x0, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x213617aa);
+
+ pci_mm_write32(HECIDEV, HECIBAR, DEFAULT_HECIBAR);
+ pci_mm_write32(HECIDEV, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ write_acpi16(0x2, 0x0);
+ write_acpi32(0x28, 0x0);
+ write_acpi32(0x2c, 0x0);
+ if (!s3resume) {
+ gav(read_acpi32(0x4));
+ gav(read_acpi32(0x20));
+ gav(read_acpi32(0x34));
+ write_acpi16(0x0, 0x900);
+ write_acpi32(0x20, 0xffff7ffe);
+ write_acpi32(0x34, 0x56974);
+ pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_3,
+ pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3) | 2);
+ }
+
+ gav(read32(DEFAULT_RCBA | 0x3410));
+
+ if (gav(read32(DEFAULT_RCBA | 0x3804)) & 0x4000) {
+ u32 v;
+
+ write8(DEFAULT_RCBA | 0x3894, 0x6);
+ write8(DEFAULT_RCBA | 0x3895, 0x50);
+ write8(DEFAULT_RCBA | 0x3896, 0x3b);
+ write8(DEFAULT_RCBA | 0x3897, 0x14);
+ write8(DEFAULT_RCBA | 0x3898, 0x2);
+ write8(DEFAULT_RCBA | 0x3899, 0x3);
+ write8(DEFAULT_RCBA | 0x389a, 0x20);
+ write8(DEFAULT_RCBA | 0x389b, 0x5);
+ write8(DEFAULT_RCBA | 0x389c, 0x9f);
+ write8(DEFAULT_RCBA | 0x389d, 0x20);
+ write8(DEFAULT_RCBA | 0x389e, 0x1);
+ write8(DEFAULT_RCBA | 0x389f, 0x6);
+ write8(DEFAULT_RCBA | 0x3890, 0xc);
+ gav(read8(DEFAULT_RCBA | 0x3890));
+ write32(DEFAULT_RCBA | 0x3808, 0x0);
+ gav(read32(DEFAULT_RCBA | 0x3808));
+ write16(DEFAULT_RCBA | 0x3891, 0x4242);
+ gav(read16(DEFAULT_RCBA | 0x3891));
+ gav(read8(DEFAULT_RCBA | 0x3890));
+ write8(DEFAULT_RCBA | 0x3890, 0xc);
+ gav(read8(DEFAULT_RCBA | 0x3890));
+ if ((gav(read32(DEFAULT_RCBA | 0x3810)) & 0x20) || WTF1)
+ v = 0x2005;
+ else
+ v = 0x2015;
+ write32(DEFAULT_RCBA | 0x38c8, v);
+ write32(DEFAULT_RCBA | 0x38c4, 0x800000 | v);
+ gav(read32(DEFAULT_RCBA | 0x38b0));
+ write32(DEFAULT_RCBA | 0x38b0, 0x1000);
+ gav(read32(DEFAULT_RCBA | 0x38b4));
+ gav(read32(DEFAULT_RCBA | 0x38b0));
+ write32(DEFAULT_RCBA | 0x38b0, 0x4);
+ gav(read32(DEFAULT_RCBA | 0x38b4));
+ write32(DEFAULT_RCBA | 0x3874, 0x1fff07d0);
+ }
+ gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0x1fff07d0
+
+ set_fsb_frequency ();
+
+ outb(0x44, 0x62);
+ outb(0x3c, 0x62);
+ nvram_read(0x71);
+ my_read_msr (MTRRcap_MSR);
+ my_read_msr (MTRRphysMask_MSR (0));
+ my_read_msr (MTRRphysMask_MSR (1));
+ my_read_msr (MTRRphysMask_MSR (2));
+ my_read_msr (MTRRphysMask_MSR (3));
+
+ gav(read32(DEFAULT_RCBA | 0x3410));
+ write32(DEFAULT_RCBA | 0x3410, 0xc61);
+
+ gav(read8(0xfed40000));
+ pci_mm_read32(0xff, 0, 0, 0x88);
+ read_mchbar32(0x28);
+ gav(read8(0xfed30008));
+}
diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/nehalem/raminit_tables.c
new file mode 100644
index 0000000..8047a69
--- /dev/null
+++ b/src/northbridge/intel/nehalem/raminit_tables.c
@@ -0,0 +1,1258 @@
+/* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */
+const u8 u8_FFFD1240[2][5][9][4][4] = {
+ {
+ {
+ {
+ {0x3b, 0x53, 0x57, 0x5c},
+ {0x3b, 0x52, 0x57, 0x5c},
+ {0x3b, 0x4d, 0x51, 0x54},
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+ {0x70, 0x80, 0x91, 0xa1},
+ },
+ {
+ {0x70, 0x80, 0x91, 0xa1},
+ {0x70, 0x80, 0x91, 0xa1},
+ {0x70, 0x80, 0x91, 0xa1},
+ {0x70, 0x80, 0x91, 0xa1},
+ },
+ {
+ {0x5c, 0x79, 0x87, 0x94},
+ {0x5c, 0x79, 0x87, 0x94},
+ {0x5c, 0x79, 0x87, 0x94},
+ {0x5c, 0x79, 0x87, 0x94},
+ }
+ }
+ }
+};
+
+const u16 u16_FFFE0EB8[2][4] = {
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000}
+};
+
+/* [CARD][LANE][CLOCK_SPEED] */
+const u16 u16_ffd1188[2][9][4] = {
+ {
+ {0xfff9, 0xfff7, 0xfff5, 0xfff2},
+ {0xfff9, 0xfff7, 0xfff5, 0xfff2},
+ {0xfffb, 0xfff9, 0xfff7, 0xfff6},
+ {0xfffb, 0xfff9, 0xfff7, 0xfff6},
+ {0xfffc, 0xfffb, 0xfffa, 0xfff8},
+ {0xfffc, 0xfffb, 0xfffa, 0xfff8},
+ {0xfffd, 0xfffc, 0xfffb, 0xfffa},
+ {0xfffd, 0xfffc, 0xfffb, 0xfffa},
+ {0x0000, 0x0000, 0x0000, 0x0000}
+ },
+ {
+ {0x0001, 0x0001, 0x0001, 0x0002},
+ {0xfffa, 0xfff8, 0xfff6, 0xfff4},
+ {0x0001, 0x0002, 0x0002, 0x0003},
+ {0xffe2, 0xffd8, 0xffce, 0xffc4},
+ {0x0021, 0x002d, 0x0038, 0x0043},
+ {0x0004, 0x0005, 0x0006, 0x0007},
+ {0x000e, 0x0013, 0x0018, 0x001d},
+ {0x0009, 0x000c, 0x000f, 0x0012},
+ {0x0000, 0x0000, 0x0000, 0x0000}
+ }
+};
+
+/* [REVISION][CHANNEL][CLOCK_INDEX][?] */
+const u8 u8_FFFD1891[2][2][4][12] = {
+ {
+ {
+ {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ },
+ {
+ {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ }
+ },
+ {
+ {
+ {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ },
+ {
+ {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00,
+ 0x00},
+ {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x74}
+ }
+ }
+};
+
+const u8 u8_FFFD17E0[2][5][4][4] = {
+ {
+ {
+ {0x00, 0x0c, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x23, 0x19, 0x0f, 0x05},
+ {0x23, 0x19, 0x0f, 0x05},
+ },
+ {
+ {0x00, 0x0c, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x23, 0x19, 0x0f, 0x05},
+ {0x23, 0x19, 0x0f, 0x05},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x44, 0x45, 0x47, 0x05},
+ {0x44, 0x45, 0x47, 0x05},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x44, 0x45, 0x46, 0x44},
+ {0x44, 0x45, 0x46, 0x44},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x2a, 0x24, 0x1e, 0x16},
+ {0x2a, 0x24, 0x1e, 0x16},
+ },
+ },
+ {
+ {
+ {0x00, 0x08, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x27, 0x1e, 0x16, 0x0d},
+ {0x27, 0x1e, 0x16, 0x0d},
+ },
+ {
+ {0x00, 0x08, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x27, 0x1e, 0x16, 0x0d},
+ {0x27, 0x1e, 0x16, 0x0d},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x44, 0x45, 0x47, 0x05},
+ {0x44, 0x45, 0x47, 0x05},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x43, 0x44, 0x45, 0x43},
+ {0x43, 0x44, 0x45, 0x43},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x2a, 0x24, 0x1e, 0x16},
+ {0x2a, 0x24, 0x1e, 0x16},
+ },
+ },
+};
+
+const u8 u8_FFFD0C78[2][5][4][2][2][4] = {
+ {
+ {
+ {
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ },
+ {
+ {
+ {0x00, 0x02, 0x0d, 0x0f},
+ {0x00, 0x02, 0x0d, 0x0f},
+ },
+ {
+ {0x00, 0x02, 0x0d, 0x0f},
+ {0x00, 0x02, 0x0d, 0x0f},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ },
+ {
+ {
+ {0x00, 0x02, 0x0d, 0x0f},
+ {0x00, 0x02, 0x0d, 0x0f},
+ },
+ {
+ {0x00, 0x02, 0x0d, 0x0f},
+ {0x00, 0x02, 0x0d, 0x0f},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ {
+ {
+ {0x04, 0x06, 0x08, 0x0a},
+ {0x04, 0x06, 0x08, 0x0a},
+ },
+ {
+ {0x04, 0x06, 0x08, 0x0a},
+ {0x04, 0x06, 0x08, 0x0a},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ },
+ },
+ {
+ {
+ {
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ },
+ {
+ {
+ {0x00, 0x06, 0x0d, 0x0f},
+ {0x00, 0x06, 0x0d, 0x0f},
+ },
+ {
+ {0x00, 0x06, 0x0d, 0x0f},
+ {0x00, 0x06, 0x0d, 0x0f},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ },
+ {
+ {
+ {0x00, 0x06, 0x13, 0x17},
+ {0x00, 0x06, 0x13, 0x17},
+ },
+ {
+ {0x00, 0x06, 0x13, 0x17},
+ {0x00, 0x06, 0x13, 0x17},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ {
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ {
+ {0x04, 0x05, 0x07, 0x08},
+ {0x04, 0x05, 0x07, 0x08},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ {
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ {
+ {0x06, 0x07, 0x09, 0x0b},
+ {0x06, 0x07, 0x09, 0x0b},
+ },
+ },
+ },
+ {
+ {
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ {
+ {0x00, 0x00, 0x03, 0x04},
+ {0x00, 0x00, 0x03, 0x04},
+ },
+ },
+ {
+ {
+ {0x04, 0x06, 0x08, 0x0a},
+ {0x00, 0x06, 0x0d, 0x0f},
+ },
+ {
+ {0x00, 0x06, 0x0d, 0x0f},
+ {0x00, 0x06, 0x0d, 0x0f},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ },
+ },
+ },
+ },
+};
+
+const u16 u16_fffd0c68[3] = { 0x04c3, 0x064d, 0x068b };
+
+const u16 u16_fffd0c70[2][2] = {
+ {0x06c0, 0x06c9},
+ {0x06a4, 0x06ad}
+};
+
+const u16 u16_fffd0c50[3][2][2] = {
+ {
+ {0x04b9, 0x04af},
+ {0x04a5, 0x049b}
+ },
+ {
+ {0x0625, 0x062f},
+ {0x0639, 0x0643},
+ },
+ {
+ {0x0663, 0x066d},
+ {0x0677, 0x0681}
+ }
+};
+
+/* [CLOCK_INDEX] */
+const u16 min_cycletime[4] = { 0x09c4, 0x0753, 0x05dc, 0x0000 };
+
+/* [CLOCK_INDEX] */
+const u16 min_cas_latency_time[4] = { 0x30d4, 0x2bf2, 0x2904, 0x0000 };
+
+/* [CHANNEL][EXT_SILICON_REVISION][?][CLOCK_INDEX] */
+/* On other mobos may also depend on slot and rank. */
+const u8 u8_FFFD0EF8[2][5][4][4] = {
+ {
+ {
+ {0x00, 0x00, 0x03, 0x04,},
+ {0x00, 0x02, 0x0d, 0x0f,},
+ {0x00, 0x00, 0x00, 0x00,},
+ {0x00, 0x00, 0x00, 0x00,},
+ },
+ {
+ {0x00, 0x00, 0x03, 0x04,},
+ {0x00, 0x02, 0x0d, 0x0f,},
+ {0x00, 0x00, 0x00, 0x00,},
+ {0x00, 0x00, 0x00, 0x00,},
+ },
+ {
+ {0x09, 0x0c, 0x0f, 0x12,},
+ {0x09, 0x0c, 0x0f, 0x12,},
+ {0x09, 0x0c, 0x0f, 0x12,},
+ {0x09, 0x0c, 0x0f, 0x12,},
+ },
+ {
+ {0x06, 0x08, 0x0a, 0x0c,},
+ {0x06, 0x08, 0x0a, 0x0c,},
+ {0x06, 0x08, 0x0a, 0x0c,},
+ {0x06, 0x08, 0x0a, 0x0c,},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00,},
+ {0x07, 0x0a, 0x0d, 0x10,},
+ {0x04, 0x06, 0x08, 0x0a,},
+ {0x04, 0x06, 0x08, 0x0a,},
+ },
+ },
+ {
+ {
+ {0x00, 0x00, 0x03, 0x04,},
+ {0x00, 0x06, 0x0d, 0x0f,},
+ {0x00, 0x00, 0x00, 0x00,},
+ {0x00, 0x00, 0x00, 0x00,},
+ },
+ {
+ {0x00, 0x00, 0x03, 0x04,},
+ {0x00, 0x06, 0x13, 0x17,},
+ {0x00, 0x00, 0x00, 0x00,},
+ {0x00, 0x00, 0x00, 0x00,},
+ },
+ {
+ {0x09, 0x0c, 0x0f, 0x12,},
+ {0x09, 0x0c, 0x0f, 0x12,},
+ {0x09, 0x0c, 0x0f, 0x12,},
+ {0x09, 0x0c, 0x0f, 0x12,},
+ },
+ {
+ {0x09, 0x0c, 0x10, 0x13,},
+ {0x09, 0x0c, 0x10, 0x13,},
+ {0x09, 0x0c, 0x10, 0x13,},
+ {0x09, 0x0c, 0x10, 0x13,},
+ },
+ {
+ {0x00, 0x00, 0x00, 0x00,},
+ {0x07, 0x0a, 0x0d, 0x10,},
+ {0x04, 0x06, 0x08, 0x0a,},
+ {0x04, 0x06, 0x08, 0x0a,},
+ },
+ },
+};
+
+/* [CLOCK_SPEED] */
+const u8 u8_FFFD1218[4] = {
+ 0x15, 0x15, 0x15, 0x12
+};
+
+const u8 reg178_min[] = { 1, 3, 4, 7 };
+const u8 reg178_max[] = { 62, 60, 59, 56 };
+const u8 reg178_step[] = { 5, 4, 3, 2 };
+
+const u16 u16_ffd1178[2][4] = {
+ {0xfffb, 0xfffa, 0xfff8, 0xfff7},
+ {0xfffb, 0xfffa, 0xfff8, 0xfff7},
+};
+
+const u16 u16_fe0eb8[2][4] = {
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000}
+};
+
+const u8 lut16[4] = { 14, 13, 14, 14 };
diff --git a/src/northbridge/intel/nehalem/udelay.c b/src/northbridge/intel/nehalem/udelay.c
new file mode 100644
index 0000000..eb298c1
--- /dev/null
+++ b/src/northbridge/intel/nehalem/udelay.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
+ */
+
+void udelay(u32 us)
+{
+ u32 dword;
+ tsc_t tsc, tsc1, tscd;
+ msr_t msr;
+ u32 fsb = 100, divisor;
+ u32 d; /* ticks per us */
+
+ msr = rdmsr(0xce);
+ divisor = (msr.lo >> 8) & 0xff;
+
+ d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+ multiply_to_tsc(&tscd, us, d);
+
+ tsc1 = rdtsc();
+ dword = tsc1.lo + tscd.lo;
+ if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+ tsc1.hi++;
+ }
+ tsc1.lo = dword;
+ tsc1.hi += tscd.hi;
+
+ do {
+ tsc = rdtsc();
+ } while ((tsc.hi < tsc1.hi)
+ || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+}
diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig
index 5637c4a..02a9869 100644
--- a/src/southbridge/intel/Kconfig
+++ b/src/southbridge/intel/Kconfig
@@ -12,4 +12,5 @@ source src/southbridge/intel/i82870/Kconfig
source src/southbridge/intel/pxhd/Kconfig
source src/southbridge/intel/sch/Kconfig
source src/southbridge/intel/bd82x6x/Kconfig
+source src/southbridge/intel/ibexpeak/Kconfig
source src/southbridge/intel/lynxpoint/Kconfig
diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc
index ba3b1d4..9dca03a 100644
--- a/src/southbridge/intel/Makefile.inc
+++ b/src/southbridge/intel/Makefile.inc
@@ -13,4 +13,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) += ibexpeak
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) += lynxpoint
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
new file mode 100644
index 0000000..af8853f
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -0,0 +1,72 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_IBEXPEAK
+ bool
+
+if SOUTHBRIDGE_INTEL_IBEXPEAK
+
+config SOUTH_BRIDGE_OPTIONS # dummy
+ def_bool y
+ select IOAPIC
+ select HAVE_HARD_RESET
+ select HAVE_USBDEBUG
+ select HAVE_SMI_HANDLER
+ select USE_WATCHDOG_ON_BOOT
+ select PCIEXP_ASPM
+ select PCIEXP_COMMON_CLOCK
+ select SPI_FLASH
+
+config EHCI_BAR
+ hex
+ default 0xfef00000
+
+config EHCI_DEBUG_OFFSET
+ hex
+ default 0xa0
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/intel/ibexpeak/bootblock.c"
+
+config SERIRQ_CONTINUOUS_MODE
+ bool
+ default n
+ help
+ If you set this option to y, the serial IRQ machine will be
+ operated in continuous mode.
+
+config HPET_MIN_TICKS
+ hex
+ default 0x80
+
+config LOCK_MANAGEMENT_ENGINE
+ bool "Lock Management Engine section"
+ default n
+ help
+ The Intel Management Engine supports preventing write accesses
+ from the host to the Management Engine section in the firmware
+ descriptor. If the ME section is locked, it can only be overwritten
+ with an external SPI flash programmer. You will want this if you
+ want to increase security of your ROM image once you are sure
+ that the ME firmware is no longer going to change.
+
+ If unsure, say N.
+
+endif
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
new file mode 100644
index 0000000..0063680
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -0,0 +1,75 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+INTERMEDIATE+=bd82x6x_add_me
+
+ramstage-y += pch.c
+ramstage-y += azalia.c
+ramstage-y += lpc.c
+ramstage-y += pci.c
+ramstage-y += pcie.c
+ramstage-y += sata.c
+ramstage-y += usb_ehci.c
+ramstage-y += me.c
+ramstage-y += me_8.x.c
+ramstage-y += smbus.c
+ramstage-y += thermal.c
+
+ramstage-y += me_status.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
+
+ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += spi.c
+ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
+smm-$(CONFIG_USBDEBUG) += usb_debug.c
+
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) +=smihandler.c me.c me_8.x.c finalize.c pch.c
+
+romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
+romstage-$(CONFIG_USBDEBUG) += usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+smm-$(CONFIG_USBDEBUG) += usb_debug.c
+romstage-y += reset.c
+
+bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL)
+ printf " DD Adding Intel Firmware Descriptor\n"
+ dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
+ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ printf " IFDTOOL me.bin -> coreboot.pre\n"
+ $(objutil)/ifdtool/ifdtool \
+ -i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
+ $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
+ printf " IFDTOOL Locking Management Engine\n"
+ $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+else
+ printf " IFDTOOL Unlocking Management Engine\n"
+ $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
+
+PHONY += bd82x6x_add_me
diff --git a/src/southbridge/intel/ibexpeak/acpi/audio.asl b/src/southbridge/intel/ibexpeak/acpi/audio.asl
new file mode 100644
index 0000000..a455328
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/audio.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel PCH HDA */
+
+// Intel High Definition Audio (Azalia) 0:1b.0
+
+Device (HDEF)
+{
+ Name (_ADR, 0x001b0000)
+
+ // Power Resources for Wake
+ Name (_PRW, Package(){
+ 13, // Bit 13 of GPE
+ 4 // Can wake from S4 state.
+ })
+}
+
diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
new file mode 100644
index 0000000..99edc31
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
@@ -0,0 +1,301 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Global Variables */
+
+Name(\PICM, 0) // IOAPIC/8259
+Name(\DSEN, 1) // Display Output Switching Enable
+
+/* Global ACPI memory region. This region is used for passing information
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we have to fix it up in coreboot's ACPI creation phase.
+ */
+
+
+OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ Offset (0x00),
+ OSYS, 16, // 0x00 - Operating System
+ SMIF, 8, // 0x02 - SMI function
+ PRM0, 8, // 0x03 - SMI function parameter
+ PRM1, 8, // 0x04 - SMI function parameter
+ SCIF, 8, // 0x05 - SCI function
+ PRM2, 8, // 0x06 - SCI function parameter
+ PRM3, 8, // 0x07 - SCI function parameter
+ LCKF, 8, // 0x08 - Global Lock function for EC
+ PRM4, 8, // 0x09 - Lock function parameter
+ PRM5, 8, // 0x0a - Lock function parameter
+ P80D, 32, // 0x0b - Debug port (IO 0x80) value
+ LIDS, 8, // 0x0f - LID state (open = 1)
+ PWRS, 8, // 0x10 - Power State (AC = 1)
+ /* Thermal policy */
+ Offset (0x11),
+ TLVL, 8, // 0x11 - Throttle Level Limit
+ FLVL, 8, // 0x12 - Current FAN Level
+ TCRT, 8, // 0x13 - Critical Threshold
+ TPSV, 8, // 0x14 - Passive Threshold
+ TMAX, 8, // 0x15 - CPU Tj_max
+ F0OF, 8, // 0x16 - FAN 0 OFF Threshold
+ F0ON, 8, // 0x17 - FAN 0 ON Threshold
+ F0PW, 8, // 0x18 - FAN 0 PWM value
+ F1OF, 8, // 0x19 - FAN 1 OFF Threshold
+ F1ON, 8, // 0x1a - FAN 1 ON Threshold
+ F1PW, 8, // 0x1b - FAN 1 PWM value
+ F2OF, 8, // 0x1c - FAN 2 OFF Threshold
+ F2ON, 8, // 0x1d - FAN 2 ON Threshold
+ F2PW, 8, // 0x1e - FAN 2 PWM value
+ F3OF, 8, // 0x1f - FAN 3 OFF Threshold
+ F3ON, 8, // 0x20 - FAN 3 ON Threshold
+ F3PW, 8, // 0x21 - FAN 3 PWM value
+ F4OF, 8, // 0x22 - FAN 4 OFF Threshold
+ F4ON, 8, // 0x23 - FAN 4 ON Threshold
+ F4PW, 8, // 0x24 - FAN 4 PWM value
+ TMPS, 8, // 0x25 - Temperature Sensor ID
+ /* Processor Identification */
+ Offset (0x28),
+ APIC, 8, // 0x28 - APIC Enabled by coreboot
+ MPEN, 8, // 0x29 - Multi Processor Enable
+ PCP0, 8, // 0x2a - PDC CPU/CORE 0
+ PCP1, 8, // 0x2b - PDC CPU/CORE 1
+ PPCM, 8, // 0x2c - Max. PPC state
+ PCNT, 8, // 0x2d - Processor count
+ /* Super I/O & CMOS config */
+ Offset (0x32),
+ NATP, 8, // 0x32 -
+ S5U0, 8, // 0x33 - Enable USB0 in S5
+ S5U1, 8, // 0x34 - Enable USB1 in S5
+ S3U0, 8, // 0x35 - Enable USB0 in S3
+ S3U1, 8, // 0x36 - Enable USB1 in S3
+ S33G, 8, // 0x37 - Enable 3G in S3
+ CMEM, 32, // 0x38 - CBMEM TOC
+ /* Integrated Graphics Device */
+ Offset (0x3c),
+ IGDS, 8, // 0x3c - IGD state (primary = 1)
+ TLST, 8, // 0x3d - Display Toggle List pointer
+ CADL, 8, // 0x3e - Currently Attached Devices List
+ PADL, 8, // 0x3f - Previously Attached Devices List
+ CSTE, 16, // 0x40 - Current display state
+ NSTE, 16, // 0x42 - Next display state
+ SSTE, 16, // 0x44 - Set display state
+ Offset (0x46),
+ NDID, 8, // 0x46 - Number of Device IDs
+ DID1, 32, // 0x47 - Device ID 1
+ DID2, 32, // 0x4b - Device ID 2
+ DID3, 32, // 0x4f - Device ID 3
+ DID4, 32, // 0x53 - Device ID 4
+ DID5, 32, // 0x57 - Device ID 5
+ /* Backlight Control */
+ Offset (0x64),
+ BLCS, 8, // 0x64 - Backlight control possible?
+ BRTL, 8, // 0x65 - Brightness Level
+ ODDS, 8, // 0x66
+ /* Ambient Light Sensors */
+ Offset (0x6e),
+ ALSE, 8, // 0x6e - ALS enable
+ ALAF, 8, // 0x6f - Ambient light adjustment factor
+ LLOW, 8, // 0x70 - LUX Low
+ LHIH, 8, // 0x71 - LUX High
+ /* EMA */
+ Offset (0x78),
+ EMAE, 8, // 0x78 - EMA enable
+ EMAP, 16, // 0x79 - EMA pointer
+ EMAL, 16, // 0x7b - EMA length
+ /* MEF */
+ Offset (0x82),
+ MEFE, 8, // 0x82 - MEF enable
+ /* TPM support */
+ Offset (0x8c),
+ TPMP, 8, // 0x8c - TPM
+ TPME, 8, // 0x8d - TPM enable
+ /* SATA */
+ Offset (0x96),
+ GTF0, 56, // 0x96 - GTF task file buffer for port 0
+ GTF1, 56, // 0x9d - GTF task file buffer for port 1
+ GTF2, 56, // 0xa4 - GTF task file buffer for port 2
+ IDEM, 8, // 0xab - IDE mode (compatible / enhanced)
+ IDET, 8, // 0xac - IDE
+ /* XHCI */
+ Offset (0xb2),
+ XHCI, 8,
+ /* IGD OpRegion */
+ Offset (0xb4),
+ ASLB, 32, // 0xb4 - IGD OpRegion Base Address
+ IBTT, 8, // 0xb8 - IGD boot panel device
+ IPAT, 8, // 0xb9 - IGD panel type cmos option
+ ITVF, 8, // 0xba - IGD TV format cmos option
+ ITVM, 8, // 0xbb - IGD TV minor format option
+ IPSC, 8, // 0xbc - IGD panel scaling
+ IBLC, 8, // 0xbd - IGD BLC config
+ IBIA, 8, // 0xbe - IGD BIA config
+ ISSC, 8, // 0xbf - IGD SSC config
+ I409, 8, // 0xc0 - IGD 0409 modified settings
+ I509, 8, // 0xc1 - IGD 0509 modified settings
+ I609, 8, // 0xc2 - IGD 0609 modified settings
+ I709, 8, // 0xc3 - IGD 0709 modified settings
+ IDMM, 8, // 0xc4 - IGD Power conservation feature
+ IDMS, 8, // 0xc5 - IGD DVMT memory size
+ IF1E, 8, // 0xc6 - IGD function 1 enable
+ HVCO, 8, // 0xc7 - IGD HPLL VCO
+ NXD1, 32, // 0xc8 - IGD _DGS next DID1
+ NXD2, 32, // 0xcc - IGD _DGS next DID2
+ NXD3, 32, // 0xd0 - IGD _DGS next DID3
+ NXD4, 32, // 0xd4 - IGD _DGS next DID4
+ NXD5, 32, // 0xd8 - IGD _DGS next DID5
+ NXD6, 32, // 0xdc - IGD _DGS next DID6
+ NXD7, 32, // 0xe0 - IGD _DGS next DID7
+ NXD8, 32, // 0xe4 - IGD _DGS next DID8
+
+ ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
+ PAVP, 8, // 0xe9 - IGD PAVP data
+ Offset (0xeb),
+ OSCC, 8, // 0xeb - PCIe OSC control
+ NPCE, 8, // 0xec - native pcie support
+ PLFL, 8, // 0xed - platform flavor
+ BREV, 8, // 0xee - board revision
+ DPBM, 8, // 0xef - digital port b mode
+ DPCM, 8, // 0xf0 - digital port c mode
+ DPDM, 8, // 0xf1 - digital port d mode
+ ALFP, 8, // 0xf2 - active lfp
+ IMON, 8, // 0xf3 - current graphics turbo imon value
+ MMIO, 8, // 0xf4 - 64bit mmio support
+
+ /* ChromeOS specific */
+ Offset (0x100),
+ #include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}
+
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+ Store (One, \S3U0)
+ Store (One, \S3U1)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+ Store (Zero, \S3U0)
+ Store (Zero, \S3U1)
+}
+
+/* Set flag to enable USB charging in S5 */
+Method (S5UE)
+{
+ Store (One, \S5U0)
+ Store (One, \S5U1)
+}
+
+/* Set flag to disable USB charging in S5 */
+Method (S5UD)
+{
+ Store (Zero, \S5U0)
+ Store (Zero, \S5U1)
+}
+
+/* Set flag to enable 3G module in S3 */
+Method (S3GE)
+{
+ Store (One, \S33G)
+}
+
+/* Set flag to disable 3G module in S3 */
+Method (S3GD)
+{
+ Store (Zero, \S33G)
+}
+
+/* Set XHCI Mode enable */
+Method (XHCE)
+{
+ Store (One, \XHCI)
+}
+
+/* Set XHCI Mode disable */
+Method (XHCD)
+{
+ Store (Zero, \XHCI)
+}
+External (\_TZ.THRM)
+External (\_TZ.SKIN)
+
+Method (TZUP)
+{
+ /* Update Primary Thermal Zone */
+ If (CondRefOf (\_TZ.THRM, Local0)) {
+ Notify (\_TZ.THRM, 0x81)
+ }
+
+ /* Update Secondary Thermal Zone */
+ If (CondRefOf (\_TZ.SKIN, Local0)) {
+ Notify (\_TZ.SKIN, 0x81)
+ }
+}
+
+/* Update Fan 0 thresholds */
+Method (F0UT, 2)
+{
+ Store (Arg0, \F0OF)
+ Store (Arg1, \F0ON)
+ TZUP ()
+}
+
+/* Update Fan 1 thresholds */
+Method (F1UT, 2)
+{
+ Store (Arg0, \F1OF)
+ Store (Arg1, \F1ON)
+ TZUP ()
+}
+
+/* Update Fan 2 thresholds */
+Method (F2UT, 2)
+{
+ Store (Arg0, \F2OF)
+ Store (Arg1, \F2ON)
+ TZUP ()
+}
+
+/* Update Fan 3 thresholds */
+Method (F3UT, 2)
+{
+ Store (Arg0, \F3OF)
+ Store (Arg1, \F3ON)
+ TZUP ()
+}
+
+/* Update Fan 4 thresholds */
+Method (F4UT, 2)
+{
+ Store (Arg0, \F4OF)
+ Store (Arg1, \F4ON)
+ TZUP ()
+}
+
+/* Update Temperature Sensor ID */
+Method (TMPU, 1)
+{
+ Store (Arg0, \TMPS)
+ TZUP ()
+}
diff --git a/src/southbridge/intel/ibexpeak/acpi/irqlinks.asl b/src/southbridge/intel/ibexpeak/acpi/irqlinks.asl
new file mode 100644
index 0000000..5fcee45
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/irqlinks.asl
@@ -0,0 +1,493 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LNKA)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 1)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTA)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLA, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLA, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTA
+ ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+ Return (RTLA)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTA)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTA, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
+Device (LNKB)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 2)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTB)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLB, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLB, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTB
+ ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+ Return (RTLB)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTB)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTB, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
+Device (LNKC)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 3)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTC)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLC, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLC, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTC
+ ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+ Return (RTLC)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTC)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTC, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
+Device (LNKD)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 4)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTD)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLD, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLD, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTD
+ ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+ Return (RTLD)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTD)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTD, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
+Device (LNKE)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 5)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTE)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLE, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLE, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTE
+ ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+ Return (RTLE)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTE)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTE, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
+Device (LNKF)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 6)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTF)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLF, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLF, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTF
+ ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+ Return (RTLF)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTF)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTF, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
+Device (LNKG)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 7)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTG)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLG, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLG, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTG
+ ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+ Return (RTLG)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTG)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTG, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
+Device (LNKH)
+{
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 8)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTH)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLH, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLH, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTH
+ ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+ Return (RTLH)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTH)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTH, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+}
+
diff --git a/src/southbridge/intel/ibexpeak/acpi/lpc.asl b/src/southbridge/intel/ibexpeak/acpi/lpc.asl
new file mode 100644
index 0000000..cc59850
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/lpc.asl
@@ -0,0 +1,248 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel LPC Bus Device - 0:1f.0
+
+Device (LPCB)
+{
+ Name(_ADR, 0x001f0000)
+
+ OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+ Field (LPC0, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PMBS, 16, // PMBASE
+ Offset (0x60), // Interrupt Routing Registers
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ Offset (0x68),
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+
+ Offset (0x80), // IO Decode Ranges
+ IOD0, 8,
+ IOD1, 8,
+
+ Offset (0xb8), // GPIO Routing Control
+ GR00, 2,
+ GR01, 2,
+ GR02, 2,
+ GR03, 2,
+ GR04, 2,
+ GR05, 2,
+ GR06, 2,
+ GR07, 2,
+ GR08, 2,
+ GR09, 2,
+ GR10, 2,
+ GR11, 2,
+ GR12, 2,
+ GR13, 2,
+ GR14, 2,
+ GR15, 2,
+
+ Offset (0xf0), // RCBA
+ RCEN, 1,
+ , 13,
+ RCBA, 18,
+ }
+
+ #include "irqlinks.asl"
+
+ #include "acpi/ec.asl"
+
+ Device (DMAC) // DMA Controller
+ {
+ Name(_HID, EISAID("PNP0200"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x00, 0x00, 0x01, 0x20)
+ IO (Decode16, 0x81, 0x81, 0x01, 0x11)
+ IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
+ IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
+ })
+ }
+
+ Device (FWH) // Firmware Hub
+ {
+ Name (_HID, EISAID("INT0800"))
+ Name (_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+ })
+ }
+
+ Device (HPET)
+ {
+ Name (_HID, EISAID("PNP0103"))
+ Name (_CID, 0x010CD041)
+
+ Name(BUF0, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
+ })
+
+ Method (_STA, 0) // Device Status
+ {
+ If (HPTE) {
+ // Note: Ancient versions of Windows don't want
+ // to see the HPET in order to work right
+ If (LGreaterEqual(OSYS, 2001)) {
+ Return (0xf) // Enable and show device
+ } Else {
+ Return (0xb) // Enable and don't show device
+ }
+ }
+
+ Return (0x0) // Not enabled, don't show.
+ }
+
+ Method (_CRS, 0, Serialized) // Current resources
+ {
+ If (HPTE) {
+ CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
+ If (Lequal(HPAS, 1)) {
+ Store(0xfed01000, HPT0)
+ }
+
+ If (Lequal(HPAS, 2)) {
+ Store(0xfed02000, HPT0)
+ }
+
+ If (Lequal(HPAS, 3)) {
+ Store(0xfed03000, HPT0)
+ }
+ }
+
+ Return (BUF0)
+ }
+ }
+
+ Device(PIC) // 8259 Interrupt Controller
+ {
+ Name(_HID,EISAID("PNP0000"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x20, 0x20, 0x01, 0x02)
+ IO (Decode16, 0x24, 0x24, 0x01, 0x02)
+ IO (Decode16, 0x28, 0x28, 0x01, 0x02)
+ IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
+ IO (Decode16, 0x30, 0x30, 0x01, 0x02)
+ IO (Decode16, 0x34, 0x34, 0x01, 0x02)
+ IO (Decode16, 0x38, 0x38, 0x01, 0x02)
+ IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
+ IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
+ IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
+ IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
+ IO (Decode16, 0xac, 0xac, 0x01, 0x02)
+ IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
+ IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
+ IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
+ IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
+ IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+ IRQNoFlags () { 2 }
+ })
+ }
+
+ Device(MATH) // FPU
+ {
+ Name (_HID, EISAID("PNP0C04"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
+ IRQNoFlags() { 13 }
+ })
+ }
+
+ Device(LDRC) // LPC device: Resource consumption
+ {
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, 2)
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
+ IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+ //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
+ IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI
+ IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO
+ })
+ }
+
+ Device (RTC) // Real Time Clock
+ {
+ Name (_HID, EISAID("PNP0B00"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x70, 0x70, 1, 8)
+// Disable as Windows doesn't like it, and systems don't seem to use it.
+// IRQNoFlags() { 8 }
+ })
+ }
+
+ Device (TIMR) // Intel 8254 timer
+ {
+ Name(_HID, EISAID("PNP0100"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags() {0}
+ })
+ }
+
+ #include "acpi/superio.asl"
+
+#ifdef ENABLE_TPM
+ Device (TPM) // Trusted Platform Module
+ {
+ Name(_HID, EISAID("IFX0102"))
+ Name(_CID, 0x310cd041)
+ Name(_UID, 1)
+
+ Method(_STA, 0)
+ {
+ If (TPMP) {
+ Return (0xf)
+ }
+ Return (0x0)
+ }
+
+ Name(_CRS, ResourceTemplate() {
+ IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
+ IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
+ IRQ (Edge, Activehigh, Exclusive) { 6 }
+ })
+ }
+#endif
+}
diff --git a/src/southbridge/intel/ibexpeak/acpi/pch.asl b/src/southbridge/intel/ibexpeak/acpi/pch.asl
new file mode 100644
index 0000000..2f75fdc
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/pch.asl
@@ -0,0 +1,280 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel Cougar Point PCH support */
+
+Scope(\)
+{
+ // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+
+ OperationRegion(IO_T, SystemIO, 0x800, 0x10)
+ Field(IO_T, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x8),
+ TRP0, 8 // IO-Trap at 0x808
+ }
+
+ // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
+ OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
+ Field(PMIO, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x20), // GPE0_STS
+ , 16,
+ GS00, 1, // GPIO00 SCI/Wake Status
+ GS01, 1, // GPIO01 SCI/Wake Status
+ GS02, 1, // GPIO02 SCI/Wake Status
+ GS03, 1, // GPIO03 SCI/Wake Status
+ GS04, 1, // GPIO04 SCI/Wake Status
+ GS05, 1, // GPIO05 SCI/Wake Status
+ GS06, 1, // GPIO06 SCI/Wake Status
+ GS07, 1, // GPIO07 SCI/Wake Status
+ GS08, 1, // GPIO08 SCI/Wake Status
+ GS09, 1, // GPIO09 SCI/Wake Status
+ GS10, 1, // GPIO10 SCI/Wake Status
+ GS11, 1, // GPIO11 SCI/Wake Status
+ GS12, 1, // GPIO12 SCI/Wake Status
+ GS13, 1, // GPIO13 SCI/Wake Status
+ GS14, 1, // GPIO14 SCI/Wake Status
+ GS15, 1, // GPIO15 SCI/Wake Status
+ Offset(0x28), // GPE0_EN
+ , 16,
+ GE00, 1, // GPIO00 SCI/Wake Enable
+ GE01, 1, // GPIO01 SCI/Wake Enable
+ GE02, 1, // GPIO02 SCI/Wake Enable
+ GE03, 1, // GPIO03 SCI/Wake Enable
+ GE04, 1, // GPIO04 SCI/Wake Enable
+ GE05, 1, // GPIO05 SCI/Wake Enable
+ GE06, 1, // GPIO06 SCI/Wake Enable
+ GE07, 1, // GPIO07 SCI/Wake Enable
+ GE08, 1, // GPIO08 SCI/Wake Enable
+ GE09, 1, // GPIO09 SCI/Wake Enable
+ GE10, 1, // GPIO10 SCI/Wake Enable
+ GE11, 1, // GPIO11 SCI/Wake Enable
+ GE12, 1, // GPIO12 SCI/Wake Enable
+ GE13, 1, // GPIO13 SCI/Wake Enable
+ GE14, 1, // GPIO14 SCI/Wake Enable
+ GE15, 1, // GPIO15 SCI/Wake Enable
+ Offset(0x42), // General Purpose Control
+ , 1, // skip 1 bit
+ GPEC, 1, // SWGPE_CTRL
+ }
+
+ // GPIO IO mapped registers (0x1f.0 reg 0x48.l)
+ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
+ Field(GPIO, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x00), // GPIO Use Select
+ GU00, 8,
+ GU01, 8,
+ GU02, 8,
+ GU03, 8,
+ Offset(0x04), // GPIO IO Select
+ GIO0, 8,
+ GIO1, 8,
+ GIO2, 8,
+ GIO3, 8,
+ Offset(0x0c), // GPIO Level
+ GL00, 1,
+ GP01, 1,
+ GP02, 1,
+ GP0e, 1,
+ GP04, 1,
+ GP05, 1,
+ GP06, 1,
+ GP07, 1,
+ GP08, 1,
+ GP09, 1,
+ GP10, 1,
+ GP11, 1,
+ GP12, 1,
+ GP13, 1,
+ GP14, 1,
+ GP15, 1,
+ GP16, 1,
+ GP17, 1,
+ GP18, 1,
+ GP19, 1,
+ GP20, 1,
+ GP21, 1,
+ GP22, 1,
+ GP23, 1,
+ GP24, 1,
+ GP25, 1,
+ GP26, 1,
+ GP27, 1,
+ GP28, 1,
+ GP29, 1,
+ GP30, 1,
+ GP31, 1,
+ Offset(0x18), // GPIO Blink
+ GB00, 8,
+ GB01, 8,
+ GB02, 8,
+ GB03, 8,
+ Offset(0x2c), // GPIO Invert
+ GIV0, 8,
+ GIV1, 8,
+ GIV2, 8,
+ GIV3, 8,
+ Offset(0x30), // GPIO Use Select 2
+ GU04, 8,
+ GU05, 8,
+ GU06, 8,
+ GU07, 8,
+ Offset(0x34), // GPIO IO Select 2
+ GIO4, 8,
+ GIO5, 8,
+ GIO6, 8,
+ GIO7, 8,
+ Offset(0x38), // GPIO Level 2
+ GP32, 1,
+ GP33, 1,
+ GP34, 1,
+ GP35, 1,
+ GP36, 1,
+ GP37, 1,
+ GP38, 1,
+ GP39, 1,
+ GP40, 1,
+ GP41, 1,
+ GP42, 1,
+ GP43, 1,
+ GP44, 1,
+ GP45, 1,
+ GP46, 1,
+ GP47, 1,
+ GP48, 1,
+ GP49, 1,
+ GP50, 1,
+ GP51, 1,
+ GP52, 1,
+ GP53, 1,
+ GP54, 1,
+ GP55, 1,
+ GP56, 1,
+ GP57, 1,
+ GP58, 1,
+ GP59, 1,
+ GP60, 1,
+ GP61, 1,
+ GP62, 1,
+ GP63, 1,
+ Offset(0x40), // GPIO Use Select 3
+ GU08, 8,
+ GU09, 4,
+ Offset(0x44), // GPIO IO Select 3
+ GIO8, 8,
+ GIO9, 4,
+ Offset(0x48), // GPIO Level 3
+ GP64, 1,
+ GP65, 1,
+ GP66, 1,
+ GP67, 1,
+ GP68, 1,
+ GP69, 1,
+ GP70, 1,
+ GP71, 1,
+ GP72, 1,
+ GP73, 1,
+ GP74, 1,
+ GP75, 1,
+ }
+
+
+ // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
+ OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
+ Field(RCRB, DWordAcc, Lock, Preserve)
+ {
+ Offset(0x0000), // Backbone
+ Offset(0x1000), // Chipset
+ Offset(0x3000), // Legacy Configuration Registers
+ Offset(0x3404), // High Performance Timer Configuration
+ HPAS, 2, // Address Select
+ , 5,
+ HPTE, 1, // Address Enable
+ Offset(0x3418), // FD (Function Disable)
+ , 1, // Reserved
+ PCID, 1, // PCI bridge disable
+ SA1D, 1, // SATA1 disable
+ SMBD, 1, // SMBUS disable
+ HDAD, 1, // Azalia disable
+ , 8, // Reserved
+ EH2D, 1, // EHCI #2 disable
+ LPBD, 1, // LPC bridge disable
+ EH1D, 1, // EHCI #1 disable
+ RP1D, 1, // Root Port 1 disable
+ RP2D, 1, // Root Port 2 disable
+ RP3D, 1, // Root Port 3 disable
+ RP4D, 1, // Root Port 4 disable
+ RP5D, 1, // Root Port 5 disable
+ RP6D, 1, // Root Port 6 disable
+ RP7D, 1, // Root Port 7 disable
+ RP8D, 1, // Root Port 8 disable
+ TTRD, 1, // Thermal sensor registers disable
+ SA2D, 1, // SATA2 disable
+ Offset(0x3428), // FD2 (Function Disable 2)
+ BDFD, 1, // Display BDF
+ ME1D, 1, // ME Interface 1 disable
+ ME2D, 1, // ME Interface 2 disable
+ IDRD, 1, // IDE redirect disable
+ KTCT, 1, // Keyboard Text redirect disable
+ }
+}
+
+// High Definition Audio (Azalia) 0:1b.0
+#include "audio.asl"
+
+// PCI Express Ports 0:1c.x
+#include "pcie.asl"
+
+// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0
+#include "usb.asl"
+
+// LPC Bridge 0:1f.0
+#include "lpc.asl"
+
+// SATA 0:1f.2, 0:1f.5
+#include "sata.asl"
+
+// SMBus 0:1f.3
+#include "smbus.asl"
+
+Method (_OSC, 4)
+{
+ /* Check for XHCI */
+ If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71")))
+ {
+ Return (^XHC.POSC(Arg1, Arg2, Arg3))
+ }
+
+ /* Check for PCIe */
+ If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ }
+
+ /* Else Return Unrecognized UUID */
+ CreateDWordField (Arg3, 0, CDW1)
+ Or (CDW1, 4, CDW1)
+ Return (Arg3)
+
+}
diff --git a/src/southbridge/intel/ibexpeak/acpi/pcie.asl b/src/southbridge/intel/ibexpeak/acpi/pcie.asl
new file mode 100644
index 0000000..934cf78
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/pcie.asl
@@ -0,0 +1,218 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel 6/7 Series PCH PCIe support */
+
+// PCI Express Ports
+
+Method (IRQM, 1, Serialized) {
+
+ /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
+ Name (IQAA, Package() {
+ Package() { 0x0000ffff, 0, 0, 16 },
+ Package() { 0x0000ffff, 1, 0, 17 },
+ Package() { 0x0000ffff, 2, 0, 18 },
+ Package() { 0x0000ffff, 3, 0, 19 } })
+ Name (IQAP, Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
+
+ /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
+ Name (IQBA, Package() {
+ Package() { 0x0000ffff, 0, 0, 17 },
+ Package() { 0x0000ffff, 1, 0, 18 },
+ Package() { 0x0000ffff, 2, 0, 19 },
+ Package() { 0x0000ffff, 3, 0, 16 } })
+ Name (IQBP, Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
+
+ /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
+ Name (IQCA, Package() {
+ Package() { 0x0000ffff, 0, 0, 18 },
+ Package() { 0x0000ffff, 1, 0, 19 },
+ Package() { 0x0000ffff, 2, 0, 16 },
+ Package() { 0x0000ffff, 3, 0, 17 } })
+ Name (IQCP, Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
+
+ /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
+ Name (IQDA, Package() {
+ Package() { 0x0000ffff, 0, 0, 19 },
+ Package() { 0x0000ffff, 1, 0, 16 },
+ Package() { 0x0000ffff, 2, 0, 17 },
+ Package() { 0x0000ffff, 3, 0, 18 } })
+ Name (IQDP, Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
+
+ Switch (ToInteger (Arg0)) {
+ /* PCIe Root Port 1 and 5 */
+ Case (Package() { 1, 5 }) {
+ If (PICM) {
+ Return (IQAA)
+ } Else {
+ Return (IQAP)
+ }
+ }
+
+ /* PCIe Root Port 2 and 6 */
+ Case (Package() { 2, 6 }) {
+ If (PICM) {
+ Return (IQBA)
+ } Else {
+ Return (IQBP)
+ }
+ }
+
+ /* PCIe Root Port 3 and 7 */
+ Case (Package() { 3, 7 }) {
+ If (PICM) {
+ Return (IQCA)
+ } Else {
+ Return (IQCP)
+ }
+ }
+
+ /* PCIe Root Port 4 and 8 */
+ Case (Package() { 4, 8 }) {
+ If (PICM) {
+ Return (IQDA)
+ } Else {
+ Return (IQDP)
+ }
+ }
+
+ Default {
+ If (PICM) {
+ Return (IQDA)
+ } Else {
+ Return (IQDP)
+ }
+ }
+ }
+}
+
+Device (RP01)
+{
+ Name (_ADR, 0x001c0000)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP02)
+{
+ Name (_ADR, 0x001c0001)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP03)
+{
+ Name (_ADR, 0x001c0002)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP04)
+{
+ Name (_ADR, 0x001c0003)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP05)
+{
+ Name (_ADR, 0x001c0004)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP06)
+{
+ Name (_ADR, 0x001c0005)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP07)
+{
+ Name (_ADR, 0x001c0006)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP08)
+{
+ Name (_ADR, 0x001c0007)
+
+ #include "pcie_port.asl"
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
diff --git a/src/southbridge/intel/ibexpeak/acpi/pcie_port.asl b/src/southbridge/intel/ibexpeak/acpi/pcie_port.asl
new file mode 100644
index 0000000..fedd9c9
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/pcie_port.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Included in each PCIe Root Port device */
+
+OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
+Field (RPCS, AnyAcc, NoLock, Preserve)
+{
+ Offset (0x4c), // Link Capabilities
+ , 24,
+ RPPN, 8, // Root Port Number
+}
diff --git a/src/southbridge/intel/ibexpeak/acpi/sata.asl b/src/southbridge/intel/ibexpeak/acpi/sata.asl
new file mode 100644
index 0000000..e0c336a
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/sata.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel SATA Controller 0:1f.2
+
+// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily
+// pluggable
+
+Device (SATA)
+{
+ Name (_ADR, 0x001f0002)
+
+ Device (PRID)
+ {
+ Name (_ADR, 0)
+
+ // Get Timing Mode
+ Method (_GTM)
+ {
+ Name(PBUF, Buffer(20) {
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ CreateDwordField (PBUF, 0, PIO0)
+ CreateDwordField (PBUF, 4, DMA0)
+ CreateDwordField (PBUF, 8, PIO1)
+ CreateDwordField (PBUF, 12, DMA1)
+ CreateDwordField (PBUF, 16, FLAG)
+
+ // TODO fill return structure
+
+ Return (PBUF)
+ }
+
+ // Set Timing Mode
+ Method (_STM, 3)
+ {
+ CreateDwordField (Arg0, 0, PIO0)
+ CreateDwordField (Arg0, 4, DMA0)
+ CreateDwordField (Arg0, 8, PIO1)
+ CreateDwordField (Arg0, 12, DMA1)
+ CreateDwordField (Arg0, 16, FLAG)
+
+ // TODO: Do the deed
+ }
+
+ Device (DSK0)
+ {
+ Name (_ADR, 0)
+ // TODO: _RMV ?
+ // TODO: _GTF ?
+ }
+
+ Device (DSK1)
+ {
+ Name (_ADR, 1)
+
+ // TODO: _RMV ?
+ // TODO: _GTF ?
+ }
+
+ }
+}
+
diff --git a/src/southbridge/intel/ibexpeak/acpi/sleepstates.asl b/src/southbridge/intel/ibexpeak/acpi/sleepstates.asl
new file mode 100644
index 0000000..06bfcb6
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/sleepstates.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name(\_S0, Package(){0x0,0x0,0x0,0x0})
+// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
+Name(\_S3, Package(){0x5,0x5,0x0,0x0})
+Name(\_S4, Package(){0x6,0x6,0x0,0x0})
+Name(\_S5, Package(){0x7,0x7,0x0,0x0})
+
diff --git a/src/southbridge/intel/ibexpeak/acpi/smbus.asl b/src/southbridge/intel/ibexpeak/acpi/smbus.asl
new file mode 100644
index 0000000..4409308
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/smbus.asl
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel SMBus Controller 0:1f.3
+
+Device (SBUS)
+{
+ Name (_ADR, 0x001f0003)
+
+#ifdef ENABLE_SMBUS_METHODS
+ OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
+ Field(SMBP, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x40),
+ , 2,
+ I2CE, 1
+ }
+
+ OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20)
+ Field (SMBI, ByteAcc, NoLock, Preserve)
+ {
+ HSTS, 8, // Host Status
+ , 8,
+ HCNT, 8, // Host Control
+ HCMD, 8, // Host Command
+ TXSA, 8, // Transmit Slave Address
+ DAT0, 8, // Host Data 0
+ DAT1, 8, // Host Data 1
+ HBDB, 8, // Host Block Data Byte
+ PECK, 8, // Packet Error Check
+ RXSA, 8, // Receive Slave Address
+ RXDA, 16, // Receive Slave Data
+ AUXS, 8, // Auxiliary Status
+ AUXC, 8, // Auxiliary Control
+ SLPC, 8, // SMLink Pin Control
+ SBPC, 8, // SMBus Pin Control
+ SSTS, 8, // Slave Status
+ SCMD, 8, // Slave Command
+ NADR, 8, // Notify Device Address
+ NDLB, 8, // Notify Data Low Byte
+ NDLH, 8, // Notify Data High Byte
+ }
+
+ // Kill all SMBus communication
+ Method (KILL, 0, Serialized)
+ {
+ Or (HCNT, 0x02, HCNT) // Send Kill
+ Or (HSTS, 0xff, HSTS) // Clean Status
+ }
+
+ // Check if last operation completed
+ // return Failure = 0, Success = 1
+ Method (CMPL, 0, Serialized)
+ {
+ Store (4000, Local0) // Timeout 200ms in 50us steps
+ While (Local0) {
+ If (And(HSTS, 0x02)) { // Completion Status?
+ Return (1) // Operation Completed
+ } Else {
+ Stall (50)
+ Decrement (Local0)
+ If (LEqual(Local0, 0)) {
+ KILL()
+ }
+ }
+ }
+
+ Return (0) // Failure
+ }
+
+
+ // Wait for SMBus to become ready
+ Method (SRDY, 0, Serialized)
+ {
+ Store (200, Local0) // Timeout 200ms
+ While (Local0) {
+ If (And(HSTS, 0x40)) { // IN_USE?
+ Sleep(1) // Wait 1ms
+ Decrement(Local0) // timeout--
+ If (LEqual(Local0, 0)) {
+ Return (1)
+ }
+ } Else {
+ Store (0, Local0) // We're ready
+ }
+ }
+
+ Store (4000, Local0) // Timeout 200ms (50us * 4000)
+ While (Local0) {
+ If (And (HSTS, 0x01)) { // Host Busy?
+ Stall(50) // Wait 50us
+ Decrement(Local0) // timeout--
+ If (LEqual(Local0, 0)) {
+ KILL()
+ }
+ } Else {
+ Return (0) // Success
+ }
+ }
+
+ Return (1) // Failure
+ }
+
+ // SMBus Send Byte
+ // Arg0: Address
+ // Arg1: Data
+ // Return: 1 = Success, 0=Failure
+
+ Method (SSXB, 2, Serialized)
+ {
+
+ // Is the SMBus Controller Ready?
+ If (SRDY()) {
+ Return (0)
+ }
+
+ // Send Byte
+ Store (0, I2CE) // SMBus Enable
+ Store (0xbf, HSTS)
+ Store (Arg0, TXSA) // Write Address
+ Store (Arg1, HCMD) // Write Data
+
+ Store (0x48, HCNT) // Start + Byte Data Protocol
+
+ If (CMPL()) {
+ Or (HSTS, 0xff, HSTS) // Clean up
+ Return (1) // Success
+ }
+
+ Return (0)
+ }
+
+
+ // SMBus Receive Byte
+ // Arg0: Address
+ // Return: 0xffff = Failure, Data (8bit) = Success
+
+ Method (SRXB, 2, Serialized)
+ {
+
+ // Is the SMBus Controller Ready?
+ If (SRDY()) {
+ Return (0xffff)
+ }
+
+ // Receive Byte
+ Store (0, I2CE) // SMBus Enable
+ Store (0xbf, HSTS)
+ Store (Or (Arg0, 1), TXSA) // Write Address
+
+ Store (0x44, HCNT) // Start
+
+ If (CMPL()) {
+ Or (HSTS, 0xff, HSTS) // Clean up
+ Return (DAT0) // Success
+ }
+
+ Return (0xffff)
+ }
+
+
+ // SMBus Write Byte
+ // Arg0: Address
+ // Arg1: Command
+ // Arg2: Data
+ // Return: 1 = Success, 0=Failure
+
+ Method (SWRB, 3, Serialized)
+ {
+
+ // Is the SMBus Controller Ready?
+ If (SRDY()) {
+ Return (0)
+ }
+
+ // Send Byte
+ Store (0, I2CE) // SMBus Enable
+ Store (0xbf, HSTS)
+ Store (Arg0, TXSA) // Write Address
+ Store (Arg1, HCMD) // Write Command
+ Store (Arg2, DAT0) // Write Data
+
+ Store (0x48, HCNT) // Start + Byte Protocol
+
+ If (CMPL()) {
+ Or (HSTS, 0xff, HSTS) // Clean up
+ Return (1) // Success
+ }
+
+ Return (0)
+ }
+
+
+ // SMBus Read Byte
+ // Arg0: Address
+ // Arg1: Command
+ // Return: 0xffff = Failure, Data (8bit) = Success
+
+ Method (SRDB, 2, Serialized)
+ {
+
+ // Is the SMBus Controller Ready?
+ If (SRDY()) {
+ Return (0xffff)
+ }
+
+ // Receive Byte
+ Store (0, I2CE) // SMBus Enable
+ Store (0xbf, HSTS)
+ Store (Or (Arg0, 1), TXSA) // Write Address
+ Store (Arg1, HCMD) // Command
+
+ Store (0x48, HCNT) // Start
+
+ If (CMPL()) {
+ Or (HSTS, 0xff, HSTS) // Clean up
+ Return (DAT0) // Success
+ }
+
+ Return (0xffff)
+ }
+#endif
+}
+
diff --git a/src/southbridge/intel/ibexpeak/acpi/usb.asl b/src/southbridge/intel/ibexpeak/acpi/usb.asl
new file mode 100644
index 0000000..f19d368
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/acpi/usb.asl
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel Cougar Point USB support */
+
+// EHCI Controller 0:1d.0
+
+Device (EHC1)
+{
+ Name(_ADR, 0x001d0000)
+
+ Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+ // Leave USB ports on for to allow Wake from USB
+
+ Method(_S3D,0) // Highest D State in S3 State
+ {
+ Return (2)
+ }
+
+ Method(_S4D,0) // Highest D State in S4 State
+ {
+ Return (2)
+ }
+
+ Device (HUB7)
+ {
+ Name (_ADR, 0x00000000)
+
+ // How many are there?
+ Device (PRT1) { Name (_ADR, 1) } // USB Port 0
+ Device (PRT2) { Name (_ADR, 2) } // USB Port 1
+ Device (PRT3) { Name (_ADR, 3) } // USB Port 2
+ Device (PRT4) { Name (_ADR, 4) } // USB Port 3
+ Device (PRT5) { Name (_ADR, 5) } // USB Port 4
+ Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+ }
+}
+
+// EHCI #2 Controller 0:1a.0
+
+Device (EHC2)
+{
+ Name(_ADR, 0x001a0000)
+
+ Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+ // Leave USB ports on for to allow Wake from USB
+
+ Method(_S3D,0) // Highest D State in S3 State
+ {
+ Return (2)
+ }
+
+ Method(_S4D,0) // Highest D State in S4 State
+ {
+ Return (2)
+ }
+
+ Device (HUB7)
+ {
+ Name (_ADR, 0x00000000)
+
+ // How many are there?
+ Device (PRT1) { Name (_ADR, 1) } // USB Port 0
+ Device (PRT2) { Name (_ADR, 2) } // USB Port 1
+ Device (PRT3) { Name (_ADR, 3) } // USB Port 2
+ Device (PRT4) { Name (_ADR, 4) } // USB Port 3
+ Device (PRT5) { Name (_ADR, 5) } // USB Port 4
+ Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+ }
+}
+
+Device (XHC)
+{
+ Name(_ADR, 0x00140000)
+ OperationRegion(XDEV, PCI_Config, 0, 256)
+ Field(XDEV, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0xD0),
+ X2PR, 32, // XUSB2PR
+ PRM2, 32, // XUSB2PRM
+ SSEN, 32, // USB3_PSSEN
+ RPM3, 32, // USB3PRM
+ XPRT, 32, // XHCI Ports
+ }
+
+ Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+ Method(POSC,3,Serialized)
+ {
+ // Create DWord field from the Capabilities Buffer
+ CreateDWordField(Arg2,0,CDW1)
+
+ // Check revision
+ If(LNotEqual(Arg1,One)) {
+ // Set unknown revision bit
+ Or(CDW1,0x8,CDW1)
+ }
+
+ // Set failure if xHCI is disabled by coreboot
+ If(LEqual(XHCI, 0)) {
+ Or(CDW1,0x2,CDW1)
+ }
+
+ // Query flag clear and xHCI in auto mode
+ If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) {
+ Store ("XHCI Switch", Debug)
+ Store(Zero, Local0)
+ And(XPRT, 0x3, Local0)
+ If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) {
+ Store(0xF, Local1)
+ }
+ ElseIf(LEqual(Local0, 2)) {
+ Store(0x3, Local1)
+ }
+ ElseIf(LEqual(Local0, 3)) {
+ Store(Zero, Local1)
+ }
+ And(RPM3, 0xFFFFFFF0, Local0)
+ Or(Local0, Local1, RPM3)
+ And(PRM2, 0xFFFFFFF0, Local0)
+ Or(Local0, Local1, PRM2)
+ And(SSEN, 0xFFFFFFF0, Local0)
+ Or(Local0, Local1, SSEN)
+ And(X2PR, 0xFFFFFFF0, Local0)
+ Or(Local0, Local1, X2PR)
+ }
+ Return(Arg2)
+ }
+
+ // Leave USB ports on for to allow Wake from USB
+ Method(_S3D,0) // Highest D State in S3 State
+ {
+ Return (2)
+ }
+
+ Method(_S4D,0) // Highest D State in S4 State
+ {
+ Return (2)
+ }
+}
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
new file mode 100644
index 0000000..6662df4
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -0,0 +1,372 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "pch.h"
+
+#define HDA_ICII_REG 0x68
+#define HDA_ICII_BUSY (1 << 0)
+#define HDA_ICII_VALID (1 << 1)
+
+typedef struct southbridge_intel_ibexpeak_config config_t;
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+ u32 reg32;
+ int count;
+
+ /* Write (val & mask) to port */
+ val &= mask;
+ reg32 = read32(port);
+ reg32 &= ~mask;
+ reg32 |= val;
+ write32(port, reg32);
+
+ /* Wait for readback of register to
+ * match what was just written to it
+ */
+ count = 50;
+ do {
+ /* Wait 1ms based on BKDG wait time */
+ mdelay(1);
+ reg32 = read32(port);
+ reg32 &= mask;
+ } while ((reg32 != val) && --count);
+
+ /* Timeout occurred */
+ if (!count)
+ return -1;
+ return 0;
+}
+
+static int codec_detect(u32 base)
+{
+ u8 reg8;
+
+ /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+ if (set_bits(base + 0x08, 1, 1) == -1)
+ goto no_codec;
+
+ /* Write back the value once reset bit is set. */
+ write16(base + 0x0, read16(base + 0x0));
+
+ /* Read in Codec location (BAR + 0xe)[2..0]*/
+ reg8 = read8(base + 0xe);
+ reg8 &= 0x0f;
+ if (!reg8)
+ goto no_codec;
+
+ return reg8;
+
+no_codec:
+ /* Codec Not found */
+ /* Put HDA back in reset (BAR + 0x8) [0] */
+ set_bits(base + 0x08, 1, 0);
+ printk(BIOS_DEBUG, "Azalia: No codec!\n");
+ return 0;
+}
+
+const u32 * cim_verb_data = NULL;
+u32 cim_verb_data_size = 0;
+const u32 * pc_beep_verbs = NULL;
+u32 pc_beep_verbs_size = 0;
+
+static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
+{
+ int idx=0;
+
+ while (idx < (cim_verb_data_size / sizeof(u32))) {
+ u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
+ if (cim_verb_data[idx] != viddid) {
+ idx += verb_size + 3; // skip verb + header
+ continue;
+ }
+ *verb = &cim_verb_data[idx+3];
+ return verb_size;
+ }
+
+ /* Not all codecs need to load another verb */
+ return 0;
+}
+
+/**
+ * Wait 50usec for the codec to indicate it is ready
+ * no response would imply that the codec is non-operative
+ */
+
+static int wait_for_ready(u32 base)
+{
+ /* Use a 1msec timeout */
+
+ int timeout = 1000;
+
+ while(timeout--) {
+ u32 reg32 = read32(base + HDA_ICII_REG);
+ if (!(reg32 & HDA_ICII_BUSY))
+ return 0;
+ udelay(1);
+ }
+
+ return -1;
+}
+
+/**
+ * Wait 50usec for the codec to indicate that it accepted
+ * the previous command. No response would imply that the code
+ * is non-operative
+ */
+
+static int wait_for_valid(u32 base)
+{
+ u32 reg32;
+
+ /* Send the verb to the codec */
+ reg32 = read32(base + HDA_ICII_REG);
+ reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
+ write32(base + HDA_ICII_REG, reg32);
+
+ /* Use a 1msec timeout */
+
+ int timeout = 1000;
+ while(timeout--) {
+ reg32 = read32(base + HDA_ICII_REG);
+ if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+ HDA_ICII_VALID)
+ return 0;
+ udelay(1);
+ }
+
+ return -1;
+}
+
+static void codec_init(struct device *dev, u32 base, int addr)
+{
+ u32 reg32;
+ const u32 *verb;
+ u32 verb_size;
+ int i;
+
+ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
+
+ /* 1 */
+ if (wait_for_ready(base) == -1) {
+ printk(BIOS_DEBUG, " codec not ready.\n");
+ return;
+ }
+
+ reg32 = (addr << 28) | 0x000f0000;
+ write32(base + 0x60, reg32);
+
+ if (wait_for_valid(base) == -1) {
+ printk(BIOS_DEBUG, " codec not valid.\n");
+ return;
+ }
+
+ reg32 = read32(base + 0x64);
+
+ /* 2 */
+ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
+ verb_size = find_verb(dev, reg32, &verb);
+
+ if (!verb_size) {
+ printk(BIOS_DEBUG, "Azalia: No verb!\n");
+ return;
+ }
+ printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
+
+ /* 3 */
+ for (i = 0; i < verb_size; i++) {
+ if (wait_for_ready(base) == -1)
+ return;
+
+ write32(base + 0x60, verb[i]);
+
+ if (wait_for_valid(base) == -1)
+ return;
+ }
+ printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
+}
+
+static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+{
+ int i;
+ for (i = 3; i >= 0; i--) {
+ if (codec_mask & (1 << i))
+ codec_init(dev, base, i);
+ }
+
+ for (i = 0; i < pc_beep_verbs_size; i++) {
+ if (wait_for_ready(base) == -1)
+ return;
+
+ write32(base + 0x60, pc_beep_verbs[i]);
+
+ if (wait_for_valid(base) == -1)
+ return;
+ }
+}
+
+static void azalia_init(struct device *dev)
+{
+ u32 base;
+ struct resource *res;
+ u32 codec_mask;
+ u8 reg8;
+ u16 reg16;
+ u32 reg32;
+
+ /* Find base address */
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res)
+ return;
+
+ // NOTE this will break as soon as the Azalia get's a bar above
+ // 4G. Is there anything we can do about it?
+ base = (u32)res->base;
+ printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+
+ if (RCBA32(0x2030) & (1 << 31)) {
+ reg32 = pci_mmio_read_config32(dev, 0x120);
+ reg32 &= 0xf8ffff01;
+ reg32 |= (1 << 24); // 2 << 24 for server
+ reg32 |= RCBA32(0x2030) & 0xfe;
+ pci_mmio_write_config32(dev, 0x120, reg32);
+
+ reg16 = pci_mmio_read_config16(dev, 0x78);
+ reg16 |= (1 << 11);
+ pci_mmio_write_config16(dev, 0x78, reg16);
+ } else
+ printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
+
+ reg32 = pci_mmio_read_config32(dev, 0x114);
+ reg32 &= ~0xfe;
+ pci_mmio_write_config32(dev, 0x114, reg32);
+
+ // Set VCi enable bit
+ reg32 = pci_mmio_read_config32(dev, 0x120);
+ reg32 |= (1 << 31);
+ pci_mmio_write_config32(dev, 0x120, reg32);
+
+ // Enable HDMI codec:
+ reg32 = pci_read_config32(dev, 0xc4);
+ reg32 |= (1 << 1);
+ pci_write_config32(dev, 0xc4, reg32);
+
+ reg8 = pci_read_config8(dev, 0x43);
+ reg8 |= (1 << 6);
+ pci_write_config8(dev, 0x43, reg8);
+
+ /* Additional programming steps */
+ reg32 = pci_read_config32(dev, 0xc4);
+ reg32 |= (1 << 13);
+ pci_write_config32(dev, 0xc4, reg32);
+
+ reg32 = pci_read_config32(dev, 0xc4);
+ reg32 |= (1 << 10);
+ pci_write_config32(dev, 0xc4, reg32);
+
+ reg32 = pci_read_config32(dev, 0xd0);
+ reg32 &= ~(1 << 31);
+ pci_write_config32(dev, 0xd0, reg32);
+
+ if (dev->device == 0x1e20) {
+ /* Additional step on Panther Point */
+ reg32 = pci_read_config32(dev, 0xc4);
+ reg32 |= (1 << 17);
+ pci_write_config32(dev, 0xc4, reg32);
+ }
+
+ /* Set Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+ pci_write_config8(dev, 0x3c, 0x0a); // unused?
+
+ /* Codec Initialization Programming Sequence */
+
+ /* Take controller out of reset */
+ reg32 = read32(base + 0x08);
+ reg32 |= (1 << 0);
+ write32(base + 0x08, reg32);
+ /* Wait 1ms */
+ udelay(1000);
+
+ //
+ reg8 = pci_read_config8(dev, 0x40); // Audio Control
+ reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
+ pci_write_config8(dev, 0x40, reg8);
+
+ reg8 = pci_read_config8(dev, 0x4d); // Docking Status
+ reg8 &= ~(1 << 7); // Docking not supported
+ pci_write_config8(dev, 0x4d, reg8);
+
+ codec_mask = codec_detect(base);
+
+ if (codec_mask) {
+ printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
+ codecs_init(dev, base, codec_mask);
+ }
+
+ /* Enable dynamic clock gating */
+ reg8 = pci_read_config8(dev, 0x43);
+ reg8 &= ~0x7;
+ reg8 |= (1 << 2) | (1 << 0);
+ pci_write_config8(dev, 0x43, reg8);
+}
+
+static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+static struct pci_operations azalia_pci_ops = {
+ .set_subsystem = azalia_set_subsystem,
+};
+
+static struct device_operations azalia_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = azalia_init,
+ .scan_bus = 0,
+ .ops_pci = &azalia_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b56, 0 };
+
+static const struct pci_driver pch_azalia __pci_driver = {
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
+
diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c
new file mode 100644
index 0000000..85a940e
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/bootblock.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <cpu/x86/tsc.h>
+#include "pch.h"
+
+static void store_initial_timestamp(void)
+{
+ /* On Cougar Point we have two 32bit scratchpad registers available:
+ * D0:F0 0xdc (SKPAD)
+ * D31:F2 0xd0 (SATA SP)
+ */
+ tsc_t tsc = rdtsc();
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+ pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+ u8 reg8;
+ device_t dev;
+
+ dev = PCI_DEV(0, 0x1f, 0);
+
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(void)
+{
+ device_t dev = PCI_DEV(0, 0x1f, 0);
+
+ /* Enable port 80 POST on LPC */
+ pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+#if 0
+ RCBA32(GCS) &= (~0x04);
+#else
+ volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
+ u32 reg32 = *gcs;
+ reg32 = reg32 & ~0x04;
+ *gcs = reg32;
+#endif
+}
+
+static void set_spi_speed(void)
+{
+ u32 fdod;
+ u8 ssfc;
+
+ /* Observe SPI Descriptor Component Section 0 */
+ RCBA32(0x38b0) = 0x1000;
+
+ /* Extract the Write/Erase SPI Frequency from descriptor */
+ fdod = RCBA32(0x38b4);
+ fdod >>= 24;
+ fdod &= 7;
+
+ /* Set Software Sequence frequency to match */
+ ssfc = RCBA8(0x3893);
+ ssfc &= ~7;
+ ssfc |= fdod;
+ RCBA8(0x3893) = ssfc;
+}
+
+static void bootblock_southbridge_init(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+ store_initial_timestamp();
+#endif
+ enable_spi_prefetch();
+ enable_port80_on_lpc();
+ set_spi_speed();
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(RC) = (1 << 2);
+}
diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h
new file mode 100644
index 0000000..83248d5
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/chip.h
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H
+#define SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H
+
+struct southbridge_intel_ibexpeak_config {
+ /**
+ * Interrupt Routing configuration
+ * If bit7 is 1, the interrupt is disabled.
+ */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
+
+ /**
+ * GPI Routing configuration
+ *
+ * Only the lower two bits have a meaning:
+ * 00: No effect
+ * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ * 10: SCI (if corresponding GPIO_EN bit is also set)
+ * 11: reserved
+ */
+ uint8_t gpi0_routing;
+ uint8_t gpi1_routing;
+ uint8_t gpi2_routing;
+ uint8_t gpi3_routing;
+ uint8_t gpi4_routing;
+ uint8_t gpi5_routing;
+ uint8_t gpi6_routing;
+ uint8_t gpi7_routing;
+ uint8_t gpi8_routing;
+ uint8_t gpi9_routing;
+ uint8_t gpi10_routing;
+ uint8_t gpi11_routing;
+ uint8_t gpi12_routing;
+ uint8_t gpi13_routing;
+ uint8_t gpi14_routing;
+ uint8_t gpi15_routing;
+
+ uint32_t gpe0_en;
+ uint16_t alt_gp_smi_en;
+
+ /* IDE configuration */
+ uint32_t ide_legacy_combined;
+ uint32_t sata_ahci;
+ uint8_t sata_port_map;
+ uint32_t sata_port0_gen3_tx;
+ uint32_t sata_port1_gen3_tx;
+
+ /**
+ * SATA Interface Speed Support Configuration
+ *
+ * Only the lower two bits have a meaning:
+ * 00 - No effect (leave as chip default)
+ * 01 - 1.5 Gb/s maximum speed
+ * 10 - 3.0 Gb/s maximum speed
+ * 11 - 6.0 Gb/s maximum speed
+ */
+ uint8_t sata_interface_speed_support;
+
+ uint32_t gen1_dec;
+ uint32_t gen2_dec;
+ uint32_t gen3_dec;
+ uint32_t gen4_dec;
+
+ /* Enable linear PCIe Root Port function numbers starting at zero */
+ uint8_t pcie_port_coalesce;
+
+ /* Override PCIe ASPM */
+ uint8_t pcie_aspm_f0;
+ uint8_t pcie_aspm_f1;
+ uint8_t pcie_aspm_f2;
+ uint8_t pcie_aspm_f3;
+ uint8_t pcie_aspm_f4;
+ uint8_t pcie_aspm_f5;
+ uint8_t pcie_aspm_f6;
+ uint8_t pcie_aspm_f7;
+};
+
+#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H */
diff --git a/src/southbridge/intel/ibexpeak/early_me.c b/src/southbridge/intel/ibexpeak/early_me.c
new file mode 100644
index 0000000..670e1ce
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/early_me.c
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include "me.h"
+#include "pch.h"
+
+static const char *me_ack_values[] = {
+ [ME_HFS_ACK_NO_DID] = "No DID Ack received",
+ [ME_HFS_ACK_RESET] = "Non-power cycle reset",
+ [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
+ [ME_HFS_ACK_S3] = "Go to S3",
+ [ME_HFS_ACK_S4] = "Go to S4",
+ [ME_HFS_ACK_S5] = "Go to S5",
+ [ME_HFS_ACK_GBL_RESET] = "Global Reset",
+ [ME_HFS_ACK_CONTINUE] = "Continue to boot"
+};
+
+static inline void pci_read_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = pci_read_config32(PCH_ME_DEV, offset);
+ memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = 0;
+ memcpy(&dword, ptr, sizeof(dword));
+ pci_write_config32(PCH_ME_DEV, offset, dword);
+}
+
+void intel_early_me_status(void)
+{
+ struct me_hfs hfs;
+ struct me_gmes gmes;
+
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+
+ intel_me_status(&hfs, &gmes);
+}
+
+int intel_early_me_init(void)
+{
+ int count;
+ struct me_uma uma;
+ struct me_hfs hfs;
+
+ printk(BIOS_INFO, "Intel ME early init\n");
+
+ /* Wait for ME UMA SIZE VALID bit to be set */
+ for (count = ME_RETRY; count > 0; --count) {
+ pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ if (uma.valid)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!count) {
+ printk(BIOS_ERR, "ERROR: ME is not ready!\n");
+ return -1;
+ }
+
+ /* Check for valid firmware */
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ if (hfs.fpt_bad) {
+ printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
+ return -1;
+ }
+
+ printk(BIOS_INFO, "Intel ME firmware is ready\n");
+ return 0;
+}
+
+int intel_early_me_uma_size(void)
+{
+ struct me_uma uma;
+
+ pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ if (uma.valid) {
+ printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
+ return uma.size;
+ }
+
+ printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
+ return 0;
+}
+
+static inline void set_global_reset(int enable)
+{
+ u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+
+ /* Clear CF9 Without Resume Well Reset Enable */
+ etr3 &= ~ETR3_CWORWRE;
+
+ /* CF9GR indicates a Global Reset */
+ if (enable)
+ etr3 |= ETR3_CF9GR;
+ else
+ etr3 &= ~ETR3_CF9GR;
+
+ pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+}
+
+int intel_early_me_init_done(u8 status)
+{
+ u8 reset;
+ int count;
+ u32 mebase_l, mebase_h;
+ struct me_hfs hfs;
+ struct me_did did = {
+ .init_done = ME_INIT_DONE,
+ .status = status
+ };
+
+ /* MEBASE from MESEG_BASE[35:20] */
+ mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
+ mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
+ did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
+
+ /* Send message to ME */
+ printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
+ "UMA base: 0x%04x\n", status, did.uma_base);
+
+ pci_write_dword_ptr(&did, PCI_ME_H_GS);
+
+ /* Must wait for ME acknowledgement */
+ for (count = ME_RETRY; count > 0; --count) {
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ if (hfs.bios_msg_ack)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!count) {
+ printk(BIOS_ERR, "ERROR: ME failed to respond\n");
+ return -1;
+ }
+
+ /* Return the requested BIOS action */
+ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
+ me_ack_values[hfs.ack_data]);
+
+ /* Check status after acknowledgement */
+ intel_early_me_status();
+
+ reset = 0;
+ switch (hfs.ack_data) {
+ case ME_HFS_ACK_CONTINUE:
+ /* Continue to boot */
+ return 0;
+ case ME_HFS_ACK_RESET:
+ /* Non-power cycle reset */
+ set_global_reset(0);
+ reset = 0x06;
+ break;
+ case ME_HFS_ACK_PWR_CYCLE:
+ /* Power cycle reset */
+ set_global_reset(0);
+ reset = 0x0e;
+ break;
+ case ME_HFS_ACK_GBL_RESET:
+ /* Global reset */
+ set_global_reset(1);
+ reset = 0x0e;
+ break;
+ case ME_HFS_ACK_S3:
+ case ME_HFS_ACK_S4:
+ case ME_HFS_ACK_S5:
+ break;
+ }
+
+ /* Perform the requested reset */
+ if (reset) {
+ outb(reset, 0xcf9);
+ hlt();
+ }
+ return -1;
+}
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
new file mode 100644
index 0000000..d8aff92
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include "pch.h"
+#include "smbus.h"
+
+void enable_smbus(void)
+{
+ device_t dev;
+
+ /* Set the SMBus device statically. */
+ dev = PCI_DEV(0x0, 0x1f, 0x3);
+
+ /* Check to make sure we've got the right device. */
+ if (pci_read_config16(dev, 0x0) != 0x8086) {
+ die("SMBus controller not found!");
+ }
+
+ /* Set SMBus I/O base. */
+ pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ print_debug("SMBus controller enabled.\n");
+}
+
+int smbus_read_byte(unsigned device, unsigned address)
+{
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+int smbus_write_byte(unsigned device, unsigned address, u8 data)
+{
+ return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
+}
+
+int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf)
+{
+ return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}
+
+int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
+{
+ return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}
+
diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c
new file mode 100644
index 0000000..f4e526d
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/early_usb.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include "pch.h"
+
+#define PCH_EHCI1_TEMP_BAR0 0xe8000000
+#define PCH_EHCI2_TEMP_BAR0 0xe8000400
+#define PCH_XHCI_TEMP_BAR0 0xe8001000
+
+/*
+ * Setup USB controller MMIO BAR to prevent the
+ * reference code from resetting the controller.
+ *
+ * The BAR will be re-assigned during device
+ * enumeration so these are only temporary.
+ */
+void enable_usb_bar(void)
+{
+ device_t usb0 = PCH_EHCI1_DEV;
+ device_t usb1 = PCH_EHCI2_DEV;
+ device_t usb3 = PCH_XHCI_DEV;
+ u32 cmd;
+
+ /* USB Controller 1 */
+ pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0);
+ cmd = pci_read_config32(usb0, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb0, PCI_COMMAND, cmd);
+
+ /* USB Controller 1 */
+ pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0);
+ cmd = pci_read_config32(usb1, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb1, PCI_COMMAND, cmd);
+
+ /* USB3 Controller */
+ pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
+ PCH_XHCI_TEMP_BAR0);
+ cmd = pci_read_config32(usb3, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb3, PCI_COMMAND, cmd);
+}
diff --git a/src/southbridge/intel/ibexpeak/elog.c b/src/southbridge/intel/ibexpeak/elog.c
new file mode 100644
index 0000000..09dfcdb
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/elog.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <stdint.h>
+#include <string.h>
+#include <elog.h>
+#include "pch.h"
+
+void pch_log_state(void)
+{
+ u16 pm1_sts, gen_pmcon_3, tco2_sts;
+ u32 gpe0_sts, gpe0_en;
+ u8 gen_pmcon_2;
+ int i;
+ struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ if (!lpc)
+ return;
+
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+ gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS);
+ gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN);
+ tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS);
+ gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2);
+ gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
+
+ /* PWR_FLR Power Failure */
+ if (gen_pmcon_2 & (1 << 0))
+ elog_add_event(ELOG_TYPE_POWER_FAIL);
+
+ /* SUS Well Power Failure */
+ if (gen_pmcon_3 & (1 << 14))
+ elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
+
+ /* SYS_PWROK Failure */
+ if (gen_pmcon_2 & (1 << 1))
+ elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
+
+ /* PWROK Failure */
+ if (gen_pmcon_2 & (1 << 0))
+ elog_add_event(ELOG_TYPE_PWROK_FAIL);
+
+ /* Second TCO Timeout */
+ if (tco2_sts & (1 << 1))
+ elog_add_event(ELOG_TYPE_TCO_RESET);
+
+ /* Power Button Override */
+ if (pm1_sts & (1 << 11))
+ elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
+
+ /* System Reset Status (reset button pushed) */
+ if (gen_pmcon_2 & (1 << 4))
+ elog_add_event(ELOG_TYPE_RESET_BUTTON);
+
+ /* General Reset Status */
+ if (gen_pmcon_3 & (1 << 9))
+ elog_add_event(ELOG_TYPE_SYSTEM_RESET);
+
+ /* ACPI Wake */
+ if (pm1_sts & (1 << 15))
+ elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
+ acpi_slp_type == 3 ? 3 : 5);
+
+ /*
+ * Wake sources
+ */
+
+ /* RTC */
+ if (pm1_sts & (1 << 10))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
+
+ /* PCI Express (TODO: determine wake device) */
+ if (pm1_sts & (1 << 14))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+
+ /* PME (TODO: determine wake device) */
+ if (gpe0_sts & (1 << 13))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
+
+ /* Internal PME (TODO: determine wake device) */
+ if (gpe0_sts & (1 << 13))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
+
+ /* GPIO 0-15 */
+ for (i = 0; i < 16; i++) {
+ if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i))))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+ }
+
+ /* SMBUS Wake */
+ if (gpe0_sts & (1 << 7))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
+}
diff --git a/src/southbridge/intel/ibexpeak/finalize.c b/src/southbridge/intel/ibexpeak/finalize.c
new file mode 100644
index 0000000..6430042
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/finalize.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/post_codes.h>
+#include <northbridge/intel/nehalem/pcie_config.c>
+#include "pch.h"
+#include <spi-generic.h>
+
+void intel_pch_finalize_smm(void)
+{
+ /* Set SPI opcode menu */
+ RCBA16(0x3894) = SPI_OPPREFIX;
+ RCBA16(0x3896) = SPI_OPTYPE;
+ RCBA32(0x3898) = SPI_OPMENU_LOWER;
+ RCBA32(0x389c) = SPI_OPMENU_UPPER;
+
+ /* Lock SPIBAR */
+ RCBA32_OR(0x3804, (1 << 15));
+
+#if CONFIG_SPI_FLASH_SMM
+ /* Re-init SPI driver to handle locked BAR */
+ spi_init();
+#endif
+
+ /* TCLOCKDN: TC Lockdown */
+ RCBA32_OR(0x0050, (1 << 31));
+
+ /* BIOS Interface Lockdown */
+ RCBA32_OR(0x3410, (1 << 0));
+
+ /* Function Disable SUS Well Lockdown */
+ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
+
+ /* Global SMI Lock */
+ pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
+
+ /* GEN_PMCON Lock */
+ pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
+
+ /* R/WO registers */
+ RCBA32(0x21a4) = RCBA32(0x21a4);
+ pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
+ pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+
+ /* Indicate finalize step with post code */
+ outb(POST_OS_BOOT, 0x80);
+}
diff --git a/src/southbridge/intel/ibexpeak/gpio.c b/src/southbridge/intel/ibexpeak/gpio.c
new file mode 100644
index 0000000..39241d6
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/gpio.c
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+
+#include "pch.h"
+#include "gpio.h"
+
+#define MAX_GPIO_NUMBER 75 /* zero based */
+
+void setup_pch_gpios(const struct pch_gpio_map *gpio)
+{
+ u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+
+ /* GPIO Set 1 */
+ if (gpio->set1.level)
+ outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL);
+ if (gpio->set1.mode)
+ outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio->set1.direction)
+ outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio->set1.reset)
+ outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio->set1.invert)
+ outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV);
+ if (gpio->set1.blink)
+ outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio->set2.level)
+ outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2);
+ if (gpio->set2.mode)
+ outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio->set2.direction)
+ outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio->set2.reset)
+ outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio->set3.level)
+ outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3);
+ if (gpio->set3.mode)
+ outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio->set3.direction)
+ outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio->set3.reset)
+ outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
+
+int get_gpio(int gpio_num)
+{
+ static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48};
+ u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+ int index, bit;
+
+ if (gpio_num > MAX_GPIO_NUMBER)
+ return 0; /* Just ignore wrong gpio numbers. */
+
+ index = gpio_num / 32;
+ bit = gpio_num % 32;
+
+ return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1;
+}
+
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array)
+{
+ int gpio;
+ unsigned bitmask = 1;
+ unsigned vector = 0;
+
+ while (bitmask &&
+ ((gpio = *gpio_num_array++) != -1)) {
+ if (get_gpio(gpio))
+ vector |= bitmask;
+ bitmask <<= 1;
+ }
+ return vector;
+}
diff --git a/src/southbridge/intel/ibexpeak/gpio.h b/src/southbridge/intel/ibexpeak/gpio.h
new file mode 100644
index 0000000..44e808a
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/gpio.h
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef INTEL_BD82X6X_GPIO_H
+#define INTEL_BD82X6X_GPIO_H
+
+#define GPIO_MODE_NATIVE 0
+#define GPIO_MODE_GPIO 1
+#define GPIO_MODE_NONE 1
+
+#define GPIO_DIR_OUTPUT 0
+#define GPIO_DIR_INPUT 1
+
+#define GPIO_NO_INVERT 0
+#define GPIO_INVERT 1
+
+#define GPIO_LEVEL_LOW 0
+#define GPIO_LEVEL_HIGH 1
+
+#define GPIO_NO_BLINK 0
+#define GPIO_BLINK 1
+
+#define GPIO_RESET_PWROK 0
+#define GPIO_RESET_RSMRST 1
+
+struct pch_gpio_set1 {
+ u32 gpio0 : 1;
+ u32 gpio1 : 1;
+ u32 gpio2 : 1;
+ u32 gpio3 : 1;
+ u32 gpio4 : 1;
+ u32 gpio5 : 1;
+ u32 gpio6 : 1;
+ u32 gpio7 : 1;
+ u32 gpio8 : 1;
+ u32 gpio9 : 1;
+ u32 gpio10 : 1;
+ u32 gpio11 : 1;
+ u32 gpio12 : 1;
+ u32 gpio13 : 1;
+ u32 gpio14 : 1;
+ u32 gpio15 : 1;
+ u32 gpio16 : 1;
+ u32 gpio17 : 1;
+ u32 gpio18 : 1;
+ u32 gpio19 : 1;
+ u32 gpio20 : 1;
+ u32 gpio21 : 1;
+ u32 gpio22 : 1;
+ u32 gpio23 : 1;
+ u32 gpio24 : 1;
+ u32 gpio25 : 1;
+ u32 gpio26 : 1;
+ u32 gpio27 : 1;
+ u32 gpio28 : 1;
+ u32 gpio29 : 1;
+ u32 gpio30 : 1;
+ u32 gpio31 : 1;
+} __attribute__ ((packed));
+
+struct pch_gpio_set2 {
+ u32 gpio32 : 1;
+ u32 gpio33 : 1;
+ u32 gpio34 : 1;
+ u32 gpio35 : 1;
+ u32 gpio36 : 1;
+ u32 gpio37 : 1;
+ u32 gpio38 : 1;
+ u32 gpio39 : 1;
+ u32 gpio40 : 1;
+ u32 gpio41 : 1;
+ u32 gpio42 : 1;
+ u32 gpio43 : 1;
+ u32 gpio44 : 1;
+ u32 gpio45 : 1;
+ u32 gpio46 : 1;
+ u32 gpio47 : 1;
+ u32 gpio48 : 1;
+ u32 gpio49 : 1;
+ u32 gpio50 : 1;
+ u32 gpio51 : 1;
+ u32 gpio52 : 1;
+ u32 gpio53 : 1;
+ u32 gpio54 : 1;
+ u32 gpio55 : 1;
+ u32 gpio56 : 1;
+ u32 gpio57 : 1;
+ u32 gpio58 : 1;
+ u32 gpio59 : 1;
+ u32 gpio60 : 1;
+ u32 gpio61 : 1;
+ u32 gpio62 : 1;
+ u32 gpio63 : 1;
+} __attribute__ ((packed));
+
+struct pch_gpio_set3 {
+ u32 gpio64 : 1;
+ u32 gpio65 : 1;
+ u32 gpio66 : 1;
+ u32 gpio67 : 1;
+ u32 gpio68 : 1;
+ u32 gpio69 : 1;
+ u32 gpio70 : 1;
+ u32 gpio71 : 1;
+ u32 gpio72 : 1;
+ u32 gpio73 : 1;
+ u32 gpio74 : 1;
+ u32 gpio75 : 1;
+} __attribute__ ((packed));
+
+struct pch_gpio_map {
+ struct {
+ const struct pch_gpio_set1 *mode;
+ const struct pch_gpio_set1 *direction;
+ const struct pch_gpio_set1 *level;
+ const struct pch_gpio_set1 *reset;
+ const struct pch_gpio_set1 *invert;
+ const struct pch_gpio_set1 *blink;
+ } set1;
+ struct {
+ const struct pch_gpio_set2 *mode;
+ const struct pch_gpio_set2 *direction;
+ const struct pch_gpio_set2 *level;
+ const struct pch_gpio_set2 *reset;
+ } set2;
+ struct {
+ const struct pch_gpio_set3 *mode;
+ const struct pch_gpio_set3 *direction;
+ const struct pch_gpio_set3 *level;
+ const struct pch_gpio_set3 *reset;
+ } set3;
+};
+
+/* Configure GPIOs with mainboard provided settings */
+void setup_pch_gpios(const struct pch_gpio_map *gpio);
+
+/* get GPIO pin value */
+int get_gpio(int gpio_num);
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array);
+
+#endif
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
new file mode 100644
index 0000000..b0af6dc
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -0,0 +1,693 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <elog.h>
+#include "pch.h"
+
+#define NMI_OFF 0
+
+#define ENABLE_ACPI_MODE_IN_COREBOOT 0
+#define TEST_SMM_FLASH_LOCKDOWN 0
+
+typedef struct southbridge_intel_ibexpeak_config config_t;
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void pch_enable_ioapic(struct device *dev)
+{
+ u32 reg32;
+
+ /* Enable ACPI I/O range decode */
+ pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+
+ set_ioapic_id(IO_APIC_ADDR, 0x01);
+
+ /* affirm full set of redirection table entries ("write once") */
+ reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+ io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+
+ /*
+ * Select Boot Configuration register (0x03) and
+ * use Processor System Bus (0x01) to deliver interrupts.
+ */
+ io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+}
+
+static void pch_enable_serial_irqs(struct device *dev)
+{
+ /* Set packet length and toggle silent mode bit for one frame. */
+ pci_write_config8(dev, SERIRQ_CNTL,
+ (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+#if !CONFIG_SERIRQ_CONTINUOUS_MODE
+ pci_write_config8(dev, SERIRQ_CNTL,
+ (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+#endif
+}
+
+/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+
+static void pch_pirq_init(device_t dev)
+{
+ device_t irq_dev;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+ pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+ pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+ pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+
+ pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+ pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+ pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+ /* Eric Biederman once said we should let the OS do this.
+ * I am not so sure anymore he was right.
+ */
+
+ for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin=0, int_line=0;
+
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
+
+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+ switch (int_pin) {
+ case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+ case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+ case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+ case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ }
+
+ if (!int_line)
+ continue;
+
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ }
+}
+
+static void pch_gpi_routing(device_t dev)
+{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+ u32 reg32 = 0;
+
+ /* An array would be much nicer here, or some
+ * other method of doing this.
+ */
+ reg32 |= (config->gpi0_routing & 0x03) << 0;
+ reg32 |= (config->gpi1_routing & 0x03) << 2;
+ reg32 |= (config->gpi2_routing & 0x03) << 4;
+ reg32 |= (config->gpi3_routing & 0x03) << 6;
+ reg32 |= (config->gpi4_routing & 0x03) << 8;
+ reg32 |= (config->gpi5_routing & 0x03) << 10;
+ reg32 |= (config->gpi6_routing & 0x03) << 12;
+ reg32 |= (config->gpi7_routing & 0x03) << 14;
+ reg32 |= (config->gpi8_routing & 0x03) << 16;
+ reg32 |= (config->gpi9_routing & 0x03) << 18;
+ reg32 |= (config->gpi10_routing & 0x03) << 20;
+ reg32 |= (config->gpi11_routing & 0x03) << 22;
+ reg32 |= (config->gpi12_routing & 0x03) << 24;
+ reg32 |= (config->gpi13_routing & 0x03) << 26;
+ reg32 |= (config->gpi14_routing & 0x03) << 28;
+ reg32 |= (config->gpi15_routing & 0x03) << 30;
+
+ pci_write_config32(dev, 0xb8, reg32);
+}
+
+static void pch_power_options(device_t dev)
+{
+ u8 reg8;
+ u16 reg16, pmbase;
+ u32 reg32;
+ const char *state;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int nmi_option;
+
+ /* Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use Kconfig setting.
+ */
+ get_option(&pwr_on, "power_on_after_fail");
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_3);
+ reg16 &= 0xfffe;
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
+ reg16 |= 1;
+ state = "off";
+ break;
+ case MAINBOARD_POWER_ON:
+ reg16 &= ~1;
+ state = "on";
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg16 &= ~1;
+ state = "state keep";
+ break;
+ default:
+ state = "undefined";
+ }
+
+ reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
+ reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
+
+ reg16 &= ~(1 << 10);
+ reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
+
+ reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
+
+ pci_write_config16(dev, GEN_PMCON_3, reg16);
+ printk(BIOS_INFO, "Set power %s after power failure.\n", state);
+
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ reg8 &= 0x0f; /* Higher Nibble must be 0 */
+ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
+ // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
+ reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ printk(BIOS_INFO, "NMI sources enabled.\n");
+ reg8 &= ~(1 << 7); /* Set NMI. */
+ } else {
+ printk(BIOS_INFO, "NMI sources disabled.\n");
+ reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
+ }
+ outb(reg8, 0x70);
+
+ /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~(3 << 0); // SMI# rate 1 minute
+ reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
+ * periodic SMIs.
+ */
+ reg16 |= (3 << 0); // Periodic SMI every 8s
+#endif
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ // Set the board's GPI routing.
+ pch_gpi_routing(dev);
+
+ pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+ outl(config->gpe0_en, pmbase + GPE0_EN);
+ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
+
+ /* Set up power management block and determine sleep mode */
+ reg32 = inl(pmbase + 0x04); // PM1_CNT
+ reg32 &= ~(7 << 10); // SLP_TYP
+ reg32 |= (1 << 0); // SCI_EN
+ outl(reg32, pmbase + 0x04);
+
+ /* Clear magic status bits to prevent unexpected wake */
+ reg32 = RCBA32(0x3310);
+ reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
+ RCBA32(0x3310) = reg32;
+
+ reg32 = RCBA32(0x3f02);
+ reg32 &= ~0xf;
+ RCBA32(0x3f02) = reg32;
+}
+
+static void pch_rtc_init(struct device *dev)
+{
+ u8 reg8;
+ int rtc_failed;
+
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ rtc_failed = reg8 & RTC_BATTERY_DEAD;
+ if (rtc_failed) {
+ reg8 &= ~RTC_BATTERY_DEAD;
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+#if CONFIG_ELOG
+ elog_add_event(ELOG_TYPE_RTC_RESET);
+#endif
+ }
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
+
+ rtc_init(rtc_failed);
+}
+
+static void mobile5_pm_init(struct device *dev)
+{
+ int i;
+
+ printk(BIOS_DEBUG, "Mobile 5 PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+
+ RCBA32 (0x1d44) = 0x00000000;
+ (void) RCBA32 (0x1d44);
+ RCBA32 (0x1d48) = 0x00030000;
+ (void) RCBA32 (0x1d48);
+ RCBA32 (0x1e80) = 0x000c0801;
+ (void) RCBA32 (0x1e80);
+ RCBA32 (0x1e84) = 0x000200f0;
+ (void) RCBA32 (0x1e84);
+
+ const u32 rcba2010[] =
+ {
+ /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000,
+ /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170
+ };
+ for (i = 0; i < sizeof (rcba2010) / sizeof (rcba2010[0]); i++)
+ {
+ RCBA32 (0x2010 + 4 * i) = rcba2010[i];
+ RCBA32 (0x2010 + 4 * i);
+ }
+
+ RCBA32 (0x2100) = 0x00000000;
+ (void) RCBA32 (0x2100);
+ RCBA32 (0x2104) = 0x00000757;
+ (void) RCBA32 (0x2104);
+ RCBA32 (0x2108) = 0x00170001;
+ (void) RCBA32 (0x2108);
+
+ RCBA32 (0x211c) = 0x00000000;
+ (void) RCBA32 (0x211c);
+ RCBA32 (0x2120) = 0x00010000;
+ (void) RCBA32 (0x2120);
+
+ RCBA32 (0x21fc) = 0x00000000;
+ (void) RCBA32 (0x21fc);
+ RCBA32 (0x2200) = 0x20000044;
+ (void) RCBA32 (0x2200);
+ RCBA32 (0x2204) = 0x00000001;
+ (void) RCBA32 (0x2204);
+ RCBA32 (0x2208) = 0x00003457;
+ (void) RCBA32 (0x2208);
+
+ const u32 rcba2210[] =
+ {
+ /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00,
+ /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000,
+ /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000,
+ /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000,
+ /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000,
+ /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000,
+ /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000
+ };
+
+ for (i = 0; i < sizeof (rcba2210) / sizeof (rcba2210[0]); i++)
+ {
+ RCBA32 (0x2210 + 4 * i) = rcba2210[i];
+ RCBA32 (0x2210 + 4 * i);
+ }
+
+ const u32 rcba2300[] =
+ {
+ /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131,
+ /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040,
+ /* 2320: */ 0xcccc0cfc, 0x0fbb0fff
+ };
+
+ for (i = 0; i < sizeof (rcba2300) / sizeof (rcba2300[0]); i++)
+ {
+ RCBA32 (0x2300 + 4 * i) = rcba2300[i];
+ RCBA32 (0x2300 + 4 * i);
+ }
+
+ RCBA32 (0x37fc) = 0x00000000;
+ (void) RCBA32 (0x37fc);
+ RCBA32 (0x3dfc) = 0x00000000;
+ (void) RCBA32 (0x3dfc);
+ RCBA32 (0x3e7c) = 0xffffffff;
+ (void) RCBA32 (0x3e7c);
+ RCBA32 (0x3efc) = 0x00000000;
+ (void) RCBA32 (0x3efc);
+ RCBA32 (0x3f00) = 0x0000010b;
+ (void) RCBA32 (0x3f00);
+}
+
+static void enable_hpet(void)
+{
+ u32 reg32;
+
+ /* Move HPET to default address 0xfed00000 and enable it */
+ reg32 = RCBA32(HPTC);
+ reg32 |= (1 << 7); // HPET Address Enable
+ reg32 &= ~(3 << 0);
+ RCBA32(HPTC) = reg32;
+
+#if CONFIG_NORTHBRIDGE_INTEL_NEHALEM
+ write32(0xfed00010, read32(0xfed00010) | 1);
+#endif
+}
+
+static void enable_clock_gating(device_t dev)
+{
+ u32 reg32;
+ u16 reg16;
+
+ RCBA32_AND_OR(0x2234, ~0UL, 0xf);
+
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 |= (1 << 2) | (1 << 11);
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
+ pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
+ pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+
+ reg32 = RCBA32(CG);
+ reg32 |= (1 << 31);
+ reg32 |= (1 << 29) | (1 << 28);
+ reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+ reg32 |= (1 << 16);
+ reg32 |= (1 << 17);
+ reg32 |= (1 << 18);
+ reg32 |= (1 << 22);
+ reg32 |= (1 << 23);
+ reg32 &= ~(1 << 20);
+ reg32 |= (1 << 19);
+ reg32 |= (1 << 0);
+ reg32 |= (0xf << 1);
+ RCBA32(CG) = reg32;
+
+ RCBA32_OR(0x38c0, 0x7);
+ RCBA32_OR(0x36d4, 0x6680c004);
+ RCBA32_OR(0x3564, 0x3);
+}
+
+#if CONFIG_HAVE_SMI_HANDLER
+static void pch_lock_smm(struct device *dev)
+{
+#if TEST_SMM_FLASH_LOCKDOWN
+ u8 reg8;
+#endif
+
+ if (acpi_slp_type != 3) {
+#if ENABLE_ACPI_MODE_IN_COREBOOT
+ printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
+ outb(0xe1, 0xb2); // Enable ACPI mode
+ printk(BIOS_DEBUG, "done.\n");
+#else
+ printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+ outb(0x1e, 0xb2); // Disable ACPI mode
+ printk(BIOS_DEBUG, "done.\n");
+#endif
+ }
+
+ /* Don't allow evil boot loaders, kernels, or
+ * userspace applications to deceive us:
+ */
+ smm_lock();
+
+#if TEST_SMM_FLASH_LOCKDOWN
+ /* Now try this: */
+ printk(BIOS_DEBUG, "Locking BIOS to RO... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ (reg8&1)?"rw":"ro");
+ reg8 &= ~(1 << 0); /* clear BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+ reg8 |= (1 << 1); /* set BLE */
+ pci_write_config8(dev, 0xdc, reg8);
+ printk(BIOS_DEBUG, "ok.\n");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ (reg8&1)?"rw":"ro");
+
+ printk(BIOS_DEBUG, "Writing:\n");
+ *(volatile u8 *)0xfff00000 = 0x00;
+ printk(BIOS_DEBUG, "Testing:\n");
+ reg8 |= (1 << 0); /* set BIOSWE */
+ pci_write_config8(dev, 0xdc, reg8);
+
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ (reg8&1)?"rw":"ro");
+ printk(BIOS_DEBUG, "Done.\n");
+#endif
+}
+#endif
+
+static void pch_disable_smm_only_flashing(struct device *dev)
+{
+ u8 reg8;
+
+ printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
+ reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 &= ~(1 << 5);
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void pch_fixups(struct device *dev)
+{
+ /*
+ * Enable DMI ASPM in the PCH
+ */
+ RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
+ RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
+ RCBA32_OR(0x21a8, 0x3);
+}
+
+static void pch_decode_init(struct device *dev)
+{
+ config_t *config = dev->chip_info;
+
+ printk(BIOS_DEBUG, "pch_decode_init\n");
+
+ pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
+}
+
+static void lpc_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "pch: lpc_init\n");
+
+ /* Set the value for PCI command register. */
+ pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+ /* IO APIC initialization. */
+ pch_enable_ioapic(dev);
+
+ pch_enable_serial_irqs(dev);
+
+ /* Setup the PIRQ. */
+ pch_pirq_init(dev);
+
+ /* Setup power options. */
+ pch_power_options(dev);
+
+ /* Initialize power management */
+ switch (pch_silicon_type()) {
+ case PCH_TYPE_MOBILE5:
+ mobile5_pm_init (dev);
+ break;
+ default:
+ printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
+ }
+
+ /* Set the state of the GPIO lines. */
+ //gpio_init(dev);
+
+ /* Initialize the real time clock. */
+ pch_rtc_init(dev);
+
+ /* Initialize ISA DMA. */
+ isa_dma_init();
+
+ /* Initialize the High Precision Event Timers, if present. */
+ enable_hpet();
+
+ /* Initialize Clock Gating */
+ enable_clock_gating(dev);
+
+ setup_i8259();
+
+ /* The OS should do this? */
+ /* Interrupt 9 should be level triggered (SCI) */
+ i8259_configure_irq_trigger(9, 1);
+
+ pch_disable_smm_only_flashing(dev);
+
+#if CONFIG_HAVE_SMI_HANDLER
+ pch_lock_smm(dev);
+#endif
+
+ pch_fixups(dev);
+}
+
+static void pch_lpc_read_resources(device_t dev)
+{
+ struct resource *res;
+ config_t *config = dev->chip_info;
+ u8 io_index = 0;
+
+ /* Get the normal PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add an extra subtractive resource for both memory and I/O. */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = 0xff800000;
+ res->size = 0x00800000; /* 8 MB for flash */
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = IO_APIC_ADDR;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ /* Set PCH IO decode ranges if required.*/
+ if ((config->gen1_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen1_dec & 0xFFFC;
+ res->size = (config->gen1_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+
+ if ((config->gen2_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen2_dec & 0xFFFC;
+ res->size = (config->gen2_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+
+ if ((config->gen3_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen3_dec & 0xFFFC;
+ res->size = (config->gen3_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+
+ if ((config->gen4_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen4_dec & 0xFFFC;
+ res->size = (config->gen4_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+}
+
+static void pch_lpc_enable_resources(device_t dev)
+{
+ pch_decode_init(dev);
+ return pci_dev_enable_resources(dev);
+}
+
+static void pch_lpc_enable(device_t dev)
+{
+ /* Enable PCH Display Port */
+ RCBA16(DISPBDF) = 0x0010;
+ RCBA32_OR(FD2, PCH_ENABLE_DBDF);
+
+ pch_enable(dev);
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pch_lpc_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pch_lpc_enable_resources,
+ .init = lpc_init,
+ .enable = pch_lpc_enable,
+ .scan_bus = scan_static_bus,
+ .ops_pci = &pci_ops,
+};
+
+
+/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
+ * Intel C200 Series Chipset
+ */
+
+static const unsigned short pci_device_ids[] = { 0x3b07,
+ 0 };
+
+static const struct pci_driver pch_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
+
+
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
new file mode 100644
index 0000000..5cd0990
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -0,0 +1,658 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This is a ramstage driver for the Intel Management Engine found in the
+ * 6-series chipset. It handles the required boot-time messages over the
+ * MMIO-based Management Engine Interface to tell the ME that the BIOS is
+ * finished with POST. Additional messages are defined for debug but are
+ * not used unless the console loglevel is high enough.
+ */
+
+#include <arch/acpi.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include <string.h>
+#include <delay.h>
+#include <elog.h>
+
+#ifdef __SMM__
+# include <northbridge/intel/nehalem/pcie_config.c>
+#else
+# include <device/device.h>
+# include <device/pci.h>
+#endif
+
+#include "me.h"
+#include "pch.h"
+
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
+
+#ifndef __SMM__
+/* Path that the BIOS should take based on ME state */
+static const char *me_bios_path_values[] = {
+ [ME_NORMAL_BIOS_PATH] = "Normal",
+ [ME_S3WAKE_BIOS_PATH] = "S3 Wake",
+ [ME_ERROR_BIOS_PATH] = "Error",
+ [ME_RECOVERY_BIOS_PATH] = "Recovery",
+ [ME_DISABLE_BIOS_PATH] = "Disable",
+ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
+};
+#endif
+
+/* MMIO base address for MEI interface */
+static u32 mei_base_address;
+
+#if CONFIG_DEBUG_INTEL_ME
+static void mei_dump(void *ptr, int dword, int offset, const char *type)
+{
+ struct mei_csr *csr;
+
+ printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
+
+ switch (offset) {
+ case MEI_H_CSR:
+ case MEI_ME_CSR_HA:
+ csr = ptr;
+ if (!csr) {
+ printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword);
+ break;
+ }
+ printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u "
+ "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth,
+ csr->buffer_read_ptr, csr->buffer_write_ptr,
+ csr->ready, csr->reset, csr->interrupt_generate,
+ csr->interrupt_status, csr->interrupt_enable);
+ break;
+ case MEI_ME_CB_RW:
+ case MEI_H_CB_WW:
+ printk(BIOS_SPEW, "CB: 0x%08x\n", dword);
+ break;
+ default:
+ printk(BIOS_SPEW, "0x%08x\n", offset);
+ break;
+ }
+}
+#else
+# define mei_dump(ptr,dword,offset,type) do {} while (0)
+#endif
+
+/*
+ * ME/MEI access helpers using memcpy to avoid aliasing.
+ */
+
+static inline void mei_read_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = read32(mei_base_address + offset);
+ memcpy(ptr, &dword, sizeof(dword));
+ mei_dump(ptr, dword, offset, "READ");
+}
+
+static inline void mei_write_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = 0;
+ memcpy(&dword, ptr, sizeof(dword));
+ write32(mei_base_address + offset, dword);
+ mei_dump(ptr, dword, offset, "WRITE");
+}
+
+#ifndef __SMM__
+static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+{
+ u32 dword = pci_read_config32(dev, offset);
+ memcpy(ptr, &dword, sizeof(dword));
+ mei_dump(ptr, dword, offset, "PCI READ");
+}
+#endif
+
+static inline void read_host_csr(struct mei_csr *csr)
+{
+ mei_read_dword_ptr(csr, MEI_H_CSR);
+}
+
+static inline void write_host_csr(struct mei_csr *csr)
+{
+ mei_write_dword_ptr(csr, MEI_H_CSR);
+}
+
+static inline void read_me_csr(struct mei_csr *csr)
+{
+ mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
+}
+
+static inline void write_cb(u32 dword)
+{
+ write32(mei_base_address + MEI_H_CB_WW, dword);
+ mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
+}
+
+static inline u32 read_cb(void)
+{
+ u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
+ return dword;
+}
+
+/* Wait for ME ready bit to be asserted */
+static int mei_wait_for_me_ready(void)
+{
+ struct mei_csr me;
+ unsigned try = ME_RETRY;
+
+ while (try--) {
+ read_me_csr(&me);
+ if (me.ready)
+ return 0;
+ udelay(ME_DELAY);
+ }
+
+ printk(BIOS_ERR, "ME: failed to become ready\n");
+ return -1;
+}
+
+static void mei_reset(void)
+{
+ struct mei_csr host;
+
+ if (mei_wait_for_me_ready() < 0)
+ return;
+
+ /* Reset host and ME circular buffers for next message */
+ read_host_csr(&host);
+ host.reset = 1;
+ host.interrupt_generate = 1;
+ write_host_csr(&host);
+
+ if (mei_wait_for_me_ready() < 0)
+ return;
+
+ /* Re-init and indicate host is ready */
+ read_host_csr(&host);
+ host.interrupt_generate = 1;
+ host.ready = 1;
+ host.reset = 0;
+ write_host_csr(&host);
+}
+
+static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
+ void *req_data)
+{
+ struct mei_csr host;
+ unsigned ndata, n;
+ u32 *data;
+
+ /* Number of dwords to write, ignoring MKHI */
+ ndata = mei->length >> 2;
+
+ /* Pad non-dword aligned request message length */
+ if (mei->length & 3)
+ ndata++;
+ if (!ndata) {
+ printk(BIOS_DEBUG, "ME: request does not include MKHI\n");
+ return -1;
+ }
+ ndata++; /* Add MEI header */
+
+ /*
+ * Make sure there is still room left in the circular buffer.
+ * Reset the buffer pointers if the requested message will not fit.
+ */
+ read_host_csr(&host);
+ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
+ printk(BIOS_ERR, "ME: circular buffer full, resetting...\n");
+ mei_reset();
+ read_host_csr(&host);
+ }
+
+ /*
+ * This implementation does not handle splitting large messages
+ * across multiple transactions. Ensure the requested length
+ * will fit in the available circular buffer depth.
+ */
+ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
+ printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n",
+ ndata + 2, host.buffer_depth);
+ return -1;
+ }
+
+ /* Write MEI header */
+ mei_write_dword_ptr(mei, MEI_H_CB_WW);
+ ndata--;
+
+ /* Write MKHI header */
+ mei_write_dword_ptr(mkhi, MEI_H_CB_WW);
+ ndata--;
+
+ /* Write message data */
+ data = req_data;
+ for (n = 0; n < ndata; ++n)
+ write_cb(*data++);
+
+ /* Generate interrupt to the ME */
+ read_host_csr(&host);
+ host.interrupt_generate = 1;
+ write_host_csr(&host);
+
+ /* Make sure ME is ready after sending request data */
+ return mei_wait_for_me_ready();
+}
+
+static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
+ void *rsp_data, int rsp_bytes)
+{
+ struct mei_header mei_rsp;
+ struct mkhi_header mkhi_rsp;
+ struct mei_csr me, host;
+ unsigned ndata, n;
+ unsigned expected;
+ u32 *data;
+
+ /* Total number of dwords to read from circular buffer */
+ expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2;
+ if (rsp_bytes & 3)
+ expected++;
+
+ /*
+ * The interrupt status bit does not appear to indicate that the
+ * message has actually been received. Instead we wait until the
+ * expected number of dwords are present in the circular buffer.
+ */
+ for (n = ME_RETRY; n; --n) {
+ read_me_csr(&me);
+ if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!n) {
+ printk(BIOS_ERR, "ME: timeout waiting for data: expected "
+ "%u, available %u\n", expected,
+ me.buffer_write_ptr - me.buffer_read_ptr);
+ return -1;
+ }
+
+ /* Read and verify MEI response header from the ME */
+ mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
+ if (!mei_rsp.is_complete) {
+ printk(BIOS_ERR, "ME: response is not complete\n");
+ return -1;
+ }
+
+ /* Handle non-dword responses and expect at least MKHI header */
+ ndata = mei_rsp.length >> 2;
+ if (mei_rsp.length & 3)
+ ndata++;
+ if (ndata != (expected - 1)) {
+ printk(BIOS_ERR, "ME: response is missing data\n");
+ return -1;
+ }
+
+ /* Read and verify MKHI response header from the ME */
+ mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW);
+ if (!mkhi_rsp.is_response ||
+ mkhi->group_id != mkhi_rsp.group_id ||
+ mkhi->command != mkhi_rsp.command) {
+ printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, "
+ "command %u ?= %u, is_response %u\n", mkhi->group_id,
+ mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
+ mkhi_rsp.is_response);
+ return -1;
+ }
+ ndata--; /* MKHI header has been read */
+
+ /* Make sure caller passed a buffer with enough space */
+ if (ndata != (rsp_bytes >> 2)) {
+ printk(BIOS_ERR, "ME: not enough room in response buffer: "
+ "%u != %u\n", ndata, rsp_bytes >> 2);
+ return -1;
+ }
+
+ /* Read response data from the circular buffer */
+ data = rsp_data;
+ for (n = 0; n < ndata; ++n)
+ *data++ = read_cb();
+
+ /* Tell the ME that we have consumed the response */
+ read_host_csr(&host);
+ host.interrupt_status = 1;
+ host.interrupt_generate = 1;
+ write_host_csr(&host);
+
+ return mei_wait_for_me_ready();
+}
+
+static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
+ void *req_data, void *rsp_data, int rsp_bytes)
+{
+ if (mei_send_msg(mei, mkhi, req_data) < 0)
+ return -1;
+ if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0)
+ return -1;
+ return 0;
+}
+
+#ifdef __SMM__
+/* Send END OF POST message to the ME */
+static int mkhi_end_of_post(void)
+{
+ struct mkhi_header mkhi = {
+ .group_id = MKHI_GROUP_ID_GEN,
+ .command = MKHI_END_OF_POST,
+ };
+ struct mei_header mei = {
+ .is_complete = 1,
+ .host_address = MEI_HOST_ADDRESS,
+ .client_address = MEI_ADDRESS_MKHI,
+ .length = sizeof(mkhi),
+ };
+
+ /* Send request and wait for response */
+ if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) {
+ printk(BIOS_ERR, "ME: END OF POST message failed\n");
+ return -1;
+ }
+
+ printk(BIOS_INFO, "ME: END OF POST message successful\n");
+ return 0;
+}
+#endif
+
+#ifdef __SMM__
+static void intel_me7_finalize_smm(void)
+{
+ struct me_hfs hfs;
+ u32 reg32;
+
+ mei_base_address =
+ pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+
+ /* S3 path will have hidden this device already */
+ if (!mei_base_address || mei_base_address == 0xfffffff0)
+ return;
+
+ /* Make sure ME is in a mode that expects EOP */
+ reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ memcpy(&hfs, ®32, sizeof(u32));
+
+ /* Abort and leave device alone if not normal mode */
+ if (hfs.fpt_bad ||
+ hfs.working_state != ME_HFS_CWS_NORMAL ||
+ hfs.operation_mode != ME_HFS_MODE_NORMAL)
+ return;
+
+ /* Try to send EOP command so ME stops accepting other commands */
+ mkhi_end_of_post();
+
+ /* Make sure IO is disabled */
+ reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+
+ /* Hide the PCI device */
+ RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+}
+
+void intel_me_finalize_smm(void)
+{
+ u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
+ switch (did) {
+ case 0x1c3a8086:
+ intel_me7_finalize_smm();
+ break;
+ case 0x1e3a8086:
+ intel_me8_finalize_smm();
+ break;
+ default:
+ printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did);
+ }
+}
+#else /* !__SMM__ */
+
+/* Determine the path that we should take based on ME status */
+static me_bios_path intel_me_path(device_t dev)
+{
+ me_bios_path path = ME_DISABLE_BIOS_PATH;
+ struct me_hfs hfs;
+ struct me_gmes gmes;
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* S3 wake skips all MKHI messages */
+ if (acpi_slp_type == 3) {
+ return ME_S3WAKE_BIOS_PATH;
+ }
+#endif
+
+ pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
+
+ /* Check and dump status */
+ intel_me_status(&hfs, &gmes);
+
+ /* Check Current Working State */
+ switch (hfs.working_state) {
+ case ME_HFS_CWS_NORMAL:
+ path = ME_NORMAL_BIOS_PATH;
+ break;
+ case ME_HFS_CWS_REC:
+ path = ME_RECOVERY_BIOS_PATH;
+ break;
+ default:
+ path = ME_DISABLE_BIOS_PATH;
+ break;
+ }
+
+ /* Check Current Operation Mode */
+ switch (hfs.operation_mode) {
+ case ME_HFS_MODE_NORMAL:
+ break;
+ case ME_HFS_MODE_DEBUG:
+ case ME_HFS_MODE_DIS:
+ case ME_HFS_MODE_OVER_JMPR:
+ case ME_HFS_MODE_OVER_MEI:
+ default:
+ path = ME_DISABLE_BIOS_PATH;
+ break;
+ }
+
+ /* Check for any error code and valid firmware */
+ if (hfs.error_code || hfs.fpt_bad)
+ path = ME_ERROR_BIOS_PATH;
+
+#if CONFIG_ELOG
+ if (path != ME_NORMAL_BIOS_PATH) {
+ struct elog_event_data_me_extended data = {
+ .current_working_state = hfs.working_state,
+ .operation_state = hfs.operation_state,
+ .operation_mode = hfs.operation_mode,
+ .error_code = hfs.error_code,
+ .progress_code = gmes.progress_code,
+ .current_pmevent = gmes.current_pmevent,
+ .current_state = gmes.current_state,
+ };
+ elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path);
+ elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT,
+ &data, sizeof(data));
+ }
+#endif
+
+ return path;
+}
+
+/* Prepare ME for MEI messages */
+static int intel_mei_setup(device_t dev)
+{
+ struct resource *res;
+ struct mei_csr host;
+ u32 reg32;
+
+ /* Find the MMIO base for the ME interface */
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res || res->base == 0 || res->size == 0) {
+ printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
+ return -1;
+ }
+ mei_base_address = res->base;
+
+ /* Ensure Memory and Bus Master bits are set */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Clean up status for next message */
+ read_host_csr(&host);
+ host.interrupt_generate = 1;
+ host.ready = 1;
+ host.reset = 0;
+ write_host_csr(&host);
+
+ return 0;
+}
+
+/* Read the Extend register hash of ME firmware */
+static int intel_me_extend_valid(device_t dev)
+{
+ struct me_heres status;
+ u32 extend[8] = {0};
+ int i, count = 0;
+
+ pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
+ if (!status.extend_feature_present) {
+ printk(BIOS_ERR, "ME: Extend Feature not present\n");
+ return -1;
+ }
+
+ if (!status.extend_reg_valid) {
+ printk(BIOS_ERR, "ME: Extend Register not valid\n");
+ return -1;
+ }
+
+ switch (status.extend_reg_algorithm) {
+ case PCI_ME_EXT_SHA1:
+ count = 5;
+ printk(BIOS_DEBUG, "ME: Extend SHA-1: ");
+ break;
+ case PCI_ME_EXT_SHA256:
+ count = 8;
+ printk(BIOS_DEBUG, "ME: Extend SHA-256: ");
+ break;
+ default:
+ printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n",
+ status.extend_reg_algorithm);
+ return -1;
+ }
+
+ for (i = 0; i < count; ++i) {
+ extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
+ printk(BIOS_DEBUG, "%08x", extend[i]);
+ }
+ printk(BIOS_DEBUG, "\n");
+
+#if CONFIG_CHROMEOS
+ /* Save hash in NVS for the OS to verify */
+ chromeos_set_me_hash(extend, count);
+#endif
+
+ return 0;
+}
+
+/* Hide the ME virtual PCI devices */
+static void intel_me_hide(device_t dev)
+{
+ dev->enabled = 0;
+ pch_enable(dev);
+}
+
+/* Check whether ME is present and do basic init */
+static void intel_me_init(device_t dev)
+{
+ me_bios_path path = intel_me_path(dev);
+
+ /* Do initial setup and determine the BIOS path */
+ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
+
+ switch (path) {
+ case ME_S3WAKE_BIOS_PATH:
+ intel_me_hide(dev);
+ break;
+
+ case ME_NORMAL_BIOS_PATH:
+ /* Validate the extend register */
+ if (intel_me_extend_valid(dev) < 0)
+ break; /* TODO: force recovery mode */
+
+ /* Prepare MEI MMIO interface */
+ if (intel_mei_setup(dev) < 0)
+ break;
+
+ /*
+ * Leave the ME unlocked in this path.
+ * It will be locked via SMI command later.
+ */
+ break;
+
+ case ME_ERROR_BIOS_PATH:
+ case ME_RECOVERY_BIOS_PATH:
+ case ME_DISABLE_BIOS_PATH:
+ case ME_FIRMWARE_UPDATE_BIOS_PATH:
+ break;
+ }
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = intel_me_init,
+ .scan_bus = scan_static_bus,
+ .ops_pci = &pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b64,
+ 0 };
+
+
+static const struct pci_driver intel_me __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids
+};
+
+#endif /* !__SMM__ */
diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h
new file mode 100644
index 0000000..6e2062d
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/me.h
@@ -0,0 +1,374 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _INTEL_ME_H
+#define _INTEL_ME_H
+
+#define ME_RETRY 100000 /* 1 second */
+#define ME_DELAY 10 /* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_DEVICE PCI_DEV(0,0,0)
+#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
+#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
+
+#define PCI_ME_HFS 0x40
+#define ME_HFS_CWS_RESET 0
+#define ME_HFS_CWS_INIT 1
+#define ME_HFS_CWS_REC 2
+#define ME_HFS_CWS_NORMAL 5
+#define ME_HFS_CWS_WAIT 6
+#define ME_HFS_CWS_TRANS 7
+#define ME_HFS_CWS_INVALID 8
+#define ME_HFS_STATE_PREBOOT 0
+#define ME_HFS_STATE_M0_UMA 1
+#define ME_HFS_STATE_M3 4
+#define ME_HFS_STATE_M0 5
+#define ME_HFS_STATE_BRINGUP 6
+#define ME_HFS_STATE_ERROR 7
+#define ME_HFS_ERROR_NONE 0
+#define ME_HFS_ERROR_UNCAT 1
+#define ME_HFS_ERROR_IMAGE 3
+#define ME_HFS_ERROR_DEBUG 4
+#define ME_HFS_MODE_NORMAL 0
+#define ME_HFS_MODE_DEBUG 2
+#define ME_HFS_MODE_DIS 3
+#define ME_HFS_MODE_OVER_JMPR 4
+#define ME_HFS_MODE_OVER_MEI 5
+#define ME_HFS_BIOS_DRAM_ACK 1
+#define ME_HFS_ACK_NO_DID 0
+#define ME_HFS_ACK_RESET 1
+#define ME_HFS_ACK_PWR_CYCLE 2
+#define ME_HFS_ACK_S3 3
+#define ME_HFS_ACK_S4 4
+#define ME_HFS_ACK_S5 5
+#define ME_HFS_ACK_GBL_RESET 6
+#define ME_HFS_ACK_CONTINUE 7
+
+struct me_hfs {
+ u32 working_state: 4;
+ u32 mfg_mode: 1;
+ u32 fpt_bad: 1;
+ u32 operation_state: 3;
+ u32 fw_init_complete: 1;
+ u32 ft_bup_ld_flr: 1;
+ u32 update_in_progress: 1;
+ u32 error_code: 4;
+ u32 operation_mode: 4;
+ u32 reserved: 4;
+ u32 boot_options_present: 1;
+ u32 ack_data: 3;
+ u32 bios_msg_ack: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_UMA 0x44
+
+struct me_uma {
+ u32 size: 6;
+ u32 reserved_1: 10;
+ u32 valid: 1;
+ u32 reserved_0: 14;
+ u32 set_to_one: 1;
+} __attribute__ ((packed));
+
+#define PCI_ME_H_GS 0x4c
+#define ME_INIT_DONE 1
+#define ME_INIT_STATUS_SUCCESS 0
+#define ME_INIT_STATUS_NOMEM 1
+#define ME_INIT_STATUS_ERROR 2
+
+struct me_did {
+ u32 uma_base: 16;
+ u32 reserved: 8;
+ u32 status: 4;
+ u32 init_done: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_GMES 0x48
+#define ME_GMES_PHASE_ROM 0
+#define ME_GMES_PHASE_BUP 1
+#define ME_GMES_PHASE_UKERNEL 2
+#define ME_GMES_PHASE_POLICY 3
+#define ME_GMES_PHASE_MODULE 4
+#define ME_GMES_PHASE_UNKNOWN 5
+#define ME_GMES_PHASE_HOST 6
+
+struct me_gmes {
+ u32 bist_in_prog : 1;
+ u32 icc_prog_sts : 2;
+ u32 invoke_mebx : 1;
+ u32 cpu_replaced_sts : 1;
+ u32 mbp_rdy : 1;
+ u32 mfs_failure : 1;
+ u32 warm_rst_req_for_df : 1;
+ u32 cpu_replaced_valid : 1;
+ u32 reserved_1 : 2;
+ u32 fw_upd_ipu : 1;
+ u32 reserved_2 : 4;
+ u32 current_state: 8;
+ u32 current_pmevent: 4;
+ u32 progress_code: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_HERES 0xbc
+#define PCI_ME_EXT_SHA1 0x00
+#define PCI_ME_EXT_SHA256 0x02
+#define PCI_ME_HER(x) (0xc0+(4*(x)))
+
+struct me_heres {
+ u32 extend_reg_algorithm: 4;
+ u32 reserved: 26;
+ u32 extend_feature_present: 1;
+ u32 extend_reg_valid: 1;
+} __attribute__ ((packed));
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW 0x00
+#define MEI_H_CSR 0x04
+#define MEI_ME_CB_RW 0x08
+#define MEI_ME_CSR_HA 0x0c
+
+struct mei_csr {
+ u32 interrupt_enable: 1;
+ u32 interrupt_status: 1;
+ u32 interrupt_generate: 1;
+ u32 ready: 1;
+ u32 reset: 1;
+ u32 reserved: 3;
+ u32 buffer_read_ptr: 8;
+ u32 buffer_write_ptr: 8;
+ u32 buffer_depth: 8;
+} __attribute__ ((packed));
+
+#define MEI_ADDRESS_CORE 0x01
+#define MEI_ADDRESS_AMT 0x02
+#define MEI_ADDRESS_RESERVED 0x03
+#define MEI_ADDRESS_WDT 0x04
+#define MEI_ADDRESS_MKHI 0x07
+#define MEI_ADDRESS_ICC 0x08
+#define MEI_ADDRESS_THERMAL 0x09
+
+#define MEI_HOST_ADDRESS 0
+
+struct mei_header {
+ u32 client_address: 8;
+ u32 host_address: 8;
+ u32 length: 9;
+ u32 reserved: 6;
+ u32 is_complete: 1;
+} __attribute__ ((packed));
+
+#define MKHI_GROUP_ID_CBM 0x00
+#define MKHI_GROUP_ID_FWCAPS 0x03
+#define MKHI_GROUP_ID_MDES 0x08
+#define MKHI_GROUP_ID_GEN 0xff
+
+#define MKHI_GLOBAL_RESET 0x0b
+
+#define MKHI_FWCAPS_GET_RULE 0x02
+
+#define MKHI_MDES_ENABLE 0x09
+
+#define MKHI_GET_FW_VERSION 0x02
+#define MKHI_SET_UMA 0x08
+#define MKHI_END_OF_POST 0x0c
+#define MKHI_FEATURE_OVERRIDE 0x14
+
+struct mkhi_header {
+ u32 group_id: 8;
+ u32 command: 7;
+ u32 is_response: 1;
+ u32 reserved: 8;
+ u32 result: 8;
+} __attribute__ ((packed));
+
+struct me_fw_version {
+ u16 code_minor;
+ u16 code_major;
+ u16 code_build_number;
+ u16 code_hot_fix;
+ u16 recovery_minor;
+ u16 recovery_major;
+ u16 recovery_build_number;
+ u16 recovery_hot_fix;
+} __attribute__ ((packed));
+
+
+#define HECI_EOP_STATUS_SUCCESS 0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET 0x01
+
+#define GLOBAL_RESET_BIOS_MRC 0x01
+#define GLOBAL_RESET_BIOS_POST 0x02
+#define GLOBAL_RESET_MEBX 0x03
+
+struct me_global_reset {
+ u8 request_origin;
+ u8 reset_type;
+} __attribute__ ((packed));
+
+typedef enum {
+ ME_NORMAL_BIOS_PATH,
+ ME_S3WAKE_BIOS_PATH,
+ ME_ERROR_BIOS_PATH,
+ ME_RECOVERY_BIOS_PATH,
+ ME_DISABLE_BIOS_PATH,
+ ME_FIRMWARE_UPDATE_BIOS_PATH,
+} me_bios_path;
+
+/* Defined in me_status.c for both romstage and ramstage */
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
+
+#ifdef __PRE_RAM__
+void intel_early_me_status(void);
+int intel_early_me_init(void);
+int intel_early_me_uma_size(void);
+int intel_early_me_init_done(u8 status);
+#endif
+
+#ifdef __SMM__
+void intel_me_finalize_smm(void);
+void intel_me8_finalize_smm(void);
+#endif
+typedef struct {
+ u32 major_version : 16;
+ u32 minor_version : 16;
+ u32 hotfix_version : 16;
+ u32 build_version : 16;
+} __attribute__ ((packed)) mbp_fw_version_name;
+
+typedef struct {
+ u8 num_icc_profiles;
+ u8 icc_profile_soft_strap;
+ u8 icc_profile_index;
+ u8 reserved;
+ u32 register_lock_mask[3];
+} __attribute__ ((packed)) mbp_icc_profile;
+
+typedef struct {
+ u32 full_net : 1;
+ u32 std_net : 1;
+ u32 manageability : 1;
+ u32 small_business : 1;
+ u32 l3manageability : 1;
+ u32 intel_at : 1;
+ u32 intel_cls : 1;
+ u32 reserved : 3;
+ u32 intel_mpc : 1;
+ u32 icc_over_clocking : 1;
+ u32 pavp : 1;
+ u32 reserved_1 : 4;
+ u32 ipv6 : 1;
+ u32 kvm : 1;
+ u32 och : 1;
+ u32 vlan : 1;
+ u32 tls : 1;
+ u32 reserved_4 : 1;
+ u32 wlan : 1;
+ u32 reserved_5 : 8;
+} __attribute__ ((packed)) mefwcaps_sku;
+
+typedef struct {
+ u16 lock_state : 1;
+ u16 authenticate_module : 1;
+ u16 s3authentication : 1;
+ u16 flash_wear_out : 1;
+ u16 flash_variable_security : 1;
+ u16 wwan3gpresent : 1;
+ u16 wwan3goob : 1;
+ u16 reserved : 9;
+} __attribute__ ((packed)) tdt_state_flag;
+
+typedef struct {
+ u8 state;
+ u8 last_theft_trigger;
+ tdt_state_flag flags;
+} __attribute__ ((packed)) tdt_state_info;
+
+typedef struct {
+ u32 platform_target_usage_type : 4;
+ u32 platform_target_market_type : 2;
+ u32 super_sku : 1;
+ u32 reserved : 1;
+ u32 intel_me_fw_image_type : 4;
+ u32 platform_brand : 4;
+ u32 reserved_1 : 16;
+} __attribute__ ((packed)) platform_type_rule_data;
+
+typedef struct {
+ mefwcaps_sku fw_capabilities;
+ u8 available;
+} mbp_fw_caps;
+
+typedef struct {
+ u16 device_id;
+ u16 fuse_test_flags;
+ u32 umchid[4];
+} __attribute__ ((packed)) mbp_rom_bist_data;
+
+typedef struct {
+ u32 key[8];
+} mbp_platform_key;
+
+typedef struct {
+ platform_type_rule_data rule_data;
+ u8 available;
+} mbp_plat_type;
+
+typedef struct {
+ mbp_fw_version_name fw_version_name;
+ mbp_fw_caps fw_caps_sku;
+ mbp_rom_bist_data rom_bist_data;
+ mbp_platform_key platform_key;
+ mbp_plat_type fw_plat_type;
+ mbp_icc_profile icc_profile;
+ tdt_state_info at_state;
+ u32 mfsintegrity;
+} me_bios_payload;
+
+typedef struct {
+ u32 mbp_size : 8;
+ u32 num_entries : 8;
+ u32 rsvd : 16;
+} __attribute__ ((packed)) mbp_header;
+
+typedef struct {
+ u32 app_id : 8;
+ u32 item_id : 8;
+ u32 length : 8;
+ u32 rsvd : 8;
+} __attribute__ ((packed)) mbp_item_header;
+
+struct me_fwcaps {
+ u32 id;
+ u8 length;
+ mefwcaps_sku caps_sku;
+ u8 reserved[3];
+} __attribute__ ((packed));
+
+#endif /* _INTEL_ME_H */
diff --git a/src/southbridge/intel/ibexpeak/me_8.x.c b/src/southbridge/intel/ibexpeak/me_8.x.c
new file mode 100644
index 0000000..9b6d11b
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/me_8.x.c
@@ -0,0 +1,935 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This is a ramstage driver for the Intel Management Engine found in the
+ * 6-series chipset. It handles the required boot-time messages over the
+ * MMIO-based Management Engine Interface to tell the ME that the BIOS is
+ * finished with POST. Additional messages are defined for debug but are
+ * not used unless the console loglevel is high enough.
+ */
+
+#include <arch/acpi.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include <string.h>
+#include <delay.h>
+#include <elog.h>
+
+#ifdef __SMM__
+#include <northbridge/intel/nehalem/pcie_config.c>
+#else
+# include <device/device.h>
+# include <device/pci.h>
+#endif
+
+#include "me.h"
+#include "pch.h"
+
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
+
+#ifndef __SMM__
+/* Path that the BIOS should take based on ME state */
+static const char *me_bios_path_values[] = {
+ [ME_NORMAL_BIOS_PATH] = "Normal",
+ [ME_S3WAKE_BIOS_PATH] = "S3 Wake",
+ [ME_ERROR_BIOS_PATH] = "Error",
+ [ME_RECOVERY_BIOS_PATH] = "Recovery",
+ [ME_DISABLE_BIOS_PATH] = "Disable",
+ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
+};
+static int intel_me_read_mbp(me_bios_payload *mbp_data);
+#endif
+
+/* MMIO base address for MEI interface */
+static u32 mei_base_address;
+
+#if CONFIG_DEBUG_INTEL_ME
+static void mei_dump(void *ptr, int dword, int offset, const char *type)
+{
+ struct mei_csr *csr;
+
+ printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
+
+ switch (offset) {
+ case MEI_H_CSR:
+ case MEI_ME_CSR_HA:
+ csr = ptr;
+ if (!csr) {
+ printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword);
+ break;
+ }
+ printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u "
+ "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth,
+ csr->buffer_read_ptr, csr->buffer_write_ptr,
+ csr->ready, csr->reset, csr->interrupt_generate,
+ csr->interrupt_status, csr->interrupt_enable);
+ break;
+ case MEI_ME_CB_RW:
+ case MEI_H_CB_WW:
+ printk(BIOS_SPEW, "CB: 0x%08x\n", dword);
+ break;
+ default:
+ printk(BIOS_SPEW, "0x%08x\n", offset);
+ break;
+ }
+}
+#else
+# define mei_dump(ptr,dword,offset,type) do {} while (0)
+#endif
+
+/*
+ * ME/MEI access helpers using memcpy to avoid aliasing.
+ */
+
+static inline void mei_read_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = read32(mei_base_address + offset);
+ memcpy(ptr, &dword, sizeof(dword));
+ mei_dump(ptr, dword, offset, "READ");
+}
+
+static inline void mei_write_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = 0;
+ memcpy(&dword, ptr, sizeof(dword));
+ write32(mei_base_address + offset, dword);
+ mei_dump(ptr, dword, offset, "WRITE");
+}
+
+#ifndef __SMM__
+static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+{
+ u32 dword = pci_read_config32(dev, offset);
+ memcpy(ptr, &dword, sizeof(dword));
+ mei_dump(ptr, dword, offset, "PCI READ");
+}
+#endif
+
+static inline void read_host_csr(struct mei_csr *csr)
+{
+ mei_read_dword_ptr(csr, MEI_H_CSR);
+}
+
+static inline void write_host_csr(struct mei_csr *csr)
+{
+ mei_write_dword_ptr(csr, MEI_H_CSR);
+}
+
+static inline void read_me_csr(struct mei_csr *csr)
+{
+ mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
+}
+
+static inline void write_cb(u32 dword)
+{
+ write32(mei_base_address + MEI_H_CB_WW, dword);
+ mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
+}
+
+static inline u32 read_cb(void)
+{
+ u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
+ return dword;
+}
+
+/* Wait for ME ready bit to be asserted */
+static int mei_wait_for_me_ready(void)
+{
+ struct mei_csr me;
+ unsigned try = ME_RETRY;
+
+ while (try--) {
+ read_me_csr(&me);
+ if (me.ready)
+ return 0;
+ udelay(ME_DELAY);
+ }
+
+ printk(BIOS_ERR, "ME: failed to become ready\n");
+ return -1;
+}
+
+static void mei_reset(void)
+{
+ struct mei_csr host;
+
+ if (mei_wait_for_me_ready() < 0)
+ return;
+
+ /* Reset host and ME circular buffers for next message */
+ read_host_csr(&host);
+ host.reset = 1;
+ host.interrupt_generate = 1;
+ write_host_csr(&host);
+
+ if (mei_wait_for_me_ready() < 0)
+ return;
+
+ /* Re-init and indicate host is ready */
+ read_host_csr(&host);
+ host.interrupt_generate = 1;
+ host.ready = 1;
+ host.reset = 0;
+ write_host_csr(&host);
+}
+
+static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
+ void *req_data)
+{
+ struct mei_csr host;
+ unsigned ndata, n;
+ u32 *data;
+
+ /* Number of dwords to write, ignoring MKHI */
+ ndata = mei->length >> 2;
+
+ /* Pad non-dword aligned request message length */
+ if (mei->length & 3)
+ ndata++;
+ if (!ndata) {
+ printk(BIOS_DEBUG, "ME: request does not include MKHI\n");
+ return -1;
+ }
+ ndata++; /* Add MEI header */
+
+ /*
+ * Make sure there is still room left in the circular buffer.
+ * Reset the buffer pointers if the requested message will not fit.
+ */
+ read_host_csr(&host);
+ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
+ printk(BIOS_ERR, "ME: circular buffer full, resetting...\n");
+ mei_reset();
+ read_host_csr(&host);
+ }
+
+ /*
+ * This implementation does not handle splitting large messages
+ * across multiple transactions. Ensure the requested length
+ * will fit in the available circular buffer depth.
+ */
+ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
+ printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n",
+ ndata + 2, host.buffer_depth);
+ return -1;
+ }
+
+ /* Write MEI header */
+ mei_write_dword_ptr(mei, MEI_H_CB_WW);
+ ndata--;
+
+ /* Write MKHI header */
+ mei_write_dword_ptr(mkhi, MEI_H_CB_WW);
+ ndata--;
+
+ /* Write message data */
+ data = req_data;
+ for (n = 0; n < ndata; ++n)
+ write_cb(*data++);
+
+ /* Generate interrupt to the ME */
+ read_host_csr(&host);
+ host.interrupt_generate = 1;
+ write_host_csr(&host);
+
+ /* Make sure ME is ready after sending request data */
+ return mei_wait_for_me_ready();
+}
+
+static int mei_recv_msg(struct mkhi_header *mkhi,
+ void *rsp_data, int rsp_bytes)
+{
+ struct mei_header mei_rsp;
+ struct mkhi_header mkhi_rsp;
+ struct mei_csr me, host;
+ unsigned ndata, n/*, me_data_len*/;
+ unsigned expected;
+ u32 *data;
+
+ /* Total number of dwords to read from circular buffer */
+ expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2;
+ if (rsp_bytes & 3)
+ expected++;
+
+ /*
+ * The interrupt status bit does not appear to indicate that the
+ * message has actually been received. Instead we wait until the
+ * expected number of dwords are present in the circular buffer.
+ */
+ for (n = ME_RETRY; n; --n) {
+ read_me_csr(&me);
+ if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!n) {
+ printk(BIOS_ERR, "ME: timeout waiting for data: expected "
+ "%u, available %u\n", expected,
+ me.buffer_write_ptr - me.buffer_read_ptr);
+ return -1;
+ }
+
+ /* Read and verify MEI response header from the ME */
+ mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
+ if (!mei_rsp.is_complete) {
+ printk(BIOS_ERR, "ME: response is not complete\n");
+ return -1;
+ }
+
+ /* Handle non-dword responses and expect at least MKHI header */
+ ndata = mei_rsp.length >> 2;
+ if (mei_rsp.length & 3)
+ ndata++;
+ if (ndata != (expected - 1)) {
+ printk(BIOS_ERR, "ME: response is missing data %d != %d\n",
+ ndata, (expected - 1));
+ return -1;
+ }
+
+ /* Read and verify MKHI response header from the ME */
+ mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW);
+ if (!mkhi_rsp.is_response ||
+ mkhi->group_id != mkhi_rsp.group_id ||
+ mkhi->command != mkhi_rsp.command) {
+ printk(BIOS_ERR, "ME: invalid response, group %u ?= %u,"
+ "command %u ?= %u, is_response %u\n", mkhi->group_id,
+ mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
+ mkhi_rsp.is_response);
+ return -1;
+ }
+ ndata--; /* MKHI header has been read */
+
+ /* Make sure caller passed a buffer with enough space */
+ if (ndata != (rsp_bytes >> 2)) {
+ printk(BIOS_ERR, "ME: not enough room in response buffer: "
+ "%u != %u\n", ndata, rsp_bytes >> 2);
+ return -1;
+ }
+
+ /* Read response data from the circular buffer */
+ data = rsp_data;
+ for (n = 0; n < ndata; ++n)
+ *data++ = read_cb();
+
+ /* Tell the ME that we have consumed the response */
+ read_host_csr(&host);
+ host.interrupt_status = 1;
+ host.interrupt_generate = 1;
+ write_host_csr(&host);
+
+ return mei_wait_for_me_ready();
+}
+
+static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
+ void *req_data, void *rsp_data, int rsp_bytes)
+{
+ if (mei_send_msg(mei, mkhi, req_data) < 0)
+ return -1;
+ if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0)
+ return -1;
+ return 0;
+}
+
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__)
+static inline void print_cap(const char *name, int state)
+{
+ printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
+ name, state ? " en" : "dis");
+}
+
+static void me_print_fw_version(mbp_fw_version_name *vers_name)
+{
+ if (!vers_name->major_version) {
+ printk(BIOS_ERR, "ME: mbp missing version report\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n",
+ vers_name->major_version, vers_name->minor_version,
+ vers_name->hotfix_version, vers_name->build_version);
+}
+
+/* Get ME Firmware Capabilities */
+static int mkhi_get_fwcaps(mefwcaps_sku *cap)
+{
+ u32 rule_id = 0;
+ struct me_fwcaps cap_msg;
+ struct mkhi_header mkhi = {
+ .group_id = MKHI_GROUP_ID_FWCAPS,
+ .command = MKHI_FWCAPS_GET_RULE,
+ };
+ struct mei_header mei = {
+ .is_complete = 1,
+ .host_address = MEI_HOST_ADDRESS,
+ .client_address = MEI_ADDRESS_MKHI,
+ .length = sizeof(mkhi) + sizeof(rule_id),
+ };
+
+ /* Send request and wait for response */
+ if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg))
+ < 0) {
+ printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
+ return -1;
+ }
+ *cap = cap_msg.caps_sku;
+ return 0;
+}
+
+/* Get ME Firmware Capabilities */
+static void me_print_fwcaps(mbp_fw_caps *caps_section)
+{
+ mefwcaps_sku *cap = &caps_section->fw_capabilities;
+ if (!caps_section->available) {
+ printk(BIOS_ERR, "ME: mbp missing fwcaps report\n");
+ if (mkhi_get_fwcaps(cap))
+ return;
+ }
+
+ print_cap("Full Network manageability", cap->full_net);
+ print_cap("Regular Network manageability", cap->std_net);
+ print_cap("Manageability", cap->manageability);
+ print_cap("Small business technology", cap->small_business);
+ print_cap("Level III manageability", cap->l3manageability);
+ print_cap("IntelR Anti-Theft (AT)", cap->intel_at);
+ print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
+ print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
+ print_cap("ICC Over Clocking", cap->icc_over_clocking);
+ print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+ print_cap("IPV6", cap->ipv6);
+ print_cap("KVM Remote Control (KVM)", cap->kvm);
+ print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
+ print_cap("Virtual LAN (VLAN)", cap->vlan);
+ print_cap("TLS", cap->tls);
+ print_cap("Wireless LAN (WLAN)", cap->wlan);
+}
+#endif
+
+#if CONFIG_CHROMEOS && 0 /* DISABLED */
+/* Tell ME to issue a global reset */
+static int mkhi_global_reset(void)
+{
+ struct me_global_reset reset = {
+ .request_origin = GLOBAL_RESET_BIOS_POST,
+ .reset_type = CBM_RR_GLOBAL_RESET,
+ };
+ struct mkhi_header mkhi = {
+ .group_id = MKHI_GROUP_ID_CBM,
+ .command = MKHI_GLOBAL_RESET,
+ };
+ struct mei_header mei = {
+ .is_complete = 1,
+ .length = sizeof(mkhi) + sizeof(reset),
+ .host_address = MEI_HOST_ADDRESS,
+ .client_address = MEI_ADDRESS_MKHI,
+ };
+
+ /* Send request and wait for response */
+ printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
+ if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
+ /* No response means reset will happen shortly... */
+ hlt();
+ }
+
+ /* If the ME responded it rejected the reset request */
+ printk(BIOS_ERR, "ME: Global Reset failed\n");
+ return -1;
+}
+#endif
+
+#ifdef __SMM__
+
+/* Send END OF POST message to the ME */
+static int mkhi_end_of_post(void)
+{
+ struct mkhi_header mkhi = {
+ .group_id = MKHI_GROUP_ID_GEN,
+ .command = MKHI_END_OF_POST,
+ };
+ struct mei_header mei = {
+ .is_complete = 1,
+ .host_address = MEI_HOST_ADDRESS,
+ .client_address = MEI_ADDRESS_MKHI,
+ .length = sizeof(mkhi),
+ };
+
+ u32 eop_ack;
+
+ /* Send request and wait for response */
+ printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
+ if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) {
+ printk(BIOS_ERR, "ME: END OF POST message failed\n");
+ return -1;
+ }
+
+ printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack);
+ return 0;
+}
+
+void intel_me8_finalize_smm(void)
+{
+ struct me_hfs hfs;
+ u32 reg32;
+
+ mei_base_address =
+ pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+
+ /* S3 path will have hidden this device already */
+ if (!mei_base_address || mei_base_address == 0xfffffff0)
+ return;
+
+ /* Make sure ME is in a mode that expects EOP */
+ reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ memcpy(&hfs, ®32, sizeof(u32));
+
+ /* Abort and leave device alone if not normal mode */
+ if (hfs.fpt_bad ||
+ hfs.working_state != ME_HFS_CWS_NORMAL ||
+ hfs.operation_mode != ME_HFS_MODE_NORMAL)
+ return;
+
+ /* Try to send EOP command so ME stops accepting other commands */
+ mkhi_end_of_post();
+
+ /* Make sure IO is disabled */
+ reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+
+ /* Hide the PCI device */
+ RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+}
+
+#else /* !__SMM__ */
+
+/* Determine the path that we should take based on ME status */
+static me_bios_path intel_me_path(device_t dev)
+{
+ me_bios_path path = ME_DISABLE_BIOS_PATH;
+ struct me_hfs hfs;
+ struct me_gmes gmes;
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* S3 wake skips all MKHI messages */
+ if (acpi_slp_type == 3) {
+ return ME_S3WAKE_BIOS_PATH;
+ }
+#endif
+
+ pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
+
+ /* Check and dump status */
+ intel_me_status(&hfs, &gmes);
+
+ /* Check Current Working State */
+ switch (hfs.working_state) {
+ case ME_HFS_CWS_NORMAL:
+ path = ME_NORMAL_BIOS_PATH;
+ break;
+ case ME_HFS_CWS_REC:
+ path = ME_RECOVERY_BIOS_PATH;
+ break;
+ default:
+ path = ME_DISABLE_BIOS_PATH;
+ break;
+ }
+
+ /* Check Current Operation Mode */
+ switch (hfs.operation_mode) {
+ case ME_HFS_MODE_NORMAL:
+ break;
+ case ME_HFS_MODE_DEBUG:
+ case ME_HFS_MODE_DIS:
+ case ME_HFS_MODE_OVER_JMPR:
+ case ME_HFS_MODE_OVER_MEI:
+ default:
+ path = ME_DISABLE_BIOS_PATH;
+ break;
+ }
+
+ /* Check for any error code and valid firmware and MBP */
+ if (hfs.error_code || hfs.fpt_bad)
+ path = ME_ERROR_BIOS_PATH;
+
+ /* Check if the MBP is ready */
+ if (!gmes.mbp_rdy) {
+ printk(BIOS_CRIT, "%s: mbp is not ready!\n",
+ __FUNCTION__);
+ path = ME_ERROR_BIOS_PATH;
+ }
+
+#if CONFIG_ELOG
+ if (path != ME_NORMAL_BIOS_PATH) {
+ struct elog_event_data_me_extended data = {
+ .current_working_state = hfs.working_state,
+ .operation_state = hfs.operation_state,
+ .operation_mode = hfs.operation_mode,
+ .error_code = hfs.error_code,
+ .progress_code = gmes.progress_code,
+ .current_pmevent = gmes.current_pmevent,
+ .current_state = gmes.current_state,
+ };
+ elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path);
+ elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT,
+ &data, sizeof(data));
+ }
+#endif
+
+ return path;
+}
+
+/* Prepare ME for MEI messages */
+static int intel_mei_setup(device_t dev)
+{
+ struct resource *res;
+ struct mei_csr host;
+ u32 reg32;
+
+ /* Find the MMIO base for the ME interface */
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res || res->base == 0 || res->size == 0) {
+ printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
+ return -1;
+ }
+ mei_base_address = res->base;
+
+ /* Ensure Memory and Bus Master bits are set */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Clean up status for next message */
+ read_host_csr(&host);
+ host.interrupt_generate = 1;
+ host.ready = 1;
+ host.reset = 0;
+ write_host_csr(&host);
+
+ return 0;
+}
+
+/* Read the Extend register hash of ME firmware */
+static int intel_me_extend_valid(device_t dev)
+{
+ struct me_heres status;
+ u32 extend[8] = {0};
+ int i, count = 0;
+
+ pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
+ if (!status.extend_feature_present) {
+ printk(BIOS_ERR, "ME: Extend Feature not present\n");
+ return -1;
+ }
+
+ if (!status.extend_reg_valid) {
+ printk(BIOS_ERR, "ME: Extend Register not valid\n");
+ return -1;
+ }
+
+ switch (status.extend_reg_algorithm) {
+ case PCI_ME_EXT_SHA1:
+ count = 5;
+ printk(BIOS_DEBUG, "ME: Extend SHA-1: ");
+ break;
+ case PCI_ME_EXT_SHA256:
+ count = 8;
+ printk(BIOS_DEBUG, "ME: Extend SHA-256: ");
+ break;
+ default:
+ printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n",
+ status.extend_reg_algorithm);
+ return -1;
+ }
+
+ for (i = 0; i < count; ++i) {
+ extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
+ printk(BIOS_DEBUG, "%08x", extend[i]);
+ }
+ printk(BIOS_DEBUG, "\n");
+
+#if CONFIG_CHROMEOS
+ /* Save hash in NVS for the OS to verify */
+ chromeos_set_me_hash(extend, count);
+#endif
+
+ return 0;
+}
+
+/* Hide the ME virtual PCI devices */
+static void intel_me_hide(device_t dev)
+{
+ dev->enabled = 0;
+ pch_enable(dev);
+}
+
+/* Check whether ME is present and do basic init */
+static void intel_me_init(device_t dev)
+{
+ me_bios_path path = intel_me_path(dev);
+ me_bios_payload mbp_data;
+
+ /* Do initial setup and determine the BIOS path */
+ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
+
+ switch (path) {
+ case ME_S3WAKE_BIOS_PATH:
+ intel_me_hide(dev);
+ break;
+
+ case ME_NORMAL_BIOS_PATH:
+ /* Validate the extend register */
+ if (intel_me_extend_valid(dev) < 0)
+ break; /* TODO: force recovery mode */
+
+ /* Prepare MEI MMIO interface */
+ if (intel_mei_setup(dev) < 0)
+ break;
+
+ if(intel_me_read_mbp(&mbp_data))
+ break;
+
+#if CONFIG_CHROMEOS && 0 /* DISABLED */
+ /*
+ * Unlock ME in recovery mode.
+ */
+ if (recovery_mode_enabled()) {
+ /* Unlock ME flash region */
+ mkhi_hmrfpo_enable();
+
+ /* Issue global reset */
+ mkhi_global_reset();
+ return;
+ }
+#endif
+
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+ me_print_fw_version(&mbp_data.fw_version_name);
+ me_print_fwcaps(&mbp_data.fw_caps_sku);
+#endif
+
+ /*
+ * Leave the ME unlocked in this path.
+ * It will be locked via SMI command later.
+ */
+ break;
+
+ case ME_ERROR_BIOS_PATH:
+ case ME_RECOVERY_BIOS_PATH:
+ case ME_DISABLE_BIOS_PATH:
+ case ME_FIRMWARE_UPDATE_BIOS_PATH:
+ break;
+ }
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = intel_me_init,
+ .scan_bus = scan_static_bus,
+ .ops_pci = &pci_ops,
+};
+
+static const struct pci_driver intel_me __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x1e3a,
+};
+
+/******************************************************************************
+ * */
+static u32 me_to_host_words_pending(void)
+{
+ struct mei_csr me;
+ read_me_csr(&me);
+ if (!me.ready)
+ return 0;
+ return (me.buffer_write_ptr - me.buffer_read_ptr) &
+ (me.buffer_depth - 1);
+}
+
+#if 0
+/* This function is not yet being used, keep it in for the future. */
+static u32 host_to_me_words_room(void)
+{
+ struct mei_csr csr;
+
+ read_me_csr(&csr);
+ if (!csr.ready)
+ return 0;
+
+ read_host_csr(&csr);
+ return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) &
+ (csr.buffer_depth - 1);
+}
+#endif
+/*
+ * mbp seems to be following its own flow, let's retrieve it in a dedicated
+ * function.
+ */
+static int intel_me_read_mbp(me_bios_payload *mbp_data)
+{
+ mbp_header mbp_hdr;
+ mbp_item_header mbp_item_hdr;
+ u32 me2host_pending;
+ u32 mbp_item_id;
+ struct mei_csr host;
+
+ me2host_pending = me_to_host_words_pending();
+ if (!me2host_pending) {
+ printk(BIOS_ERR, "ME: no mbp data!\n");
+ return -1;
+ }
+
+ /* we know for sure that at least the header is there */
+ mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW);
+
+ if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) ||
+ (me2host_pending < mbp_hdr.mbp_size)) {
+ printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words"
+ " buffer contains %d words\n",
+ mbp_hdr.num_entries, mbp_hdr.mbp_size,
+ me2host_pending);
+ return -1;
+ }
+
+ me2host_pending--;
+ memset(mbp_data, 0, sizeof(*mbp_data));
+
+ while (mbp_hdr.num_entries--) {
+ u32* copy_addr;
+ u32 copy_size, buffer_room;
+ void *p;
+
+ if (!me2host_pending) {
+ printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n",
+ mbp_hdr.num_entries + 1);
+ return -1;
+ }
+
+ mei_read_dword_ptr(&mbp_item_hdr, MEI_ME_CB_RW);
+
+ if (mbp_item_hdr.length > me2host_pending) {
+ printk(BIOS_ERR, "ME: insufficient mbp data %d "
+ "entries to go!\n",
+ mbp_hdr.num_entries + 1);
+ return -1;
+ }
+
+ me2host_pending -= mbp_item_hdr.length;
+
+ mbp_item_id = (((u32)mbp_item_hdr.item_id) << 8) +
+ mbp_item_hdr.app_id;
+
+ copy_size = mbp_item_hdr.length - 1;
+
+#define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \
+ buffer_room = sizeof(mbp_data->field) / sizeof(u32); \
+ break; \
+ }
+
+ p = &mbp_item_hdr;
+ printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
+
+ switch(mbp_item_id) {
+ case 0x101:
+ SET_UP_COPY(fw_version_name);
+
+ case 0x102:
+ SET_UP_COPY(icc_profile);
+
+ case 0x103:
+ SET_UP_COPY(at_state);
+
+ case 0x201:
+ mbp_data->fw_caps_sku.available = 1;
+ SET_UP_COPY(fw_caps_sku.fw_capabilities);
+
+ case 0x301:
+ SET_UP_COPY(rom_bist_data);
+
+ case 0x401:
+ SET_UP_COPY(platform_key);
+
+ case 0x501:
+ mbp_data->fw_plat_type.available = 1;
+ SET_UP_COPY(fw_plat_type.rule_data);
+
+ case 0x601:
+ SET_UP_COPY(mfsintegrity);
+
+ default:
+ printk(BIOS_ERR, "ME: unknown mbp item id 0x%x!!!\n",
+ mbp_item_id);
+ return -1;
+ }
+
+ if (buffer_room != copy_size) {
+ printk(BIOS_ERR, "ME: buffer room %d != %d copy size"
+ " for item 0x%x!!!\n",
+ buffer_room, copy_size, mbp_item_id);
+ return -1;
+ }
+ while(copy_size--)
+ *copy_addr++ = read_cb();
+ }
+
+ read_host_csr(&host);
+ host.interrupt_generate = 1;
+ write_host_csr(&host);
+
+ {
+ int cntr = 0;
+ while(host.interrupt_generate) {
+ read_host_csr(&host);
+ cntr++;
+ }
+ printk(BIOS_SPEW, "ME: mbp read OK after %d cycles\n", cntr);
+ }
+
+ return 0;
+}
+
+#endif /* !__SMM__ */
diff --git a/src/southbridge/intel/ibexpeak/me_status.c b/src/southbridge/intel/ibexpeak/me_status.c
new file mode 100644
index 0000000..b2f38d6
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/me_status.c
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <console/console.h>
+#include "me.h"
+
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+/* HFS1[3:0] Current Working State Values */
+static const char *me_cws_values[] = {
+ [ME_HFS_CWS_RESET] = "Reset",
+ [ME_HFS_CWS_INIT] = "Initializing",
+ [ME_HFS_CWS_REC] = "Recovery",
+ [ME_HFS_CWS_NORMAL] = "Normal",
+ [ME_HFS_CWS_WAIT] = "Platform Disable Wait",
+ [ME_HFS_CWS_TRANS] = "OP State Transition",
+ [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In"
+};
+
+/* HFS1[8:6] Current Operation State Values */
+static const char *me_opstate_values[] = {
+ [ME_HFS_STATE_PREBOOT] = "Preboot",
+ [ME_HFS_STATE_M0_UMA] = "M0 with UMA",
+ [ME_HFS_STATE_M3] = "M3 without UMA",
+ [ME_HFS_STATE_M0] = "M0 without UMA",
+ [ME_HFS_STATE_BRINGUP] = "Bring up",
+ [ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
+};
+
+/* HFS[19:16] Current Operation Mode Values */
+static const char *me_opmode_values[] = {
+ [ME_HFS_MODE_NORMAL] = "Normal",
+ [ME_HFS_MODE_DEBUG] = "Debug",
+ [ME_HFS_MODE_DIS] = "Soft Temporary Disable",
+ [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
+ [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
+};
+
+/* HFS[15:12] Error Code Values */
+static const char *me_error_values[] = {
+ [ME_HFS_ERROR_NONE] = "No Error",
+ [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
+ [ME_HFS_ERROR_IMAGE] = "Image Failure",
+ [ME_HFS_ERROR_DEBUG] = "Debug Failure"
+};
+
+/* GMES[31:28] ME Progress Code */
+static const char *me_progress_values[] = {
+ [ME_GMES_PHASE_ROM] = "ROM Phase",
+ [ME_GMES_PHASE_BUP] = "BUP Phase",
+ [ME_GMES_PHASE_UKERNEL] = "uKernel Phase",
+ [ME_GMES_PHASE_POLICY] = "Policy Module",
+ [ME_GMES_PHASE_MODULE] = "Module Loading",
+ [ME_GMES_PHASE_UNKNOWN] = "Unknown",
+ [ME_GMES_PHASE_HOST] = "Host Communication"
+};
+
+/* GMES[27:24] Power Management Event */
+static const char *me_pmevent_values[] = {
+ [0x00] = "Clean Moff->Mx wake",
+ [0x01] = "Moff->Mx wake after an error",
+ [0x02] = "Clean global reset",
+ [0x03] = "Global reset after an error",
+ [0x04] = "Clean Intel ME reset",
+ [0x05] = "Intel ME reset due to exception",
+ [0x06] = "Pseudo-global reset",
+ [0x07] = "S0/M0->Sx/M3",
+ [0x08] = "Sx/M3->S0/M0",
+ [0x09] = "Non-power cycle reset",
+ [0x0a] = "Power cycle reset through M3",
+ [0x0b] = "Power cycle reset through Moff",
+ [0x0c] = "Sx/Mx->Sx/Moff"
+};
+
+/* Progress Code 0 states */
+static const char *me_progress_rom_values[] = {
+ [0x00] = "BEGIN",
+ [0x06] = "DISABLE"
+};
+
+/* Progress Code 1 states */
+static const char *me_progress_bup_values[] = {
+ [0x00] = "Initialization starts",
+ [0x01] = "Disable the host wake event",
+ [0x04] = "Flow determination start process",
+ [0x08] = "Error reading/matching the VSCC table in the descriptor",
+ [0x0a] = "Check to see if straps say ME DISABLED",
+ [0x0b] = "Timeout waiting for PWROK",
+ [0x0d] = "Possibly handle BUP manufacturing override strap",
+ [0x11] = "Bringup in M3",
+ [0x12] = "Bringup in M0",
+ [0x13] = "Flow detection error",
+ [0x15] = "M3 clock switching error",
+ [0x18] = "M3 kernel load",
+ [0x1c] = "T34 missing - cannot program ICC",
+ [0x1f] = "Waiting for DID BIOS message",
+ [0x20] = "Waiting for DID BIOS message failure",
+ [0x21] = "DID reported an error",
+ [0x22] = "Enabling UMA",
+ [0x23] = "Enabling UMA error",
+ [0x24] = "Sending DID Ack to BIOS",
+ [0x25] = "Sending DID Ack to BIOS error",
+ [0x26] = "Switching clocks in M0",
+ [0x27] = "Switching clocks in M0 error",
+ [0x28] = "ME in temp disable",
+ [0x32] = "M0 kernel load",
+};
+
+/* Progress Code 3 states */
+static const char *me_progress_policy_values[] = {
+ [0x00] = "Entery into Policy Module",
+ [0x03] = "Received S3 entry",
+ [0x04] = "Received S4 entry",
+ [0x05] = "Received S5 entry",
+ [0x06] = "Received UPD entry",
+ [0x07] = "Received PCR entry",
+ [0x08] = "Received NPCR entry",
+ [0x09] = "Received host wake",
+ [0x0a] = "Received AC<>DC switch",
+ [0x0b] = "Received DRAM Init Done",
+ [0x0c] = "VSCC Data not found for flash device",
+ [0x0d] = "VSCC Table is not valid",
+ [0x0e] = "Flash Partition Boundary is outside address space",
+ [0x0f] = "ME cannot access the chipset descriptor region",
+ [0x10] = "Required VSCC values for flash parts do not match",
+};
+#endif
+
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+{
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+ /* Check Current States */
+ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n",
+ hfs->fpt_bad ? "BAD" : "OK");
+ printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n",
+ hfs->ft_bup_ld_flr ? "YES" : "NO");
+ printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n",
+ hfs->fw_init_complete ? "YES" : "NO");
+ printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n",
+ hfs->mfg_mode ? "YES" : "NO");
+ printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n",
+ hfs->boot_options_present ? "YES" : "NO");
+ printk(BIOS_DEBUG, "ME: Update In Progress : %s\n",
+ hfs->update_in_progress ? "YES" : "NO");
+ printk(BIOS_DEBUG, "ME: Current Working State : %s\n",
+ me_cws_values[hfs->working_state]);
+ printk(BIOS_DEBUG, "ME: Current Operation State : %s\n",
+ me_opstate_values[hfs->operation_state]);
+ printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n",
+ me_opmode_values[hfs->operation_mode]);
+ printk(BIOS_DEBUG, "ME: Error Code : %s\n",
+ me_error_values[hfs->error_code]);
+ printk(BIOS_DEBUG, "ME: Progress Phase : %s\n",
+ me_progress_values[gmes->progress_code]);
+ printk(BIOS_DEBUG, "ME: Power Management Event : %s\n",
+ me_pmevent_values[gmes->current_pmevent]);
+
+ printk(BIOS_DEBUG, "ME: Progress Phase State : ");
+ switch (gmes->progress_code) {
+ case ME_GMES_PHASE_ROM: /* ROM Phase */
+ printk(BIOS_DEBUG, "%s",
+ me_progress_rom_values[gmes->current_state]);
+ break;
+
+ case ME_GMES_PHASE_BUP: /* Bringup Phase */
+ if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values)
+ && me_progress_bup_values[gmes->current_state])
+ printk(BIOS_DEBUG, "%s",
+ me_progress_bup_values[gmes->current_state]);
+ else
+ printk(BIOS_DEBUG, "0x%02x", gmes->current_state);
+ break;
+
+ case ME_GMES_PHASE_POLICY: /* Policy Module Phase */
+ if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values)
+ && me_progress_policy_values[gmes->current_state])
+ printk(BIOS_DEBUG, "%s",
+ me_progress_policy_values[gmes->current_state]);
+ else
+ printk(BIOS_DEBUG, "0x%02x", gmes->current_state);
+ break;
+
+ case ME_GMES_PHASE_HOST: /* Host Communication Phase */
+ if (!gmes->current_state)
+ printk(BIOS_DEBUG, "Host communication established");
+ else
+ printk(BIOS_DEBUG, "0x%02x", gmes->current_state);
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state);
+ }
+ printk(BIOS_DEBUG, "\n");
+#endif
+}
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
new file mode 100644
index 0000000..7b8b6c9
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "vendorcode/google/chromeos/gnvs.h"
+typedef struct {
+ /* Miscellaneous */
+ u16 osys; /* 0x00 - Operating System */
+ u8 smif; /* 0x02 - SMI function call ("TRAP") */
+ u8 prm0; /* 0x03 - SMI function call parameter */
+ u8 prm1; /* 0x04 - SMI function call parameter */
+ u8 scif; /* 0x05 - SCI function call (via _L00) */
+ u8 prm2; /* 0x06 - SCI function call parameter */
+ u8 prm3; /* 0x07 - SCI function call parameter */
+ u8 lckf; /* 0x08 - Global Lock function for EC */
+ u8 prm4; /* 0x09 - Lock function parameter */
+ u8 prm5; /* 0x0a - Lock function parameter */
+ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
+ u8 lids; /* 0x0f - LID state (open = 1) */
+ u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ /* Thermal policy */
+ u8 tlvl; /* 0x11 - Throttle Level Limit */
+ u8 flvl; /* 0x12 - Current FAN Level */
+ u8 tcrt; /* 0x13 - Critical Threshold */
+ u8 tpsv; /* 0x14 - Passive Threshold */
+ u8 tmax; /* 0x15 - CPU Tj_max */
+ u8 f0of; /* 0x16 - FAN 0 OFF Threshold */
+ u8 f0on; /* 0x17 - FAN 0 ON Threshold */
+ u8 f0pw; /* 0x18 - FAN 0 PWM value */
+ u8 f1of; /* 0x19 - FAN 1 OFF Threshold */
+ u8 f1on; /* 0x1a - FAN 1 ON Threshold */
+ u8 f1pw; /* 0x1b - FAN 1 PWM value */
+ u8 f2of; /* 0x1c - FAN 2 OFF Threshold */
+ u8 f2on; /* 0x1d - FAN 2 ON Threshold */
+ u8 f2pw; /* 0x1e - FAN 2 PWM value */
+ u8 f3of; /* 0x1f - FAN 3 OFF Threshold */
+ u8 f3on; /* 0x20 - FAN 3 ON Threshold */
+ u8 f3pw; /* 0x21 - FAN 3 PWM value */
+ u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
+ u8 f4on; /* 0x23 - FAN 4 ON Threshold */
+ u8 f4pw; /* 0x24 - FAN 4 PWM value */
+ u8 tmps; /* 0x25 - Temperature Sensor ID */
+ u8 rsvd3[2];
+ /* Processor Identification */
+ u8 apic; /* 0x28 - APIC enabled */
+ u8 mpen; /* 0x29 - MP capable/enabled */
+ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
+ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
+ u8 ppcm; /* 0x2c - Max. PPC state */
+ u8 pcnt; /* 0x2d - Processor Count */
+ u8 rsvd4[4];
+ /* Super I/O & CMOS config */
+ u8 natp; /* 0x32 - SIO type */
+ u8 s5u0; /* 0x33 - Enable USB0 in S5 */
+ u8 s5u1; /* 0x34 - Enable USB1 in S5 */
+ u8 s3u0; /* 0x35 - Enable USB0 in S3 */
+ u8 s3u1; /* 0x36 - Enable USB1 in S3 */
+ u8 s33g; /* 0x37 - Enable S3 in 3G */
+ u32 cmem; /* 0x38 - CBMEM TOC */
+ /* Integrated Graphics Device */
+ u8 igds; /* 0x3c - IGD state */
+ u8 tlst; /* 0x3d - Display Toggle List Pointer */
+ u8 cadl; /* 0x3e - currently attached devices */
+ u8 padl; /* 0x3f - previously attached devices */
+ u16 cste; /* 0x40 - current display state */
+ u16 nste; /* 0x42 - next display state */
+ u16 sste; /* 0x44 - set display state */
+ u8 ndid; /* 0x46 - number of device ids */
+ u32 did[5]; /* 0x47 - 5b device id 1..5 */
+ u8 rsvd5[0x9];
+ /* Backlight Control */
+ u8 blcs; /* 0x64 - Backlight Control possible */
+ u8 brtl;
+ u8 odds;
+ u8 rsvd6[0x7];
+ /* Ambient Light Sensors*/
+ u8 alse; /* 0x6e - ALS enable */
+ u8 alaf;
+ u8 llow;
+ u8 lhih;
+ u8 rsvd7[0x6];
+ /* Extended Mobile Access */
+ u8 emae; /* 0x78 - EMA enable */
+ u16 emap; /* 0x79 - EMA pointer */
+ u16 emal; /* 0x7a - EMA Length */
+ u8 rsvd8[0x5];
+ /* MEF */
+ u8 mefe; /* 0x82 - MEF enable */
+ u8 rsvd9[0x9];
+ /* TPM support */
+ u8 tpmp; /* 0x8c - TPM */
+ u8 tpme;
+ u8 rsvd10[8];
+ /* SATA */
+ u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
+ u8 gtf1[7];
+ u8 gtf2[7];
+ u8 idem;
+ u8 idet;
+ u8 rsvd11[6];
+ /* XHCI */
+ u8 xhci;
+ /* IGD OpRegion (not implemented yet) */
+ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
+ u8 ibtt; /* 0xb8 - IGD boot type */
+ u8 ipat; /* 0xb9 - IGD panel type */
+ u8 itvf; /* 0xba - IGD TV format */
+ u8 itvm; /* 0xbb - IGD TV minor format */
+ u8 ipsc; /* 0xbc - IGD Panel Scaling */
+ u8 iblc; /* 0xbd - IGD BLC configuration */
+ u8 ibia; /* 0xbe - IGD BIA configuration */
+ u8 issc; /* 0xbf - IGD SSC configuration */
+ u8 i409; /* 0xc0 - IGD 0409 modified settings */
+ u8 i509; /* 0xc1 - IGD 0509 modified settings */
+ u8 i609; /* 0xc2 - IGD 0609 modified settings */
+ u8 i709; /* 0xc3 - IGD 0709 modified settings */
+ u8 idmm; /* 0xc4 - IGD Power Conservation */
+ u8 idms; /* 0xc5 - IGD DVMT memory size */
+ u8 if1e; /* 0xc6 - IGD Function 1 Enable */
+ u8 hvco; /* 0xc7 - IGD HPLL VCO */
+ u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
+ u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
+ u8 pavp; /* 0xe9 - IGD PAVP data */
+ u8 rsvd12; /* 0xea - rsvd */
+ u8 oscc; /* 0xeb - PCIe OSC control */
+ u8 npce; /* 0xec - native pcie support */
+ u8 plfl; /* 0xed - platform flavor */
+ u8 brev; /* 0xee - board revision */
+ u8 dpbm; /* 0xef - digital port b mode */
+ u8 dpcm; /* 0xf0 - digital port c mode */
+ u8 dpdm; /* 0xf1 - digital port c mode */
+ u8 alfp; /* 0xf2 - active lfp */
+ u8 imon; /* 0xf3 - current graphics turbo imon value */
+ u8 mmio; /* 0xf4 - 64bit mmio support */
+ u8 rsvd13[11]; /* 0xf5 - rsvd */
+
+ /* ChromeOS specific (starts at 0x100)*/
+ chromeos_acpi_t chromeos;
+} __attribute__((packed)) global_nvs_t;
+
+#ifdef __SMM__
+/* Used in SMM to find the ACPI GNVS address */
+global_nvs_t *smm_get_gnvs(void);
+#endif
diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c
new file mode 100644
index 0000000..0e05558
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/pch.c
@@ -0,0 +1,429 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#ifdef __SMM__
+#include <arch/io.h>
+#include <device/pci_def.h>
+#else /* !__SMM__ */
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+#include "pch.h"
+
+static int pch_revision_id = -1;
+static int pch_type = -1;
+
+int pch_silicon_revision(void)
+{
+ device_t dev;
+
+#ifdef __SMM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+#endif
+
+ if (pch_revision_id < 0)
+ pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
+ return pch_revision_id;
+}
+
+int pch_silicon_type(void)
+{
+ device_t dev;
+
+#ifdef __SMM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+#endif
+
+ if (pch_type < 0)
+ pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
+ return pch_type;
+}
+
+int pch_silicon_supported(int type, int rev)
+{
+ int cur_type = pch_silicon_type();
+ int cur_rev = pch_silicon_revision();
+
+ switch (type) {
+ case PCH_TYPE_CPT:
+ /* CougarPoint minimum revision */
+ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
+ return 1;
+ /* PantherPoint any revision */
+ if (cur_type == PCH_TYPE_PPT)
+ return 1;
+ break;
+
+ case PCH_TYPE_PPT:
+ /* PantherPoint minimum revision */
+ if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+ unsigned try = IOBP_RETRY;
+ u32 data;
+
+ while (try--) {
+ data = RCBA32(IOBPS);
+ if ((data & 1) == 0)
+ return 1;
+ udelay(10);
+ }
+
+ printk(BIOS_ERR, "IOBP timeout\n");
+ return 0;
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+ u32 data;
+
+ /* Set the address */
+ RCBA32(IOBPIRI) = address;
+
+ /* READ OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ RCBA32(IOBPS) = IOBPS_RW_BX;
+ else
+ RCBA32(IOBPS) = IOBPS_READ_AX;
+ if (!iobp_poll())
+ return;
+
+ /* Read IOBP data */
+ data = RCBA32(IOBPD);
+ if (!iobp_poll())
+ return;
+
+ /* Check for successful transaction */
+ if ((RCBA32(IOBPS) & 0x6) != 0) {
+ printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
+ return;
+ }
+
+ /* Update the data */
+ data &= andvalue;
+ data |= orvalue;
+
+ /* WRITE OPCODE */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+ RCBA32(IOBPS) = IOBPS_RW_BX;
+ else
+ RCBA32(IOBPS) = IOBPS_WRITE_AX;
+ if (!iobp_poll())
+ return;
+
+ /* Write IOBP data */
+ RCBA32(IOBPD) = data;
+ if (!iobp_poll())
+ return;
+}
+
+#ifndef __SMM__
+/* Set bit in Function Disble register to hide this device */
+static void pch_hide_devfn(unsigned devfn)
+{
+ switch (devfn) {
+ case PCI_DEVFN(22, 0): /* MEI #1 */
+ RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+ break;
+ case PCI_DEVFN(22, 1): /* MEI #2 */
+ RCBA32_OR(FD2, PCH_DISABLE_MEI2);
+ break;
+ case PCI_DEVFN(22, 2): /* IDE-R */
+ RCBA32_OR(FD2, PCH_DISABLE_IDER);
+ break;
+ case PCI_DEVFN(22, 3): /* KT */
+ RCBA32_OR(FD2, PCH_DISABLE_KT);
+ break;
+ case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
+ RCBA32_OR(BUC, PCH_DISABLE_GBE);
+ break;
+ case PCI_DEVFN(26, 0): /* EHCI #2 */
+ RCBA32_OR(FD, PCH_DISABLE_EHCI2);
+ break;
+ case PCI_DEVFN(27, 0): /* HD Audio Controller */
+ RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
+ break;
+ case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
+ case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
+ case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
+ case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
+ case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
+ case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
+ case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
+ case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
+ RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn)));
+ break;
+ case PCI_DEVFN(29, 0): /* EHCI #1 */
+ RCBA32_OR(FD, PCH_DISABLE_EHCI1);
+ break;
+ case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */
+ RCBA32_OR(FD, PCH_DISABLE_P2P);
+ break;
+ case PCI_DEVFN(31, 0): /* LPC */
+ RCBA32_OR(FD, PCH_DISABLE_LPC);
+ break;
+ case PCI_DEVFN(31, 2): /* SATA #1 */
+ RCBA32_OR(FD, PCH_DISABLE_SATA1);
+ break;
+ case PCI_DEVFN(31, 3): /* SMBUS */
+ RCBA32_OR(FD, PCH_DISABLE_SMBUS);
+ break;
+ case PCI_DEVFN(31, 5): /* SATA #22 */
+ RCBA32_OR(FD, PCH_DISABLE_SATA2);
+ break;
+ case PCI_DEVFN(31, 6): /* Thermal Subsystem */
+ RCBA32_OR(FD, PCH_DISABLE_THERMAL);
+ break;
+ }
+}
+
+/* Check if any port in set X to X+3 is enabled */
+static int pch_pcie_check_set_enabled(device_t dev)
+{
+ device_t port;
+ int port_func;
+ int dev_func = PCI_FUNC(dev->path.pci.devfn);
+
+ printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev));
+
+ /* Go through static device tree list of devices
+ * because enumeration is still in progress */
+ for (port = all_devices; port; port = port->next) {
+ /* Only care about PCIe root ports */
+ if (PCI_SLOT(port->path.pci.devfn) !=
+ PCI_SLOT(dev->path.pci.devfn))
+ continue;
+
+ /* Check if port is in range and enabled */
+ port_func = PCI_FUNC(port->path.pci.devfn);
+ if (port_func >= dev_func &&
+ port_func < (dev_func + 4) &&
+ port->enabled)
+ return 1;
+ }
+
+ /* None of the ports in this set are enabled */
+ return 0;
+}
+
+/* RPFN is a write-once register so keep a copy until it is written */
+static u32 new_rpfn;
+
+/* Swap function numbers assigned to two PCIe Root Ports */
+static void pch_pcie_function_swap(u8 old_fn, u8 new_fn)
+{
+ u32 old_rpfn = new_rpfn;
+
+ printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n",
+ old_fn, new_fn);
+
+ new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn));
+
+ /* Old function set to new function and disabled */
+ new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn));
+ new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn));
+}
+
+/* Update devicetree with new Root Port function number assignment */
+static void pch_pcie_devicetree_update(void)
+{
+ device_t dev;
+
+ /* Update the function numbers in the static devicetree */
+ for (dev = all_devices; dev; dev = dev->next) {
+ u8 new_devfn;
+
+ /* Only care about PCH PCIe root ports */
+ if (PCI_SLOT(dev->path.pci.devfn) !=
+ PCH_PCIE_DEV_SLOT)
+ continue;
+
+ /* Determine the new devfn for this port */
+ new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT,
+ RPFN_FNGET(new_rpfn,
+ PCI_FUNC(dev->path.pci.devfn)));
+
+ if (dev->path.pci.devfn != new_devfn) {
+ printk(BIOS_DEBUG,
+ "PCH: PCIe map %02x.%1x -> %02x.%1x\n",
+ PCI_SLOT(dev->path.pci.devfn),
+ PCI_FUNC(dev->path.pci.devfn),
+ PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
+
+ dev->path.pci.devfn = new_devfn;
+ }
+ }
+}
+
+/* Special handling for PCIe Root Port devices */
+static void pch_pcie_enable(device_t dev)
+{
+ struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
+ u32 reg32;
+
+ /*
+ * Save a copy of the Root Port Function Number map when
+ * starting to walk the list of PCIe Root Ports so it can
+ * be updated locally and written out when the last port
+ * has been processed.
+ */
+ if (PCI_FUNC(dev->path.pci.devfn) == 0) {
+ new_rpfn = RCBA32(RPFN);
+
+ /*
+ * Enable Root Port coalescing if the first port is disabled
+ * or the other devices will not be enumerated by the OS.
+ */
+ if (!dev->enabled)
+ config->pcie_port_coalesce = 1;
+
+ if (config->pcie_port_coalesce)
+ printk(BIOS_INFO,
+ "PCH: PCIe Root Port coalescing is enabled\n");
+ }
+
+ if (!dev->enabled) {
+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
+
+ /*
+ * PCIE Power Savings for PantherPoint and CougarPoint/B1+
+ *
+ * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
+ * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
+ *
+ * This check is done here instead of pcie driver
+ * because the pcie driver enable() handler is not
+ * called unless the device is enabled.
+ */
+ if ((PCI_FUNC(dev->path.pci.devfn) == 0 ||
+ PCI_FUNC(dev->path.pci.devfn) == 4)) {
+ /* Handle workaround for PPT and CPT/B1+ */
+ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) &&
+ !pch_pcie_check_set_enabled(dev)) {
+ u8 reg8 = pci_read_config8(dev, 0xe2);
+ reg8 |= 1;
+ pci_write_config8(dev, 0xe2, reg8);
+ }
+
+ /*
+ * Enable Clock Gating for shared PCIe resources
+ * before disabling this particular port.
+ */
+ pci_write_config8(dev, 0xe1, 0x3c);
+ }
+
+ /* Ensure memory, io, and bus master are all disabled */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Do not claim downstream transactions for PCIe ports */
+ new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
+
+ /* Hide this device if possible */
+ pch_hide_devfn(dev->path.pci.devfn);
+ } else {
+ int fn;
+
+ /*
+ * Check if there is a lower disabled port to swap with this
+ * port in order to maintain linear order starting at zero.
+ */
+ if (config->pcie_port_coalesce) {
+ for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) {
+ if (!(new_rpfn & RPFN_HIDE(fn)))
+ continue;
+
+ /* Swap places with this function */
+ pch_pcie_function_swap(
+ PCI_FUNC(dev->path.pci.devfn), fn);
+ break;
+ }
+ }
+
+ /* Enable SERR */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_SERR;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+ }
+
+ /*
+ * When processing the last PCIe root port we can now
+ * update the Root Port Function Number and Hide register.
+ */
+ if (PCI_FUNC(dev->path.pci.devfn) == 7) {
+ printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
+ RCBA32(RPFN), new_rpfn);
+ RCBA32(RPFN) = new_rpfn;
+
+ /* Update static devictree with new function numbers */
+ if (config->pcie_port_coalesce)
+ pch_pcie_devicetree_update();
+ }
+}
+
+void pch_enable(device_t dev)
+{
+ u32 reg32;
+
+ /* PCH PCIe Root Ports get special handling */
+ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT)
+ return pch_pcie_enable(dev);
+
+ if (!dev->enabled) {
+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
+
+ /* Ensure memory, io, and bus master are all disabled */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Hide this device if possible */
+ pch_hide_devfn(dev->path.pci.devfn);
+ } else {
+ /* Enable SERR */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_SERR;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+ }
+}
+
+struct chip_operations southbridge_intel_ibexpeak_ops = {
+ CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge")
+ .enable_dev = pch_enable,
+};
+#endif
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
new file mode 100644
index 0000000..356dd8a
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -0,0 +1,571 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
+#define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
+
+/* PCH types */
+#define PCH_TYPE_CPT 0x1c /* CougarPoint */
+#define PCH_TYPE_PPT 0x1e /* IvyBridge */
+#define PCH_TYPE_MOBILE5 0x3b
+
+/* PCH stepping values for LPC device */
+#define PCH_STEP_A0 0
+#define PCH_STEP_A1 1
+#define PCH_STEP_B0 2
+#define PCH_STEP_B1 3
+#define PCH_STEP_B2 4
+#define PCH_STEP_B3 5
+
+/*
+ * It does not matter where we put the SMBus I/O base, as long as we
+ * keep it consistent and don't interfere with other devices. Stage2
+ * will relocate this anyways.
+ * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * again. But handling static BARs is a generic problem that should be
+ * solved in the device allocator.
+ */
+#define SMBUS_IO_BASE 0x0400
+#define SMBUS_SLAVE_ADDR 0x24
+/* TODO Make sure these don't get changed by stage2 */
+#define DEFAULT_GPIOBASE 0x0480
+#define DEFAULT_PMBASE 0x0500
+
+#define DEFAULT_RCBA 0xfed1c000
+
+#ifndef __ACPI__
+#define DEBUG_PERIODIC_SMIS 0
+
+#if defined (__SMM__) && !defined(__ASSEMBLER__)
+void intel_pch_finalize_smm(void);
+#endif
+
+#if !defined(__ASSEMBLER__)
+#if !defined(__PRE_RAM__)
+#if !defined(__SMM__)
+#include "chip.h"
+void pch_enable(device_t dev);
+#endif
+int pch_silicon_revision(void);
+int pch_silicon_type(void);
+int pch_silicon_supported(int type, int rev);
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+#if CONFIG_ELOG
+void pch_log_state(void);
+#endif
+#else /* __PRE_RAM__ */
+void enable_smbus(void);
+void enable_usb_bar(void);
+int smbus_read_byte(unsigned device, unsigned address);
+int smbus_write_byte(unsigned device, unsigned address, u8 data);
+int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
+int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
+int early_spi_read(u32 offset, u32 size, u8 *buffer);
+#endif
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS 0x06
+#define SMLT 0x1b
+#define SECSTS 0x1e
+#define INTR 0x3c
+#define BCTRL 0x3e
+#define SBR (1 << 6)
+#define SEE (1 << 1)
+#define PERE (1 << 0)
+
+#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
+#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
+#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)
+#define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
+#define PCH_PCIE_DEV_SLOT 28
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_3 0xa4
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD (1 << 2)
+#define RTC_POWER_FAILED (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define ACPI_EN (1 << 7)
+#define BIOS_CNTL 0xDC
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT 0xb8
+
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
+
+#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
+
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
+#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
+#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
+#define INTR_LN 0x3c
+#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
+#define IDE_DECODE_ENABLE (1 << 15)
+#define IDE_SITRE (1 << 14)
+#define IDE_ISP_5_CLOCKS (0 << 12)
+#define IDE_ISP_4_CLOCKS (1 << 12)
+#define IDE_ISP_3_CLOCKS (2 << 12)
+#define IDE_RCT_4_CLOCKS (0 << 8)
+#define IDE_RCT_3_CLOCKS (1 << 8)
+#define IDE_RCT_2_CLOCKS (2 << 8)
+#define IDE_RCT_1_CLOCKS (3 << 8)
+#define IDE_DTE1 (1 << 7)
+#define IDE_PPE1 (1 << 6)
+#define IDE_IE1 (1 << 5)
+#define IDE_TIME1 (1 << 4)
+#define IDE_DTE0 (1 << 3)
+#define IDE_PPE0 (1 << 2)
+#define IDE_IE0 (1 << 1)
+#define IDE_TIME0 (1 << 0)
+#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
+
+#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
+#define IDE_SSDE1 (1 << 3)
+#define IDE_SSDE0 (1 << 2)
+#define IDE_PSDE1 (1 << 1)
+#define IDE_PSDE0 (1 << 0)
+
+#define IDE_SDMA_TIM 0x4a
+
+#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
+#define FAST_PCB1 (1 << 13)
+#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
+#define PCB1 (1 << 1)
+#define PCB0 (1 << 0)
+
+#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
+#define SATA_SP 0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
+
+/* PCI Configuration Space (D31:F3): SMBus */
+#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
+#define SMB_BASE 0x20
+#define HOSTC 0x40
+#define SMB_RCV_SLVA 0x09
+
+/* HOSTC bits */
+#define I2C_EN (1 << 2)
+#define SMB_SMI_EN (1 << 1)
+#define HST_EN (1 << 0)
+
+/* SMBus I/O bits. */
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL 0x2
+#define SMBHSTCMD 0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT 0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL 0xf
+
+#define SMBUS_TIMEOUT (10 * 1000 * 100)
+
+
+/* Southbridge IO BARs */
+
+#define GPIOBASE 0x48
+
+#define PMBASE 0x40
+
+/* Root Complex Register Block */
+#define RCBA 0xf0
+
+#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
+#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
+#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
+
+#define RCBA_AND_OR(bits, x, and, or) \
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
+
+#define VCH 0x0000 /* 32bit */
+#define VCAP1 0x0004 /* 32bit */
+#define VCAP2 0x0008 /* 32bit */
+#define PVC 0x000c /* 16bit */
+#define PVS 0x000e /* 16bit */
+
+#define V0CAP 0x0010 /* 32bit */
+#define V0CTL 0x0014 /* 32bit */
+#define V0STS 0x001a /* 16bit */
+
+#define V1CAP 0x001c /* 32bit */
+#define V1CTL 0x0020 /* 32bit */
+#define V1STS 0x0026 /* 16bit */
+
+#define RCTCL 0x0100 /* 32bit */
+#define ESD 0x0104 /* 32bit */
+#define ULD 0x0110 /* 32bit */
+#define ULBA 0x0118 /* 64bit */
+
+#define RP1D 0x0120 /* 32bit */
+#define RP1BA 0x0128 /* 64bit */
+#define RP2D 0x0130 /* 32bit */
+#define RP2BA 0x0138 /* 64bit */
+#define RP3D 0x0140 /* 32bit */
+#define RP3BA 0x0148 /* 64bit */
+#define RP4D 0x0150 /* 32bit */
+#define RP4BA 0x0158 /* 64bit */
+#define HDD 0x0160 /* 32bit */
+#define HDBA 0x0168 /* 64bit */
+#define RP5D 0x0170 /* 32bit */
+#define RP5BA 0x0178 /* 64bit */
+#define RP6D 0x0180 /* 32bit */
+#define RP6BA 0x0188 /* 64bit */
+
+#define RPC 0x0400 /* 32bit */
+#define RPFN 0x0404 /* 32bit */
+
+/* Root Port configuratinon space hide */
+#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
+/* Get the function number assigned to a Root Port */
+#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
+/* Set the function number for a Root Port */
+#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
+/* Root Port function number mask */
+#define RPFN_FNMASK(port) (7 << ((port) * 4))
+
+#define TRSR 0x1e00 /* 8bit */
+#define TRCR 0x1e10 /* 64bit */
+#define TWDR 0x1e18 /* 64bit */
+
+#define IOTR0 0x1e80 /* 64bit */
+#define IOTR1 0x1e88 /* 64bit */
+#define IOTR2 0x1e90 /* 64bit */
+#define IOTR3 0x1e98 /* 64bit */
+
+#define TCTL 0x3000 /* 8bit */
+
+#define NOINT 0
+#define INTA 1
+#define INTB 2
+#define INTC 3
+#define INTD 4
+
+#define DIR_IDR 12 /* Interrupt D Pin Offset */
+#define DIR_ICR 8 /* Interrupt C Pin Offset */
+#define DIR_IBR 4 /* Interrupt B Pin Offset */
+#define DIR_IAR 0 /* Interrupt A Pin Offset */
+
+#define PIRQA 0
+#define PIRQB 1
+#define PIRQC 2
+#define PIRQD 3
+#define PIRQE 4
+#define PIRQF 5
+#define PIRQG 6
+#define PIRQH 7
+
+/* IO Buffer Programming */
+#define IOBPIRI 0x2330
+#define IOBPD 0x2334
+#define IOBPS 0x2338
+#define IOBPS_RW_BX ((1 << 9)|(1 << 10))
+#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
+#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
+
+#define D31IP 0x3100 /* 32bit */
+#define D31IP_TTIP 24 /* Thermal Throttle Pin */
+#define D31IP_SIP2 20 /* SATA Pin 2 */
+#define D31IP_UNKIP 16
+#define D31IP_SMIP 12 /* SMBUS Pin */
+#define D31IP_SIP 8 /* SATA Pin */
+#define D30IP 0x3104 /* 32bit */
+#define D30IP_PIP 0 /* PCI Bridge Pin */
+#define D29IP 0x3108 /* 32bit */
+#define D29IP_E1P 0 /* EHCI #1 Pin */
+#define D28IP 0x310c /* 32bit */
+#define D28IP_P8IP 28 /* PCI Express Port 8 */
+#define D28IP_P7IP 24 /* PCI Express Port 7 */
+#define D28IP_P6IP 20 /* PCI Express Port 6 */
+#define D28IP_P5IP 16 /* PCI Express Port 5 */
+#define D28IP_P4IP 12 /* PCI Express Port 4 */
+#define D28IP_P3IP 8 /* PCI Express Port 3 */
+#define D28IP_P2IP 4 /* PCI Express Port 2 */
+#define D28IP_P1IP 0 /* PCI Express Port 1 */
+#define D27IP 0x3110 /* 32bit */
+#define D27IP_ZIP 0 /* HD Audio Pin */
+#define D26IP 0x3114 /* 32bit */
+#define D26IP_E2P 0 /* EHCI #2 Pin */
+#define D25IP 0x3118 /* 32bit */
+#define D25IP_LIP 0 /* GbE LAN Pin */
+#define D22IP 0x3124 /* 32bit */
+#define D22IP_KTIP 12 /* KT Pin */
+#define D22IP_IDERIP 8 /* IDE-R Pin */
+#define D22IP_MEI2IP 4 /* MEI #2 Pin */
+#define D22IP_MEI1IP 0 /* MEI #1 Pin */
+#define D20IP 0x3128 /* 32bit */
+#define D20IP_XHCIIP 0
+#define D31IR 0x3140 /* 16bit */
+#define D30IR 0x3142 /* 16bit */
+#define D29IR 0x3144 /* 16bit */
+#define D28IR 0x3146 /* 16bit */
+#define D27IR 0x3148 /* 16bit */
+#define D26IR 0x314c /* 16bit */
+#define D25IR 0x3150 /* 16bit */
+#define D22IR 0x315c /* 16bit */
+#define D20IR 0x3160 /* 16bit */
+#define OIC 0x31fe /* 16bit */
+#define SOFT_RESET_CTRL 0x38f4
+#define SOFT_RESET_DATA 0x38f8
+
+#define DIR_ROUTE(x,a,b,c,d) \
+ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
+
+#define RC 0x3400 /* 32bit */
+#define HPTC 0x3404 /* 32bit */
+#define GCS 0x3410 /* 32bit */
+#define BUC 0x3414 /* 32bit */
+#define PCH_DISABLE_GBE (1 << 5)
+#define FD 0x3418 /* 32bit */
+#define DISPBDF 0x3424 /* 16bit */
+#define FD2 0x3428 /* 32bit */
+#define CG 0x341c /* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P (1 << 1)
+#define PCH_DISABLE_SATA1 (1 << 2)
+#define PCH_DISABLE_SMBUS (1 << 3)
+#define PCH_DISABLE_HD_AUDIO (1 << 4)
+#define PCH_DISABLE_EHCI2 (1 << 13)
+#define PCH_DISABLE_LPC (1 << 14)
+#define PCH_DISABLE_EHCI1 (1 << 15)
+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
+#define PCH_DISABLE_THERMAL (1 << 24)
+#define PCH_DISABLE_SATA2 (1 << 25)
+#define PCH_DISABLE_XHCI (1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT (1 << 4)
+#define PCH_DISABLE_IDER (1 << 3)
+#define PCH_DISABLE_MEI2 (1 << 2)
+#define PCH_DISABLE_MEI1 (1 << 1)
+#define PCH_ENABLE_DBDF (1 << 0)
+
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL 0x00
+#define GP_IO_SEL 0x04
+#define GP_LVL 0x0c
+#define GPO_BLINK 0x18
+#define GPI_INV 0x2c
+#define GPIO_USE_SEL2 0x30
+#define GP_IO_SEL2 0x34
+#define GP_LVL2 0x38
+#define GPIO_USE_SEL3 0x40
+#define GP_IO_SEL3 0x44
+#define GP_LVL3 0x48
+#define GP_RST_SEL1 0x60
+#define GP_RST_SEL2 0x64
+#define GP_RST_SEL3 0x68
+
+/* ICH7 PMBASE */
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP (7 << 10)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define PROC_CNT 0x10
+#define LV2 0x14
+#define LV3 0x15
+#define LV4 0x16
+#define PM2_CNT 0x50 // mobile only
+#define GPE0_STS 0x20
+#define PME_B0_STS (1 << 13)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define PCI_EXP_STS (1 << 9)
+#define RI_STS (1 << 8)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define GPE0_EN 0x28
+#define PME_B0_EN (1 << 13)
+#define PME_EN (1 << 11)
+#define TCOSCI_EN (1 << 6)
+#define SMI_EN 0x30
+#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
+#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define MCSMI_EN (1 << 11) // Trap microcontroller range access
+#define BIOS_RLS (1 << 7) // asserts SCI on bit set
+#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
+#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
+#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
+#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
+#define EOS (1 << 1) // End of SMI (deassert SMI#)
+#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
+#define SMI_STS 0x34
+#define ALT_GP_SMI_EN 0x38
+#define ALT_GP_SMI_STS 0x3a
+#define GPE_CNTL 0x42
+#define DEVACT_STS 0x44
+#define SS_CNT 0x50
+#define C3_RES 0x54
+#define TCO1_STS 0x64
+#define DMISCI_STS (1 << 9)
+#define TCO2_STS 0x66
+
+/*
+ * SPI Opcode Menu setup for SPIBAR lockdown
+ * should support most common flash chips.
+ */
+
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+ (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+ (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+ (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
+ (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
+ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+
+#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */
+#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
+#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
+#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
+#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
+#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */
+#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
+#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
+#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
+#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
+#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
+#define SPIBAR_FADDR 0x3808 /* SPI flash address */
+#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
+
+#endif /* __ACPI__ */
+#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */
diff --git a/src/southbridge/intel/ibexpeak/pci.c b/src/southbridge/intel/ibexpeak/pci.c
new file mode 100644
index 0000000..306e7d5
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/pci.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+
+static void pci_init(struct device *dev)
+{
+ u16 reg16;
+ u8 reg8;
+
+ printk(BIOS_DEBUG, "PCI init.\n");
+ /* Enable Bus Master */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MASTER;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /* This device has no interrupt */
+ pci_write_config8(dev, INTR, 0xff);
+
+ /* disable parity error response and SERR */
+ reg16 = pci_read_config16(dev, BCTRL);
+ reg16 &= ~(1 << 0);
+ reg16 &= ~(1 << 1);
+ pci_write_config16(dev, BCTRL, reg16);
+
+ /* Master Latency Count must be set to 0x04! */
+ reg8 = pci_read_config8(dev, SMLT);
+ reg8 &= 0x07;
+ reg8 |= (0x04 << 3);
+ pci_write_config8(dev, SMLT, reg8);
+
+ /* Will this improve throughput of bus masters? */
+ pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+
+ /* Clear errors in status registers */
+ reg16 = pci_read_config16(dev, PSTS);
+ //reg16 |= 0xf900;
+ pci_write_config16(dev, PSTS, reg16);
+
+ reg16 = pci_read_config16(dev, SECSTS);
+ // reg16 |= 0xf900;
+ pci_write_config16(dev, SECSTS, reg16);
+}
+
+#undef PCI_BRIDGE_UPDATE_COMMAND
+static void ich_pci_dev_enable_resources(struct device *dev)
+{
+ const struct pci_operations *ops;
+ uint16_t command;
+
+ /* Set the subsystem vendor and device id for mainboard devices */
+ ops = ops_pci(dev);
+ if (dev->on_mainboard && ops && ops->set_subsystem) {
+ printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
+ dev_path(dev),
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+ ops->set_subsystem(dev,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+ }
+
+ command = pci_read_config16(dev, PCI_COMMAND);
+ command |= dev->command;
+#ifdef PCI_BRIDGE_UPDATE_COMMAND
+ /* If we write to PCI_COMMAND, on some systems
+ * this will cause the ROM and APICs not being visible
+ * anymore.
+ */
+ printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
+ pci_write_config16(dev, PCI_COMMAND, command);
+#else
+ printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+#endif
+}
+
+static void ich_pci_bus_enable_resources(struct device *dev)
+{
+ uint16_t ctrl;
+ /* enable IO in command register if there is VGA card
+ * connected with (even it does not claim IO resource)
+ */
+ if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
+ dev->command |= PCI_COMMAND_IO;
+ ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ ctrl |= dev->link_list->bridge_ctrl;
+ ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
+ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+ /* This is the reason we need our own pci_bus_enable_resources */
+ ich_pci_dev_enable_resources(dev);
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ /* NOTE: This is not the default position! */
+ if (!vendor || !device) {
+ pci_write_config32(dev, 0x54,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, 0x54,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = ich_pci_bus_enable_resources,
+ .init = pci_init,
+ .scan_bus = pci_scan_bridge,
+ .ops_pci = &pci_ops,
+};
+
+static const struct pci_driver pch_pci __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x2448,
+};
diff --git a/src/southbridge/intel/ibexpeak/pcie.c b/src/southbridge/intel/ibexpeak/pcie.c
new file mode 100644
index 0000000..9dc9801
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/pcie.c
@@ -0,0 +1,315 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+
+static void pch_pcie_pm_early(struct device *dev)
+{
+ u16 link_width_p0, link_width_p4;
+ u8 slot_power_limit = 10; /* 10W for x1 */
+ u32 reg32;
+ u8 reg8;
+
+ reg32 = RCBA32(RPC);
+
+ /* Port 0-3 link aggregation from PCIEPCS1[1:0] soft strap */
+ switch (reg32 & 3) {
+ case 3:
+ link_width_p0 = 4;
+ break;
+ case 1:
+ case 2:
+ link_width_p0 = 2;
+ break;
+ case 0:
+ default:
+ link_width_p0 = 1;
+ }
+
+ /* Port 4-7 link aggregation from PCIEPCS2[1:0] soft strap */
+ switch ((reg32 >> 2) & 3) {
+ case 3:
+ link_width_p4 = 4;
+ break;
+ case 1:
+ case 2:
+ link_width_p4 = 2;
+ break;
+ case 0:
+ default:
+ link_width_p4 = 1;
+ }
+
+ /* Enable dynamic clock gating where needed */
+ reg8 = pci_read_config8(dev, 0xe1);
+ switch (PCI_FUNC(dev->path.pci.devfn)) {
+ case 0: /* Port 0 */
+ if (link_width_p0 == 4)
+ slot_power_limit = 40; /* 40W for x4 */
+ else if (link_width_p0 == 2)
+ slot_power_limit = 20; /* 20W for x2 */
+ reg8 |= 0x3f;
+ break;
+ case 4: /* Port 4 */
+ if (link_width_p4 == 4)
+ slot_power_limit = 40; /* 40W for x4 */
+ else if (link_width_p4 == 2)
+ slot_power_limit = 20; /* 20W for x2 */
+ reg8 |= 0x3f;
+ break;
+ case 1: /* Port 1 only if Port 0 is x1 */
+ if (link_width_p0 == 1)
+ reg8 |= 0x3;
+ break;
+ case 2: /* Port 2 only if Port 0 is x1 or x2 */
+ case 3: /* Port 3 only if Port 0 is x1 or x2 */
+ if (link_width_p0 <= 2)
+ reg8 |= 0x3;
+ break;
+ case 5: /* Port 5 only if Port 4 is x1 */
+ if (link_width_p4 == 1)
+ reg8 |= 0x3;
+ break;
+ case 6: /* Port 7 only if Port 4 is x1 or x2 */
+ case 7: /* Port 7 only if Port 4 is x1 or x2 */
+ if (link_width_p4 <= 2)
+ reg8 |= 0x3;
+ break;
+ }
+ pci_write_config8(dev, 0xe1, reg8);
+
+ /* Set 0xE8[0] = 1 */
+ reg32 = pci_read_config32(dev, 0xe8);
+ reg32 |= 1;
+ pci_write_config32(dev, 0xe8, reg32);
+
+ /* Adjust Common Clock exit latency */
+ reg32 = pci_read_config32(dev, 0xd8);
+ reg32 &= ~(1 << 17);
+ reg32 |= (1 << 16) | (1 << 15);
+ reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */
+ pci_write_config32(dev, 0xd8, reg32);
+
+ /* Adjust ASPM L1 exit latency */
+ reg32 = pci_read_config32(dev, 0x4c);
+ reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15));
+ if (RCBA32(0x2320) & (1 << 16)) {
+ /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
+ reg32 |= (1 << 17);
+ } else {
+ /* Else set ASPM L1 to 2-4us */
+ reg32 |= (1 << 16);
+ }
+ pci_write_config32(dev, 0x4c, reg32);
+
+ /* Set slot power limit as configured above */
+ reg32 = pci_read_config32(dev, 0x54);
+ reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */
+ reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */
+ reg32 |= (slot_power_limit << 7);
+ pci_write_config32(dev, 0x54, reg32);
+}
+
+static void pch_pcie_pm_late(struct device *dev)
+{
+ struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
+ enum aspm_type apmc = 0;
+ u32 reg32;
+
+ /* Set 0x314 = 0x743a361b */
+ pci_mmio_write_config32(dev, 0x314, 0x743a361b);
+
+ /* Set 0x318[31:16] = 0x1414 */
+ reg32 = pci_mmio_read_config32(dev, 0x318);
+ reg32 &= 0x0000ffff;
+ reg32 |= 0x14140000;
+ pci_mmio_write_config32(dev, 0x318, reg32);
+
+ /* Set 0x324[5] = 1 */
+ reg32 = pci_mmio_read_config32(dev, 0x324);
+ reg32 |= (1 << 5);
+ pci_mmio_write_config32(dev, 0x324, reg32);
+
+ /* Set 0x330[7:0] = 0x40 */
+ reg32 = pci_mmio_read_config32(dev, 0x330);
+ reg32 &= ~(0xff);
+ reg32 |= 0x40;
+ pci_mmio_write_config32(dev, 0x330, reg32);
+
+ /* Set 0x33C[24:0] = 0x854c74 */
+ reg32 = pci_mmio_read_config32(dev, 0x33c);
+ reg32 &= 0xff000000;
+ reg32 |= 0x00854c74;
+ pci_mmio_write_config32(dev, 0x33c, reg32);
+
+ /* No IO-APIC, Disable EOI forwarding */
+ reg32 = pci_read_config32(dev, 0xd4);
+ reg32 |= (1 << 1);
+ pci_write_config32(dev, 0xd4, reg32);
+
+ /* Check for a rootport ASPM override */
+ switch (PCI_FUNC(dev->path.pci.devfn)) {
+ case 0:
+ apmc = config->pcie_aspm_f0;
+ break;
+ case 1:
+ apmc = config->pcie_aspm_f1;
+ break;
+ case 2:
+ apmc = config->pcie_aspm_f2;
+ break;
+ case 3:
+ apmc = config->pcie_aspm_f3;
+ break;
+ case 4:
+ apmc = config->pcie_aspm_f4;
+ break;
+ case 5:
+ apmc = config->pcie_aspm_f5;
+ break;
+ case 6:
+ apmc = config->pcie_aspm_f6;
+ break;
+ case 7:
+ apmc = config->pcie_aspm_f7;
+ break;
+ }
+
+ /* Setup the override or get the real ASPM setting */
+ if (apmc) {
+ reg32 = pci_read_config32(dev, 0xd4);
+ reg32 |= (apmc << 2) | (1 << 4);
+ pci_write_config32(dev, 0xd4, reg32);
+ } else {
+ apmc = pci_read_config32(dev, 0x50) & 3;
+ }
+
+ /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
+ if (apmc == PCIE_ASPM_BOTH) {
+ reg32 = pci_read_config32(dev, 0xe8);
+ reg32 |= (1 << 1);
+ pci_write_config32(dev, 0xe8, reg32);
+ }
+}
+
+static void pci_init(struct device *dev)
+{
+ u16 reg16;
+ u32 reg32;
+
+ printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
+
+ /* Enable Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* Set Cache Line Size to 0x10 */
+ // This has no effect but the OS might expect it
+ pci_write_config8(dev, 0x0c, 0x10);
+
+ reg16 = pci_read_config16(dev, 0x3e);
+ reg16 &= ~(1 << 0); /* disable parity error response */
+ // reg16 &= ~(1 << 1); /* disable SERR */
+ reg16 |= (1 << 2); /* ISA enable */
+ pci_write_config16(dev, 0x3e, reg16);
+
+#ifdef EVEN_MORE_DEBUG
+ reg32 = pci_read_config32(dev, 0x20);
+ printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
+ reg32 = pci_read_config32(dev, 0x24);
+ printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
+ reg32 = pci_read_config32(dev, 0x28);
+ printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
+ reg32 = pci_read_config32(dev, 0x2c);
+ printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
+#endif
+
+ /* Clear errors in status registers */
+ reg16 = pci_read_config16(dev, 0x06);
+ //reg16 |= 0xf900;
+ pci_write_config16(dev, 0x06, reg16);
+
+ reg16 = pci_read_config16(dev, 0x1e);
+ //reg16 |= 0xf900;
+ pci_write_config16(dev, 0x1e, reg16);
+}
+
+static void pch_pcie_enable(device_t dev)
+{
+ /* Power Management init before enumeration */
+ pch_pcie_pm_early(dev);
+}
+
+static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
+{
+ unsigned int ret;
+
+ /* Normal PCIe Scan */
+ ret = pciexp_scan_bridge(dev, max);
+
+ /* Late Power Management init after bridge device enumeration */
+ pch_pcie_pm_late(dev);
+
+ return ret;
+}
+
+static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ /* NOTE: This is not the default position! */
+ if (!vendor || !device) {
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0));
+ } else {
+ pci_write_config32(dev, 0x94,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = pcie_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pci_init,
+ .enable = pch_pcie_enable,
+ .scan_bus = pch_pciexp_scan_bridge,
+ .ops_pci = &pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16,
+ 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
+ 0x1e10, 0x1e12, 0x1e14, 0x1e16,
+ 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
+ 0 };
+
+static const struct pci_driver pch_pcie __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/southbridge/intel/ibexpeak/reset.c b/src/southbridge/intel/ibexpeak/reset.c
new file mode 100644
index 0000000..429aad0
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/reset.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void soft_reset(void)
+{
+ outb(0x04, 0xcf9);
+}
+
+void hard_reset(void)
+{
+ outb(0x06, 0xcf9);
+}
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
new file mode 100644
index 0000000..9f673fc
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -0,0 +1,300 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+
+typedef struct southbridge_intel_ibexpeak_config config_t;
+
+static inline u32 sir_read(struct device *dev, int idx)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(struct device *dev, int idx, u32 value)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ pci_write_config32(dev, SATA_SIRD, value);
+}
+
+static void sata_init(struct device *dev)
+{
+ u32 reg32;
+ u16 reg16;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ printk(BIOS_DEBUG, "SATA: Initializing...\n");
+
+ if (config == NULL) {
+ printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
+ return;
+ }
+
+ /* SATA configuration */
+
+ /* Enable BARs */
+ pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+ if (config->ide_legacy_combined) {
+ printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_config32(dev, 0x24, 0x00000000);
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ pci_write_config8(dev, 0x09, 0x80);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+ /* Set IDE I/O Configuration */
+ reg32 =
+ SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ pci_write_config32(dev, IDE_CONFIG, reg32);
+
+ /* Port enable */
+ reg16 = pci_read_config16(dev, 0x92);
+ reg16 &= ~0x3f;
+ reg16 |= config->sata_port_map;
+ pci_write_config16(dev, 0x92, reg16);
+
+ /* SATA Initialization register */
+ pci_write_config32(dev, 0x94,
+ ((config->
+ sata_port_map ^ 0x3f) << 24) | 0x183);
+ } else if (config->sata_ahci) {
+ u32 abar;
+
+ printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
+
+ /* Set Interrupt Line */
+ /* Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0x0b);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, 0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0);
+
+ /* Set IDE I/O Configuration */
+ reg32 = SIG_MODE_PRI_NORMAL; // | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ pci_write_config32(dev, IDE_CONFIG, reg32);
+
+ /* for AHCI, Port Enable is managed in memory mapped space */
+ reg16 = pci_read_config16(dev, 0x92);
+ reg16 &= ~0x3f; /* 6 ports SKU + ORM */
+ reg16 |= 0x8100 | config->sata_port_map;
+ pci_write_config16(dev, 0x92, reg16);
+
+ /* SATA Initialization register */
+ pci_write_config32(dev, 0x94,
+ ((config->
+ sata_port_map ^ 0x3f) << 24) | 0x183 |
+ 0x40000000);
+ pci_write_config32(dev, 0x98, 0x00590200);
+
+ /* Initialize AHCI memory-mapped space */
+ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ /* CAP (HBA Capabilities) : enable power management */
+ reg32 = read32(abar + 0x00);
+ reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
+ reg32 &= ~0x00020060; // clear SXS+EMS+PMS
+ /* Set ISS, if available */
+ if (config->sata_interface_speed_support) {
+ reg32 &= ~0x00f00000;
+ reg32 |= (config->sata_interface_speed_support & 0x03)
+ << 20;
+ }
+ write32(abar + 0x00, reg32);
+ /* PI (Ports implemented) */
+ write32(abar + 0x0c, config->sata_port_map);
+ (void)read32(abar + 0x0c); /* Read back 1 */
+ (void)read32(abar + 0x0c); /* Read back 2 */
+ /* CAP2 (HBA Capabilities Extended) */
+ reg32 = read32(abar + 0x24);
+ reg32 &= ~0x00000002;
+ write32(abar + 0x24, reg32);
+ /* VSP (Vendor Specific Register */
+ reg32 = read32(abar + 0xa0);
+ reg32 &= ~0x00000005;
+ write32(abar + 0xa0, reg32);
+ } else {
+ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
+
+ /* No AHCI: clear AHCI base */
+ pci_write_config32(dev, 0x24, 0x00000000);
+
+ /* And without AHCI BAR no memory decoding */
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MEMORY;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
+
+ /* Native mode capable on both primary and secondary (0xa)
+ * or'ed with enabled (0x50) = 0xf
+ */
+ pci_write_config8(dev, 0x09, 0x8f);
+
+ /* Set Interrupt Line */
+ /* Interrupt Pin is set by D31IP.PIP */
+ pci_write_config8(dev, INTR_LN, 0xff);
+
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_SITRE | IDE_ISP_3_CLOCKS |
+ IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+ /* Sync DMA */
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+ /* Set IDE I/O Configuration */
+ reg32 =
+ SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+ pci_write_config32(dev, IDE_CONFIG, reg32);
+
+ /* Port enable */
+ reg16 = pci_read_config16(dev, 0x92);
+ reg16 &= ~0x3f;
+ reg16 |= config->sata_port_map;
+ pci_write_config16(dev, 0x92, reg16);
+
+ /* SATA Initialization register */
+ pci_write_config32(dev, 0x94,
+ ((config->
+ sata_port_map ^ 0x3f) << 24) | 0x183);
+ }
+
+ /* Set Gen3 Transmitter settings if needed */
+ if (config->sata_port0_gen3_tx)
+ pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
+ config->sata_port0_gen3_tx);
+
+ if (config->sata_port1_gen3_tx)
+ pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
+ config->sata_port1_gen3_tx);
+
+ /* Additional Programming Requirements */
+ sir_write(dev, 0x04, 0x00000000);
+ sir_write(dev, 0x28, 0x0a000033);
+ reg32 = sir_read(dev, 0x54);
+ reg32 &= 0xff000000;
+ reg32 |= 0x555555;
+ sir_write(dev, 0x54, reg32);
+ sir_write(dev, 0x64, 0xcccccccc);
+ reg32 = sir_read(dev, 0x68);
+ reg32 &= 0xffff0000;
+ reg32 |= 0xcccc;
+ sir_write(dev, 0x68, reg32);
+ reg32 = sir_read(dev, 0x78);
+ reg32 &= 0x0000ffff;
+ reg32 |= 0x88880000;
+ sir_write(dev, 0x78, reg32);
+ sir_write(dev, 0x84, 0x001c7000);
+ sir_write(dev, 0x88, 0x88888888);
+ sir_write(dev, 0xa0, 0x001c7000);
+ // a4
+ sir_write(dev, 0xc4, 0x0c0c0c0c);
+ sir_write(dev, 0xc8, 0x0c0c0c0c);
+ sir_write(dev, 0xd4, 0x10000000);
+
+ pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
+ pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
+}
+
+static void sata_enable(device_t dev)
+{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+ u16 map = 0;
+
+ if (!config)
+ return;
+
+ /*
+ * Set SATA controller mode early so the resource allocator can
+ * properly assign IO/Memory resources for the controller.
+ */
+ if (config->sata_ahci)
+ map = 0x0060;
+
+ map |= (config->sata_port_map ^ 0x3f) << 8;
+
+ pci_write_config16(dev, 0x90, map);
+}
+
+static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor &
+ 0xffff));
+ }
+}
+
+static struct pci_operations sata_pci_ops = {
+ .set_subsystem = sata_set_subsystem,
+};
+
+static struct device_operations sata_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sata_init,
+ .enable = sata_enable,
+ .scan_bus = 0,
+ .ops_pci = &sata_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b2e, 0 };
+
+static const struct pci_driver pch_sata __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
new file mode 100644
index 0000000..490819b
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "pch.h"
+#include "smbus.h"
+
+static void pch_smbus_init(device_t dev)
+{
+ struct resource *res;
+ u16 reg16;
+
+ /* Enable clock gating */
+ reg16 = pci_read_config32(dev, 0x80);
+ reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
+ pci_write_config32(dev, 0x80, reg16);
+
+ /* Set Receive Slave Address */
+ res = find_resource(dev, PCI_BASE_ADDRESS_4);
+ if (res)
+ outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
+}
+
+static int lsmbus_read_byte(device_t dev, u8 address)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
+ res = find_resource(pbus->dev, 0x20);
+
+ return do_smbus_read_byte(res->base, device, address);
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+ .read_byte = lsmbus_read_byte,
+};
+
+static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+static struct pci_operations smbus_pci_ops = {
+ .set_subsystem = smbus_set_subsystem,
+};
+
+static void smbus_read_resources(device_t dev)
+{
+ struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
+ res->base = SMBUS_IO_BASE;
+ res->size = 32;
+ res->limit = res->base + res->size - 1;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Also add MMIO resource */
+ res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
+}
+
+static struct device_operations smbus_ops = {
+ .read_resources = smbus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .scan_bus = scan_static_bus,
+ .init = pch_smbus_init,
+ .ops_smbus_bus = &lops_smbus_bus,
+ .ops_pci = &smbus_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b30, 0 };
+
+static const struct pci_driver pch_smbus __pci_driver = {
+ .ops = &smbus_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/southbridge/intel/ibexpeak/smbus.h b/src/southbridge/intel/ibexpeak/smbus.h
new file mode 100644
index 0000000..d6e4ce5
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/smbus.h
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu at gmail.com>
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+#include "pch.h"
+
+static void smbus_delay(void)
+{
+ inb(0x80);
+}
+
+static int smbus_wait_until_ready(u16 smbus_base)
+{
+ unsigned loops = SMBUS_TIMEOUT;
+ unsigned char byte;
+ do {
+ smbus_delay();
+ if (--loops == 0)
+ break;
+ byte = inb(smbus_base + SMBHSTSTAT);
+ } while (byte & 1);
+ return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u16 smbus_base)
+{
+ unsigned loops = SMBUS_TIMEOUT;
+ unsigned char byte;
+ do {
+ smbus_delay();
+ if (--loops == 0)
+ break;
+ byte = inb(smbus_base + SMBHSTSTAT);
+ } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
+ return loops ? 0 : -1;
+}
+
+static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+{
+ unsigned char global_status_register;
+ unsigned char byte;
+
+ if (smbus_wait_until_ready(smbus_base) < 0) {
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+ }
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(address & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a byte data read */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+ (smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* Clear the data byte... */
+ outb(0, smbus_base + SMBHSTDAT0);
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+ smbus_base + SMBHSTCTL);
+
+ /* Poll for transaction completion */
+ if (smbus_wait_until_done(smbus_base) < 0) {
+ return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+ }
+
+ global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+ /* Ignore the "In Use" status... */
+ global_status_register &= ~(3 << 5);
+
+ /* Read results of transaction */
+ byte = inb(smbus_base + SMBHSTDAT0);
+ if (global_status_register != (1 << 1)) {
+ return SMBUS_ERROR;
+ }
+ return byte;
+}
+
+#ifdef __PRE_RAM__
+
+static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
+{
+ unsigned char global_status_register;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(address & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a byte data read */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+ (smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* Clear the data byte... */
+ outb(data, smbus_base + SMBHSTDAT0);
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+ smbus_base + SMBHSTCTL);
+
+ /* Poll for transaction completion */
+ if (smbus_wait_until_done(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+ global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+ /* Ignore the "In Use" status... */
+ global_status_register &= ~(3 << 5);
+
+ /* Read results of transaction */
+ if (global_status_register != (1 << 1))
+ return SMBUS_ERROR;
+
+ return 0;
+}
+
+static int do_smbus_block_write(unsigned smbus_base, unsigned device,
+ unsigned cmd, unsigned bytes, const u8 *buf)
+{
+ u8 status;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(cmd & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a block data write */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
+ (smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* set number of bytes to transfer */
+ outb(bytes, smbus_base + SMBHSTDAT0);
+
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ bytes--;
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+ smbus_base + SMBHSTCTL);
+
+ while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ /* Poll for transaction completion */
+ do {
+ status = inb(smbus_base + SMBHSTSTAT);
+ if (status & ((1 << 4) | /* FAILED */
+ (1 << 3) | /* BUS ERR */
+ (1 << 2))) /* DEV ERR */
+ return SMBUS_ERROR;
+
+ if (status & 0x80) { /* Byte done */
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ outb(status, smbus_base + SMBHSTSTAT);
+ }
+ } while(status & 0x01);
+
+ return 0;
+}
+
+static int do_smbus_block_read(unsigned smbus_base, unsigned device,
+ unsigned cmd, unsigned bytes, u8 *buf)
+{
+ u8 status;
+ int bytes_read = 0;
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(cmd & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a block data read */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
+ (smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+ smbus_base + SMBHSTCTL);
+
+ while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ /* Poll for transaction completion */
+ do {
+ status = inb(smbus_base + SMBHSTSTAT);
+ if (status & ((1 << 4) | /* FAILED */
+ (1 << 3) | /* BUS ERR */
+ (1 << 2))) /* DEV ERR */
+ return SMBUS_ERROR;
+
+ if (status & 0x80) { /* Byte done */
+ *buf = inb(smbus_base + SMBBLKDAT);
+ buf++;
+ bytes_read++;
+ outb(status, smbus_base + SMBHSTSTAT);
+ if (--bytes == 1) {
+ /* indicate that next byte is the last one */
+ outb(inb(smbus_base + SMBHSTCTL) | 0x20,
+ smbus_base + SMBHSTCTL);
+ }
+ }
+ } while(status & 0x01);
+
+ return bytes_read;
+}
+#endif
diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c
new file mode 100644
index 0000000..f5c8883
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/smi.c
@@ -0,0 +1,415 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <string.h>
+#include "pch.h"
+
+#include "northbridge/intel/nehalem/nehalem.h"
+
+extern unsigned char _binary_smm_start;
+extern unsigned char _binary_smm_end;
+
+/* While we read PMBASE dynamically in case it changed, let's
+ * initialize it with a sane value
+ */
+static u16 pmbase = DEFAULT_PMBASE;
+
+/**
+ * @brief read and clear PM1_STS
+ * @return PM1_STS register
+ */
+static u16 reset_pm1_status(void)
+{
+ u16 reg16;
+
+ reg16 = inw(pmbase + PM1_STS);
+ /* set status bits are cleared by writing 1 to them */
+ outw(reg16, pmbase + PM1_STS);
+
+ return reg16;
+}
+
+static void dump_pm1_status(u16 pm1_sts)
+{
+ printk(BIOS_DEBUG, "PM1_STS: ");
+ if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
+ if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
+ if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
+ if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
+ if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
+ if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
+ if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
+ if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+/**
+ * @brief read and clear SMI_STS
+ * @return SMI_STS register
+ */
+static u32 reset_smi_status(void)
+{
+ u32 reg32;
+
+ reg32 = inl(pmbase + SMI_STS);
+ /* set status bits are cleared by writing 1 to them */
+ outl(reg32, pmbase + SMI_STS);
+
+ return reg32;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+ printk(BIOS_DEBUG, "SMI_STS: ");
+ if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+ if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+ if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+ if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+ if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+ if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+ if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+ if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+ if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+ if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+ if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+ if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+ if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+ if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
+ if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
+ if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+ if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
+ if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
+ if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+ if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear GPE0_STS
+ * @return GPE0_STS register
+ */
+static u32 reset_gpe0_status(void)
+{
+ u32 reg32;
+
+ reg32 = inl(pmbase + GPE0_STS);
+ /* set status bits are cleared by writing 1 to them */
+ outl(reg32, pmbase + GPE0_STS);
+
+ return reg32;
+}
+
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+ int i;
+ printk(BIOS_DEBUG, "GPE0_STS: ");
+ for (i=31; i>= 16; i--) {
+ if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+ }
+ if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+ if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+ if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+ if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+ if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+ if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
+ if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
+ if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
+ if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
+ if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
+ if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
+ if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
+ if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+ if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear ALT_GP_SMI_STS
+ * @return ALT_GP_SMI_STS register
+ */
+static u16 reset_alt_gp_smi_status(void)
+{
+ u16 reg16;
+
+ reg16 = inl(pmbase + ALT_GP_SMI_STS);
+ /* set status bits are cleared by writing 1 to them */
+ outl(reg16, pmbase + ALT_GP_SMI_STS);
+
+ return reg16;
+}
+
+static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
+{
+ int i;
+ printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
+ for (i=15; i>= 0; i--) {
+ if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
+ }
+ printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief read and clear TCOx_STS
+ * @return TCOx_STS registers
+ */
+static u32 reset_tco_status(void)
+{
+ u32 tcobase = pmbase + 0x60;
+ u32 reg32;
+
+ reg32 = inl(tcobase + 0x04);
+ /* set status bits are cleared by writing 1 to them */
+ outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
+ if (reg32 & (1 << 18))
+ outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+
+ return reg32;
+}
+
+
+static void dump_tco_status(u32 tco_sts)
+{
+ printk(BIOS_DEBUG, "TCO_STS: ");
+ if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+ if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+ if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+ if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+ if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+ if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+ if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
+ if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
+ if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+ if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
+ if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
+ if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
+ if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief Set the EOS bit
+ */
+static void smi_set_eos(void)
+{
+ u8 reg8;
+
+ reg8 = inb(pmbase + SMI_EN);
+ reg8 |= EOS;
+ outb(reg8, pmbase + SMI_EN);
+}
+
+extern uint8_t smm_relocation_start, smm_relocation_end;
+
+static void smm_relocate(void)
+{
+ u32 smi_en;
+ u16 pm1_en;
+ u32 gpe0_en;
+
+ printk(BIOS_DEBUG, "Initializing SMM handler...");
+
+ pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+ PMBASE) & 0xff80;
+
+ printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
+
+ smi_en = inl(pmbase + SMI_EN);
+ if (smi_en & APMC_EN) {
+ printk(BIOS_INFO, "SMI# handler already enabled?\n");
+ return;
+ }
+
+ /* copy the SMM relocation code */
+ memcpy((void *)0x38000, &smm_relocation_start,
+ &smm_relocation_end - &smm_relocation_start);
+
+ printk(BIOS_DEBUG, "\n");
+ dump_smi_status(reset_smi_status());
+ dump_pm1_status(reset_pm1_status());
+ dump_gpe0_status(reset_gpe0_status());
+ dump_alt_gp_smi_status(reset_alt_gp_smi_status());
+ dump_tco_status(reset_tco_status());
+
+ /* Disable GPE0 PME_B0 */
+ gpe0_en = inl(pmbase + GPE0_EN);
+ gpe0_en &= ~PME_B0_EN;
+ outl(gpe0_en, pmbase + GPE0_EN);
+
+ pm1_en = 0;
+ pm1_en |= PWRBTN_EN;
+ pm1_en |= GBL_EN;
+ outw(pm1_en, pmbase + PM1_EN);
+
+ /* Enable SMI generation:
+ * - on TCO events
+ * - on APMC writes (io 0xb2)
+ * - on writes to SLP_EN (sleep states)
+ * - on writes to GBL_RLS (bios commands)
+ * No SMIs:
+ * - on microcontroller writes (io 0x62/0x66)
+ */
+
+ smi_en = 0; /* reset SMI enables */
+
+#if 0
+ smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
+#endif
+ smi_en |= TCO_EN;
+ smi_en |= APMC_EN;
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
+ * periodic SMIs.
+ */
+ smi_en |= PERIODIC_EN;
+#endif
+ smi_en |= SLP_SMI_EN;
+#if 0
+ smi_en |= BIOS_EN;
+#endif
+
+ /* The following need to be on for SMIs to happen */
+ smi_en |= EOS | GBL_SMI_EN;
+
+ outl(smi_en, pmbase + SMI_EN);
+
+ /**
+ * There are several methods of raising a controlled SMI# via
+ * software, among them:
+ * - Writes to io 0xb2 (APMC)
+ * - Writes to the Local Apic ICR with Delivery mode SMI.
+ *
+ * Using the local apic is a bit more tricky. According to
+ * AMD Family 11 Processor BKDG no destination shorthand must be
+ * used.
+ * The whole SMM initialization is quite a bit hardware specific, so
+ * I'm not too worried about the better of the methods at the moment
+ */
+
+ /* raise an SMI interrupt */
+ printk(BIOS_SPEW, " ... raise SMI#\n");
+ outb(0x00, 0xb2);
+}
+
+static int smm_handler_copied = 0;
+
+static void smm_install(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ u32 smm_base = 0xa0000;
+ struct ied_header ied = {
+ .signature = "INTEL RSVD",
+ .size = IED_SIZE,
+ .reserved = {0},
+ };
+
+ /* The first CPU running this gets to copy the SMM handler. But not all
+ * of them.
+ */
+ if (smm_handler_copied)
+ return;
+ smm_handler_copied = 1;
+
+ /* enable the SMM memory window */
+ pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
+
+#if CONFIG_SMM_TSEG
+ smm_base = pci_read_config32(dev, TSEG) & ~1;
+#endif
+
+ /* copy the real SMM handler */
+ printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
+ memcpy((void *)smm_base, &_binary_smm_start,
+ (size_t)(&_binary_smm_end - &_binary_smm_start));
+
+ /* copy the IED header into place */
+ if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
+ /* Top of TSEG region */
+ smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
+ printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
+ smm_base);
+ memcpy((void *)smm_base, &ied, sizeof(ied));
+ }
+ wbinvd();
+
+ /* close the SMM memory window and enable normal SMM */
+ pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
+}
+
+void smm_init(void)
+{
+#if CONFIG_ELOG
+ /* Log events from chipset before clearing */
+ pch_log_state();
+#endif
+
+ /* Put SMM code to 0xa0000 */
+ smm_install();
+
+ /* Put relocation code to 0x38000 and relocate SMBASE */
+ smm_relocate();
+
+ /* We're done. Make sure SMIs can happen! */
+ smi_set_eos();
+}
+
+void smm_lock(void)
+{
+ /* LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+ D_LCK | G_SMRAME | C_BASE_SEG);
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+ /*
+ * Issue SMI to set the gnvs pointer in SMM.
+ * tcg and smi1 are unused.
+ *
+ * EAX = APM_CNT_GNVS_UPDATE
+ * EBX = gnvs pointer
+ * EDX = APM_CNT
+ */
+ asm volatile (
+ "outb %%al, %%dx\n\t"
+ : /* ignore result */
+ : "a" (APM_CNT_GNVS_UPDATE),
+ "b" ((u32)gnvs),
+ "d" (APM_CNT)
+ );
+}
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
new file mode 100644
index 0000000..e89dd98
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -0,0 +1,849 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <device/pci_def.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+#include <pc80/mc146818rtc.h>
+#include "pch.h"
+
+#include "nvs.h"
+
+/* We are using PCIe accesses for now
+ * 1. the chipset can do it
+ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
+ */
+
+#include "northbridge/intel/nehalem/nehalem.h"
+#include <northbridge/intel/nehalem/pcie_config.c>
+
+/* While we read PMBASE dynamically in case it changed, let's
+ * initialize it with a sane value
+ */
+static u16 pmbase = DEFAULT_PMBASE;
+u16 smm_get_pmbase(void)
+{
+ return pmbase;
+}
+
+static u8 smm_initialized = 0;
+
+/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
+ * by coreboot.
+ */
+static global_nvs_t *gnvs = (global_nvs_t *)0x0;
+global_nvs_t *smm_get_gnvs(void)
+{
+ return gnvs;
+}
+
+#if CONFIG_SMM_TSEG
+static u32 tseg_base = 0;
+u32 smi_get_tseg_base(void)
+{
+ if (!tseg_base)
+ tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
+ return tseg_base;
+}
+void tseg_relocate(void **ptr)
+{
+ /* Adjust pointer with TSEG base */
+ if (*ptr && *ptr < (void*)smi_get_tseg_base())
+ *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base());
+}
+#endif
+
+/**
+ * @brief read and clear PM1_STS
+ * @return PM1_STS register
+ */
+static u16 reset_pm1_status(void)
+{
+ u16 reg16;
+
+ reg16 = inw(pmbase + PM1_STS);
+ /* set status bits are cleared by writing 1 to them */
+ outw(reg16, pmbase + PM1_STS);
+
+ return reg16;
+}
+
+static void dump_pm1_status(u16 pm1_sts)
+{
+ printk(BIOS_SPEW, "PM1_STS: ");
+ if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
+ if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
+ if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
+ if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
+ if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
+ if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
+ if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
+ if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
+ printk(BIOS_SPEW, "\n");
+ int reg16 = inw(pmbase + PM1_EN);
+ printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
+}
+
+/**
+ * @brief read and clear SMI_STS
+ * @return SMI_STS register
+ */
+static u32 reset_smi_status(void)
+{
+ u32 reg32;
+
+ reg32 = inl(pmbase + SMI_STS);
+ /* set status bits are cleared by writing 1 to them */
+ outl(reg32, pmbase + SMI_STS);
+
+ return reg32;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+ printk(BIOS_DEBUG, "SMI_STS: ");
+ if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+ if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+ if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+ if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+ if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+ if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+ if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+ if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+ if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+ if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+ if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+ if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+ if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
+ if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
+ if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+ if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
+ if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
+ if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+ if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear GPE0_STS
+ * @return GPE0_STS register
+ */
+static u32 reset_gpe0_status(void)
+{
+ u32 reg32;
+
+ reg32 = inl(pmbase + GPE0_STS);
+ /* set status bits are cleared by writing 1 to them */
+ outl(reg32, pmbase + GPE0_STS);
+
+ return reg32;
+}
+
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+ int i;
+ printk(BIOS_DEBUG, "GPE0_STS: ");
+ for (i=31; i>= 16; i--) {
+ if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+ }
+ if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+ if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+ if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+ if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+ if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW ");
+ if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
+ if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
+ if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
+ if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
+ if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
+ if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
+ if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
+ if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
+ if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG ");
+ if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear TCOx_STS
+ * @return TCOx_STS registers
+ */
+static u32 reset_tco_status(void)
+{
+ u32 tcobase = pmbase + 0x60;
+ u32 reg32;
+
+ reg32 = inl(tcobase + 0x04);
+ /* set status bits are cleared by writing 1 to them */
+ outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
+ if (reg32 & (1 << 18))
+ outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+
+ return reg32;
+}
+
+
+static void dump_tco_status(u32 tco_sts)
+{
+ printk(BIOS_DEBUG, "TCO_STS: ");
+ if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+ if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+ if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+ if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+ if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+ if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+ if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
+ if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
+ if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+ if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
+ if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
+ if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
+ if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
+ printk(BIOS_DEBUG, "\n");
+}
+
+int southbridge_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x32:
+ printk(BIOS_DEBUG, "OS Init\n");
+ /* gnvs->smif:
+ * On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ */
+ gnvs->smif = 0;
+ return 1; /* IO trap handled */
+ }
+
+ /* Not handled */
+ return 0;
+}
+
+/**
+ * @brief Set the EOS bit
+ */
+void southbridge_smi_set_eos(void)
+{
+ u8 reg8;
+
+ reg8 = inb(pmbase + SMI_EN);
+ reg8 |= EOS;
+ outb(reg8, pmbase + SMI_EN);
+}
+
+static void busmaster_disable_on_bus(int bus)
+{
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
+}
+
+/*
+ * Drive GPIO 60 low to gate memory reset in S3.
+ *
+ * Intel reference designs all use GPIO 60 but it is
+ * not a requirement and boards could use a different pin.
+ */
+static void southbridge_gate_memory_reset(void)
+{
+ u32 reg32;
+ u16 gpiobase;
+
+ gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+ if (!gpiobase)
+ return;
+
+ /* Make sure it is set as GPIO */
+ reg32 = inl(gpiobase + GPIO_USE_SEL2);
+ if (!(reg32 & (1 << 28))) {
+ reg32 |= (1 << 28);
+ outl(reg32, gpiobase + GPIO_USE_SEL2);
+ }
+
+ /* Make sure it is set as output */
+ reg32 = inl(gpiobase + GP_IO_SEL2);
+ if (reg32 & (1 << 28)) {
+ reg32 &= ~(1 << 28);
+ outl(reg32, gpiobase + GP_IO_SEL2);
+ }
+
+ /* Drive the output low */
+ reg32 = inl(gpiobase + GP_LVL2);
+ reg32 &= ~(1 << 28);
+ outl(reg32, gpiobase + GP_LVL2);
+}
+
+static void xhci_sleep(u8 slp_typ)
+{
+ u32 reg32, xhci_bar;
+ u16 reg16;
+
+ switch (slp_typ) {
+ case SLP_TYP_S3:
+ case SLP_TYP_S4:
+ reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74);
+ reg16 &= ~0x03UL;
+ pcie_write_config32(PCH_XHCI_DEV, 0x74, reg16);
+
+ reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
+ reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
+
+ xhci_bar = pcie_read_config32(PCH_XHCI_DEV,
+ PCI_BASE_ADDRESS_0) & ~0xFUL;
+
+ if ((xhci_bar + 0x4C0) & 1)
+ pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
+ if ((xhci_bar + 0x4D0) & 1)
+ pch_iobp_update(0xEC000182, ~0UL, (3 << 2));
+ if ((xhci_bar + 0x4E0) & 1)
+ pch_iobp_update(0xEC000282, ~0UL, (3 << 2));
+ if ((xhci_bar + 0x4F0) & 1)
+ pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
+
+ reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
+
+ reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74);
+ reg16 |= 0x03;
+ pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16);
+ break;
+
+ case SLP_TYP_S5:
+ reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74);
+ reg16 |= ((1 << 8) | 0x03);
+ pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16);
+ break;
+ }
+}
+
+
+static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u8 reg8;
+ u32 reg32;
+ u8 slp_typ;
+ u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+
+ // save and recover RTC port values
+ u8 tmp70, tmp72;
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+ get_option(&s5pwr, "power_on_after_fail");
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+
+ void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
+
+ /* First, disable further SMIs */
+ reg8 = inb(pmbase + SMI_EN);
+ reg8 &= ~SLP_SMI_EN;
+ outb(reg8, pmbase + SMI_EN);
+
+ /* Figure out SLP_TYP */
+ reg32 = inl(pmbase + PM1_CNT);
+ printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
+ slp_typ = (reg32 >> 10) & 7;
+
+ if (smm_get_gnvs()->xhci)
+ xhci_sleep(slp_typ);
+
+ /* Do any mainboard sleep handling */
+ tseg_relocate((void **)&mainboard_sleep);
+ if (mainboard_sleep)
+ mainboard_sleep(slp_typ-2);
+
+#if CONFIG_ELOG_GSMI
+ /* Log S3, S4, and S5 entry */
+ if (slp_typ >= 5)
+ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+#endif
+
+ /* Next, do the deed.
+ */
+
+ switch (slp_typ) {
+ case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+ case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+ case 5:
+ printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
+
+ /* Gate memory reset */
+ southbridge_gate_memory_reset();
+
+ /* Invalidate the cache before going to S3 */
+ wbinvd();
+ break;
+ case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+ case 7:
+ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+
+ outl(0, pmbase + GPE0_EN);
+
+ /* Always set the flag in case CMOS was changed on runtime. For
+ * "KEEP", switch to "OFF" - KEEP is software emulated
+ */
+ reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ if (s5pwr == MAINBOARD_POWER_ON) {
+ reg8 &= ~1;
+ } else {
+ reg8 |= 1;
+ }
+ pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+
+ /* also iterates over all bridges on bus 0 */
+ busmaster_disable_on_bus(0);
+ break;
+ default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
+ }
+
+ /* Write back to the SLP register to cause the originally intended
+ * event again. We need to set BIT13 (SLP_EN) though to make the
+ * sleep happen.
+ */
+ outl(reg32 | SLP_EN, pmbase + PM1_CNT);
+
+ /* Make sure to stop executing code here for S3/S4/S5 */
+ if (slp_typ > 1)
+ hlt();
+
+ /* In most sleep states, the code flow of this function ends at
+ * the line above. However, if we entered sleep state S1 and wake
+ * up again, we will continue to execute code in this function.
+ */
+ reg32 = inl(pmbase + PM1_CNT);
+ if (reg32 & SCI_EN) {
+ /* The OS is not an ACPI OS, so we set the state to S0 */
+ reg32 &= ~(SLP_EN | SLP_TYP);
+ outl(reg32, pmbase + PM1_CNT);
+ }
+}
+
+/*
+ * Look for Synchronous IO SMI and use save state from that
+ * core in case we are not running on the same core that
+ * initiated the IO transaction.
+ */
+static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
+{
+ em64t101_smm_state_save_area_t *state;
+ u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET;
+ int node;
+
+ /* Check all nodes looking for the one that issued the IO */
+ for (node = 0; node < CONFIG_MAX_CPUS; node++) {
+ state = (em64t101_smm_state_save_area_t *)
+ (base - (node * 0x400));
+
+ /* Check for Synchronous IO (bit0==1) */
+ if (!(state->io_misc_info & (1 << 0)))
+ continue;
+
+ /* Make sure it was a write (bit4==0) */
+ if (state->io_misc_info & (1 << 4))
+ continue;
+
+ /* Check for APMC IO port */
+ if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
+ continue;
+
+ /* Check AX against the requested command */
+ if ((state->rax & 0xff) != cmd)
+ continue;
+
+ return state;
+ }
+
+ return NULL;
+}
+
+#if CONFIG_ELOG_GSMI
+static void southbridge_smi_gsmi(void)
+{
+ u32 *ret, *param;
+ u8 sub_command;
+ em64t101_smm_state_save_area_t *io_smi =
+ smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);
+
+ if (!io_smi)
+ return;
+
+ /* Command and return value in EAX */
+ ret = (u32*)&io_smi->rax;
+ sub_command = (u8)(*ret >> 8);
+
+ /* Parameter buffer in EBX */
+ param = (u32*)&io_smi->rbx;
+
+ /* drivers/elog/gsmi.c */
+ *ret = gsmi_exec(sub_command, param);
+}
+#endif
+
+static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u32 pmctrl;
+ u8 reg8;
+ int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
+ em64t101_smm_state_save_area_t *state;
+
+ /* Emulate B2 register as the FADT / Linux expects it */
+
+ reg8 = inb(APM_CNT);
+ switch (reg8) {
+ case APM_CNT_CST_CONTROL:
+ /* Calling this function seems to cause
+ * some kind of race condition in Linux
+ * and causes a kernel oops
+ */
+ printk(BIOS_DEBUG, "C-state control\n");
+ break;
+ case APM_CNT_PST_CONTROL:
+ /* Calling this function seems to cause
+ * some kind of race condition in Linux
+ * and causes a kernel oops
+ */
+ printk(BIOS_DEBUG, "P-state control\n");
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ pmctrl = inl(pmbase + PM1_CNT);
+ pmctrl &= ~SCI_EN;
+ outl(pmctrl, pmbase + PM1_CNT);
+ printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
+ break;
+ case APM_CNT_ACPI_ENABLE:
+ pmctrl = inl(pmbase + PM1_CNT);
+ pmctrl |= SCI_EN;
+ outl(pmctrl, pmbase + PM1_CNT);
+ printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
+ break;
+ case APM_CNT_GNVS_UPDATE:
+ if (smm_initialized) {
+ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
+ return;
+ }
+ state = smi_apmc_find_state_save(reg8);
+ if (state) {
+ /* EBX in the state save contains the GNVS pointer */
+ gnvs = (global_nvs_t *)((u32)state->rbx);
+ smm_initialized = 1;
+ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
+ }
+ break;
+#if CONFIG_ELOG_GSMI
+ case ELOG_GSMI_APM_CNT:
+ southbridge_smi_gsmi();
+ break;
+#endif
+ }
+
+ tseg_relocate((void **)&mainboard_apmc);
+ if (mainboard_apmc)
+ mainboard_apmc(reg8);
+}
+
+static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u16 pm1_sts;
+
+ pm1_sts = reset_pm1_status();
+ dump_pm1_status(pm1_sts);
+
+ /* While OSPM is not active, poweroff immediately
+ * on a power button event.
+ */
+ if (pm1_sts & PWRBTN_STS) {
+ // power button pressed
+ u32 reg32;
+ reg32 = (7 << 10) | (1 << 13);
+#if CONFIG_ELOG_GSMI
+ elog_add_event(ELOG_TYPE_POWER_BUTTON);
+#endif
+ outl(reg32, pmbase + PM1_CNT);
+ }
+}
+
+static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u32 gpe0_sts;
+
+ gpe0_sts = reset_gpe0_status();
+ dump_gpe0_status(gpe0_sts);
+}
+
+static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+{
+ void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi;
+ u16 reg16;
+ reg16 = inw(pmbase + ALT_GP_SMI_STS);
+ outw(reg16, pmbase + ALT_GP_SMI_STS);
+
+ reg16 &= inw(pmbase + ALT_GP_SMI_EN);
+
+ tseg_relocate((void **)&mainboard_gpi);
+ if (mainboard_gpi) {
+ mainboard_gpi(reg16);
+ } else {
+ if (reg16)
+ printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
+ }
+
+ outw(reg16, pmbase + ALT_GP_SMI_STS);
+}
+
+static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u32 reg32;
+
+ reg32 = inl(pmbase + SMI_EN);
+
+ /* Are periodic SMIs enabled? */
+ if ((reg32 & MCSMI_EN) == 0)
+ return;
+
+ printk(BIOS_DEBUG, "Microcontroller SMI.\n");
+}
+
+
+
+static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u32 tco_sts;
+
+ tco_sts = reset_tco_status();
+
+ /* Any TCO event? */
+ if (!tco_sts)
+ return;
+
+ if (tco_sts & (1 << 8)) { // BIOSWR
+ u8 bios_cntl;
+
+ bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+
+ if (bios_cntl & 1) {
+ /* BWE is RW, so the SMI was caused by a
+ * write to BWE, not by a write to the BIOS
+ */
+
+ /* This is the place where we notice someone
+ * is trying to tinker with the BIOS. We are
+ * trying to be nice and just ignore it. A more
+ * resolute answer would be to power down the
+ * box.
+ */
+ printk(BIOS_DEBUG, "Switching back to RO\n");
+ pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+ } /* No else for now? */
+ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
+ /* Handle TCO timeout */
+ printk(BIOS_DEBUG, "TCO Timeout.\n");
+ } else if (!tco_sts) {
+ dump_tco_status(tco_sts);
+ }
+}
+
+static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u32 reg32;
+
+ reg32 = inl(pmbase + SMI_EN);
+
+ /* Are periodic SMIs enabled? */
+ if ((reg32 & PERIODIC_EN) == 0)
+ return;
+
+ printk(BIOS_DEBUG, "Periodic SMI.\n");
+}
+
+static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
+{
+#define IOTRAP(x) (trap_sts & (1 << x))
+ u32 trap_sts, trap_cycle;
+ u32 data, mask = 0;
+ int i;
+
+ trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
+ RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
+
+ trap_cycle = RCBA32(0x1e10);
+ for (i=16; i<20; i++) {
+ if (trap_cycle & (1 << i))
+ mask |= (0xff << ((i - 16) << 2));
+ }
+
+
+ /* IOTRAP(3) SMI function call */
+ if (IOTRAP(3)) {
+ if (gnvs && gnvs->smif)
+ io_trap_handler(gnvs->smif); // call function smif
+ return;
+ }
+
+ /* IOTRAP(2) currently unused
+ * IOTRAP(1) currently unused */
+
+ /* IOTRAP(0) SMIC */
+ if (IOTRAP(0)) {
+ if (!(trap_cycle & (1 << 24))) { // It's a write
+ printk(BIOS_DEBUG, "SMI1 command\n");
+ data = RCBA32(0x1e18);
+ data &= mask;
+ // if (smi1)
+ // southbridge_smi_command(data);
+ // return;
+ }
+ // Fall through to debug
+ }
+
+ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+ for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
+ printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
+ printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
+
+ if (!(trap_cycle & (1 << 24))) {
+ /* Write Cycle */
+ data = RCBA32(0x1e18);
+ printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
+ }
+#undef IOTRAP
+}
+
+typedef void (*smi_handler_t)(unsigned int node,
+ smm_state_save_area_t *state_save);
+
+static smi_handler_t southbridge_smi[32] = {
+ NULL, // [0] reserved
+ NULL, // [1] reserved
+ NULL, // [2] BIOS_STS
+ NULL, // [3] LEGACY_USB_STS
+ southbridge_smi_sleep, // [4] SLP_SMI_STS
+ southbridge_smi_apmc, // [5] APM_STS
+ NULL, // [6] SWSMI_TMR_STS
+ NULL, // [7] reserved
+ southbridge_smi_pm1, // [8] PM1_STS
+ southbridge_smi_gpe0, // [9] GPE0_STS
+ southbridge_smi_gpi, // [10] GPI_STS
+ southbridge_smi_mc, // [11] MCSMI_STS
+ NULL, // [12] DEVMON_STS
+ southbridge_smi_tco, // [13] TCO_STS
+ southbridge_smi_periodic, // [14] PERIODIC_STS
+ NULL, // [15] SERIRQ_SMI_STS
+ NULL, // [16] SMBUS_SMI_STS
+ NULL, // [17] LEGACY_USB2_STS
+ NULL, // [18] INTEL_USB2_STS
+ NULL, // [19] reserved
+ NULL, // [20] PCI_EXP_SMI_STS
+ southbridge_smi_monitor, // [21] MONITOR_STS
+ NULL, // [22] reserved
+ NULL, // [23] reserved
+ NULL, // [24] reserved
+ NULL, // [25] EL_SMI_STS
+ NULL, // [26] SPI_STS
+ NULL, // [27] reserved
+ NULL, // [28] reserved
+ NULL, // [29] reserved
+ NULL, // [30] reserved
+ NULL // [31] reserved
+};
+
+/**
+ * @brief Interrupt handler for SMI#
+ *
+ * @param smm_revision revision of the smm state save map
+ */
+
+void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+{
+ int i, dump = 0;
+ u32 smi_sts;
+
+ /* Update global variable pmbase */
+ pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+
+ /* We need to clear the SMI status registers, or we won't see what's
+ * happening in the following calls.
+ */
+ smi_sts = reset_smi_status();
+
+ /* Call SMI sub handler for each of the status bits */
+ for (i = 0; i < 31; i++) {
+ if (smi_sts & (1 << i)) {
+ if (southbridge_smi[i]) {
+#if CONFIG_SMM_TSEG
+ smi_handler_t handler = (smi_handler_t)
+ ((u8*)southbridge_smi[i] +
+ smi_get_tseg_base());
+ if (handler)
+ handler(node, state_save);
+#else
+ southbridge_smi[i](node, state_save);
+#endif
+ } else {
+ printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+ "handler available.\n", i);
+ dump = 1;
+ }
+ }
+ }
+
+ if(dump) {
+ dump_smi_status(smi_sts);
+ }
+
+}
diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c
new file mode 100644
index 0000000..cf577ec
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/spi.c
@@ -0,0 +1,746 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is derived from the flashrom project. */
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+
+#include <spi-generic.h>
+
+#define min(a, b) ((a)<(b)?(a):(b))
+
+#ifdef __SMM__
+#include <northbridge/intel/nehalem/pcie_config.c>
+#define pci_read_config_byte(dev, reg, targ)\
+ *(targ) = pcie_read_config8(dev, reg)
+#define pci_read_config_word(dev, reg, targ)\
+ *(targ) = pcie_read_config16(dev, reg)
+#define pci_read_config_dword(dev, reg, targ)\
+ *(targ) = pcie_read_config32(dev, reg)
+#define pci_write_config_byte(dev, reg, val)\
+ pcie_write_config8(dev, reg, val)
+#define pci_write_config_word(dev, reg, val)\
+ pcie_write_config16(dev, reg, val)
+#define pci_write_config_dword(dev, reg, val)\
+ pcie_write_config32(dev, reg, val)
+#else /* !__SMM__ */
+#include <device/device.h>
+#include <device/pci.h>
+#define pci_read_config_byte(dev, reg, targ)\
+ *(targ) = pci_read_config8(dev, reg)
+#define pci_read_config_word(dev, reg, targ)\
+ *(targ) = pci_read_config16(dev, reg)
+#define pci_read_config_dword(dev, reg, targ)\
+ *(targ) = pci_read_config32(dev, reg)
+#define pci_write_config_byte(dev, reg, val)\
+ pci_write_config8(dev, reg, val)
+#define pci_write_config_word(dev, reg, val)\
+ pci_write_config16(dev, reg, val)
+#define pci_write_config_dword(dev, reg, val)\
+ pci_write_config32(dev, reg, val)
+#endif /* !__SMM__ */
+
+typedef struct spi_slave ich_spi_slave;
+
+static int ichspi_lock = 0;
+
+typedef struct ich7_spi_regs {
+ uint16_t spis;
+ uint16_t spic;
+ uint32_t spia;
+ uint64_t spid[8];
+ uint64_t _pad;
+ uint32_t bbar;
+ uint16_t preop;
+ uint16_t optype;
+ uint8_t opmenu[8];
+} __attribute__((packed)) ich7_spi_regs;
+
+typedef struct ich9_spi_regs {
+ uint32_t bfpr;
+ uint16_t hsfs;
+ uint16_t hsfc;
+ uint32_t faddr;
+ uint32_t _reserved0;
+ uint32_t fdata[16];
+ uint32_t frap;
+ uint32_t freg[5];
+ uint32_t _reserved1[3];
+ uint32_t pr[5];
+ uint32_t _reserved2[2];
+ uint8_t ssfs;
+ uint8_t ssfc[3];
+ uint16_t preop;
+ uint16_t optype;
+ uint8_t opmenu[8];
+ uint32_t bbar;
+ uint8_t _reserved3[12];
+ uint32_t fdoc;
+ uint32_t fdod;
+ uint8_t _reserved4[8];
+ uint32_t afc;
+ uint32_t lvscc;
+ uint32_t uvscc;
+ uint8_t _reserved5[4];
+ uint32_t fpb;
+ uint8_t _reserved6[28];
+ uint32_t srdl;
+ uint32_t srdc;
+ uint32_t srd;
+} __attribute__((packed)) ich9_spi_regs;
+
+typedef struct ich_spi_controller {
+ int locked;
+
+ uint8_t *opmenu;
+ int menubytes;
+ uint16_t *preop;
+ uint16_t *optype;
+ uint32_t *addr;
+ uint8_t *data;
+ unsigned databytes;
+ uint8_t *status;
+ uint16_t *control;
+ uint32_t *bbar;
+} ich_spi_controller;
+
+static ich_spi_controller cntlr;
+
+enum {
+ SPIS_SCIP = 0x0001,
+ SPIS_GRANT = 0x0002,
+ SPIS_CDS = 0x0004,
+ SPIS_FCERR = 0x0008,
+ SSFS_AEL = 0x0010,
+ SPIS_LOCK = 0x8000,
+ SPIS_RESERVED_MASK = 0x7ff0,
+ SSFS_RESERVED_MASK = 0x7fe2
+};
+
+enum {
+ SPIC_SCGO = 0x000002,
+ SPIC_ACS = 0x000004,
+ SPIC_SPOP = 0x000008,
+ SPIC_DBC = 0x003f00,
+ SPIC_DS = 0x004000,
+ SPIC_SME = 0x008000,
+ SSFC_SCF_MASK = 0x070000,
+ SSFC_RESERVED = 0xf80000
+};
+
+enum {
+ HSFS_FDONE = 0x0001,
+ HSFS_FCERR = 0x0002,
+ HSFS_AEL = 0x0004,
+ HSFS_BERASE_MASK = 0x0018,
+ HSFS_BERASE_SHIFT = 3,
+ HSFS_SCIP = 0x0020,
+ HSFS_FDOPSS = 0x2000,
+ HSFS_FDV = 0x4000,
+ HSFS_FLOCKDN = 0x8000
+};
+
+enum {
+ HSFC_FGO = 0x0001,
+ HSFC_FCYCLE_MASK = 0x0006,
+ HSFC_FCYCLE_SHIFT = 1,
+ HSFC_FDBC_MASK = 0x3f00,
+ HSFC_FDBC_SHIFT = 8,
+ HSFC_FSMIE = 0x8000
+};
+
+enum {
+ SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
+ SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
+ SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
+ SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
+};
+
+#if CONFIG_DEBUG_SPI_FLASH
+
+static u8 readb_(const void *addr)
+{
+ u8 v = read8((unsigned long)addr);
+ printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
+ v, ((unsigned) addr & 0xffff) - 0xf020);
+ return v;
+}
+
+static u16 readw_(const void *addr)
+{
+ u16 v = read16((unsigned long)addr);
+ printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
+ v, ((unsigned) addr & 0xffff) - 0xf020);
+ return v;
+}
+
+static u32 readl_(const void *addr)
+{
+ u32 v = read32((unsigned long)addr);
+ printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
+ v, ((unsigned) addr & 0xffff) - 0xf020);
+ return v;
+}
+
+static void writeb_(u8 b, const void *addr)
+{
+ write8((unsigned long)addr, b);
+ printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
+ b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+static void writew_(u16 b, const void *addr)
+{
+ write16((unsigned long)addr, b);
+ printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
+ b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+static void writel_(u32 b, const void *addr)
+{
+ write32((unsigned long)addr, b);
+ printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
+ b, ((unsigned) addr & 0xffff) - 0xf020);
+}
+
+#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
+
+#define readb_(a) read8((uint32_t)a)
+#define readw_(a) read16((uint32_t)a)
+#define readl_(a) read32((uint32_t)a)
+#define writeb_(val, addr) write8((uint32_t)addr, val)
+#define writew_(val, addr) write16((uint32_t)addr, val)
+#define writel_(val, addr) write32((uint32_t)addr, val)
+
+#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
+
+static void write_reg(const void *value, void *dest, uint32_t size)
+{
+ const uint8_t *bvalue = value;
+ uint8_t *bdest = dest;
+
+ while (size >= 4) {
+ writel_(*(const uint32_t *)bvalue, bdest);
+ bdest += 4; bvalue += 4; size -= 4;
+ }
+ while (size) {
+ writeb_(*bvalue, bdest);
+ bdest++; bvalue++; size--;
+ }
+}
+
+static void read_reg(const void *src, void *value, uint32_t size)
+{
+ const uint8_t *bsrc = src;
+ uint8_t *bvalue = value;
+
+ while (size >= 4) {
+ *(uint32_t *)bvalue = readl_(bsrc);
+ bsrc += 4; bvalue += 4; size -= 4;
+ }
+ while (size) {
+ *bvalue = readb_(bsrc);
+ bsrc++; bvalue++; size--;
+ }
+}
+
+static void ich_set_bbar(uint32_t minaddr)
+{
+ const uint32_t bbar_mask = 0x00ffff00;
+ uint32_t ichspi_bbar;
+
+ minaddr &= bbar_mask;
+ ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
+ ichspi_bbar |= minaddr;
+ writel_(ichspi_bbar, cntlr.bbar);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ printk(BIOS_DEBUG, "spi_cs_is_valid used but not implemented\n");
+ return 0;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ ich_spi_slave *slave = malloc(sizeof(*slave));
+
+ if (!slave) {
+ printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n");
+ return NULL;
+ }
+
+ memset(slave, 0, sizeof(*slave));
+
+ slave->bus = bus;
+ slave->cs = cs;
+ return slave;
+}
+
+/*
+ * Check if this device ID matches one of supported Intel PCH devices.
+ *
+ * Return the ICH version if there is a match, or zero otherwise.
+ */
+static inline int get_ich_version(uint16_t device_id)
+{
+ if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
+ return 7;
+
+ if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
+ device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
+ (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
+ device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)
+ || device_id == 0x3b07)
+ return 9;
+
+ return 0;
+}
+
+void spi_init(void)
+{
+ int ich_version = 0;
+
+ uint8_t *rcrb; /* Root Complex Register Block */
+ uint32_t rcba; /* Root Complex Base Address */
+ uint8_t bios_cntl;
+ device_t dev;
+ uint32_t ids;
+ uint16_t vendor_id, device_id;
+
+#ifdef __SMM__
+ dev = PCI_DEV(0, 31, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+#endif
+ pci_read_config_dword(dev, 0, &ids);
+ vendor_id = ids;
+ device_id = (ids >> 16);
+
+ if (vendor_id != PCI_VENDOR_ID_INTEL) {
+ printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n");
+ return;
+ }
+
+ ich_version = get_ich_version(device_id);
+
+ if (!ich_version) {
+ printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n");
+ return;
+ }
+
+ pci_read_config_dword(dev, 0xf0, &rcba);
+ /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
+ rcrb = (uint8_t *)(rcba & 0xffffc000);
+ switch (ich_version) {
+ case 7:
+ {
+ const uint16_t ich7_spibar_offset = 0x3020;
+ ich7_spi_regs *ich7_spi =
+ (ich7_spi_regs *)(rcrb + ich7_spibar_offset);
+
+ ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK;
+ cntlr.opmenu = ich7_spi->opmenu;
+ cntlr.menubytes = sizeof(ich7_spi->opmenu);
+ cntlr.optype = &ich7_spi->optype;
+ cntlr.addr = &ich7_spi->spia;
+ cntlr.data = (uint8_t *)ich7_spi->spid;
+ cntlr.databytes = sizeof(ich7_spi->spid);
+ cntlr.status = (uint8_t *)&ich7_spi->spis;
+ cntlr.control = &ich7_spi->spic;
+ cntlr.bbar = &ich7_spi->bbar;
+ cntlr.preop = &ich7_spi->preop;
+ break;
+ }
+ case 9:
+ {
+ const uint16_t ich9_spibar_offset = 0x3800;
+ ich9_spi_regs *ich9_spi =
+ (ich9_spi_regs *)(rcrb + ich9_spibar_offset);
+ ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
+ cntlr.opmenu = ich9_spi->opmenu;
+ cntlr.menubytes = sizeof(ich9_spi->opmenu);
+ cntlr.optype = &ich9_spi->optype;
+ cntlr.addr = &ich9_spi->faddr;
+ cntlr.data = (uint8_t *)ich9_spi->fdata;
+ cntlr.databytes = sizeof(ich9_spi->fdata);
+ cntlr.status = &ich9_spi->ssfs;
+ cntlr.control = (uint16_t *)ich9_spi->ssfc;
+ cntlr.bbar = &ich9_spi->bbar;
+ cntlr.preop = &ich9_spi->preop;
+ break;
+ }
+ default:
+ printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version);
+ }
+
+ ich_set_bbar(0);
+
+ /* Disable the BIOS write protect so write commands are allowed. */
+ pci_read_config_byte(dev, 0xdc, &bios_cntl);
+ switch (ich_version) {
+ case 9:
+ /* Deassert SMM BIOS Write Protect Disable. */
+ bios_cntl &= ~(1 << 5);
+ break;
+
+ default:
+ break;
+ }
+ pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* Handled by ICH automatically. */
+}
+
+typedef struct spi_transaction {
+ const uint8_t *out;
+ uint32_t bytesout;
+ uint8_t *in;
+ uint32_t bytesin;
+ uint8_t type;
+ uint8_t opcode;
+ uint32_t offset;
+} spi_transaction;
+
+static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+{
+ trans->out += bytes;
+ trans->bytesout -= bytes;
+}
+
+static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+{
+ trans->in += bytes;
+ trans->bytesin -= bytes;
+}
+
+static void spi_setup_type(spi_transaction *trans)
+{
+ trans->type = 0xFF;
+
+ /* Try to guess spi type from read/write sizes. */
+ if (trans->bytesin == 0) {
+ if (trans->bytesout > 4)
+ /*
+ * If bytesin = 0 and bytesout > 4, we presume this is
+ * a write data operation, which is accompanied by an
+ * address.
+ */
+ trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
+ else
+ trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
+ return;
+ }
+
+ if (trans->bytesout == 1) { /* and bytesin is > 0 */
+ trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
+ return;
+ }
+
+ if (trans->bytesout == 4) { /* and bytesin is > 0 */
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ }
+
+ /* Fast read command is called with 5 bytes instead of 4 */
+ if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ --trans->bytesout;
+ }
+}
+
+static int spi_setup_opcode(spi_transaction *trans)
+{
+ uint16_t optypes;
+ uint8_t opmenu[cntlr.menubytes];
+
+ trans->opcode = trans->out[0];
+ spi_use_out(trans, 1);
+ if (!ichspi_lock) {
+ /* The lock is off, so just use index 0. */
+ writeb_(trans->opcode, cntlr.opmenu);
+ optypes = readw_(cntlr.optype);
+ optypes = (optypes & 0xfffc) | (trans->type & 0x3);
+ writew_(optypes, cntlr.optype);
+ return 0;
+ } else {
+ /* The lock is on. See if what we need is on the menu. */
+ uint8_t optype;
+ uint16_t opcode_index;
+
+ /* Write Enable is handled as atomic prefix */
+ if (trans->opcode == SPI_OPCODE_WREN)
+ return 0;
+
+ read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
+ for (opcode_index = 0; opcode_index < cntlr.menubytes;
+ opcode_index++) {
+ if (opmenu[opcode_index] == trans->opcode)
+ break;
+ }
+
+ if (opcode_index == cntlr.menubytes) {
+ printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
+ trans->opcode);
+ return -1;
+ }
+
+ optypes = readw_(cntlr.optype);
+ optype = (optypes >> (opcode_index * 2)) & 0x3;
+ if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
+ optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
+ trans->bytesout >= 3) {
+ /* We guessed wrong earlier. Fix it up. */
+ trans->type = optype;
+ }
+ if (optype != trans->type) {
+ printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
+ optype);
+ return -1;
+ }
+ return opcode_index;
+ }
+}
+
+static int spi_setup_offset(spi_transaction *trans)
+{
+ /* Separate the SPI address and data. */
+ switch (trans->type) {
+ case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
+ case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
+ return 0;
+ case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
+ case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
+ trans->offset = ((uint32_t)trans->out[0] << 16) |
+ ((uint32_t)trans->out[1] << 8) |
+ ((uint32_t)trans->out[2] << 0);
+ spi_use_out(trans, 3);
+ return 1;
+ default:
+ printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
+ return -1;
+ }
+}
+
+/*
+ * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
+ * below is True) or 0. In case the wait was for the bit(s) to set - write
+ * those bits back, which would cause resetting them.
+ *
+ * Return the last read status value on success or -1 on failure.
+ */
+static int ich_status_poll(u16 bitmask, int wait_til_set)
+{
+ int timeout = 6000; /* This will result in 60 ms */
+ u16 status = 0;
+
+ while (timeout--) {
+ status = readw_(cntlr.status);
+ if (wait_til_set ^ ((status & bitmask) == 0)) {
+ if (wait_til_set)
+ writew_((status & bitmask), cntlr.status);
+ return status;
+ }
+ udelay(10);
+ }
+
+ printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n",
+ status, bitmask);
+ return -1;
+}
+
+int spi_xfer(struct spi_slave *slave, const void *dout,
+ unsigned int bitsout, void *din, unsigned int bitsin)
+{
+ uint16_t control;
+ int16_t opcode_index;
+ int with_address;
+ int status;
+
+ spi_transaction trans = {
+ dout, bitsout / 8,
+ din, bitsin / 8,
+ 0xff, 0xff, 0
+ };
+
+ /* There has to always at least be an opcode. */
+ if (!bitsout || !dout) {
+ printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
+ return -1;
+ }
+ /* Make sure if we read something we have a place to put it. */
+ if (bitsin != 0 && !din) {
+ printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
+ return -1;
+ }
+ /* Right now we don't support writing partial bytes. */
+ if (bitsout % 8 || bitsin % 8) {
+ printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n");
+ return -1;
+ }
+
+ if (ich_status_poll(SPIS_SCIP, 0) == -1)
+ return -1;
+
+ writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
+
+ spi_setup_type(&trans);
+ if ((opcode_index = spi_setup_opcode(&trans)) < 0)
+ return -1;
+ if ((with_address = spi_setup_offset(&trans)) < 0)
+ return -1;
+
+ if (trans.opcode == SPI_OPCODE_WREN) {
+ /*
+ * Treat Write Enable as Atomic Pre-Op if possible
+ * in order to prevent the Management Engine from
+ * issuing a transaction between WREN and DATA.
+ */
+ if (!ichspi_lock)
+ writew_(trans.opcode, cntlr.preop);
+ return 0;
+ }
+
+ /* Preset control fields */
+ control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
+
+ /* Issue atomic preop cycle if needed */
+ if (readw_(cntlr.preop))
+ control |= SPIC_ACS;
+
+ if (!trans.bytesout && !trans.bytesin) {
+ /* SPI addresses are 24 bit only */
+ if (with_address)
+ writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
+
+ /*
+ * This is a 'no data' command (like Write Enable), its
+ * bitesout size was 1, decremented to zero while executing
+ * spi_setup_opcode() above. Tell the chip to send the
+ * command.
+ */
+ writew_(control, cntlr.control);
+
+ /* wait for the result */
+ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
+ if (status == -1)
+ return -1;
+
+ if (status & SPIS_FCERR) {
+ printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
+ return -1;
+ }
+
+ return 0;
+ }
+
+ /*
+ * Check if this is a write command atempting to transfer more bytes
+ * than the controller can handle. Iterations for writes are not
+ * supported here because each SPI write command needs to be preceded
+ * and followed by other SPI commands, and this sequence is controlled
+ * by the SPI chip driver.
+ */
+ if (trans.bytesout > cntlr.databytes) {
+ printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
+ " CONTROLLER_PAGE_LIMIT?\n");
+ return -1;
+ }
+
+ /*
+ * Read or write up to databytes bytes at a time until everything has
+ * been sent.
+ */
+ while (trans.bytesout || trans.bytesin) {
+ uint32_t data_length;
+
+ /* SPI addresses are 24 bit only */
+ writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
+
+ if (trans.bytesout)
+ data_length = min(trans.bytesout, cntlr.databytes);
+ else
+ data_length = min(trans.bytesin, cntlr.databytes);
+
+ /* Program data into FDATA0 to N */
+ if (trans.bytesout) {
+ write_reg(trans.out, cntlr.data, data_length);
+ spi_use_out(&trans, data_length);
+ if (with_address)
+ trans.offset += data_length;
+ }
+
+ /* Add proper control fields' values */
+ control &= ~((cntlr.databytes - 1) << 8);
+ control |= SPIC_DS;
+ control |= (data_length - 1) << 8;
+
+ /* write it */
+ writew_(control, cntlr.control);
+
+ /* Wait for Cycle Done Status or Flash Cycle Error. */
+ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
+ if (status == -1)
+ return -1;
+
+ if (status & SPIS_FCERR) {
+ printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
+ return -1;
+ }
+
+ if (trans.bytesin) {
+ read_reg(cntlr.data, trans.in, data_length);
+ spi_use_in(&trans, data_length);
+ if (with_address)
+ trans.offset += data_length;
+ }
+ }
+
+ /* Clear atomic preop now that xfer is done */
+ writew_(0, cntlr.preop);
+
+ return 0;
+}
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
new file mode 100644
index 0000000..68af04f
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 or (at your option)
+ * any later version of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+#include <usbdebug.h>
+#include <arch/io.h>
+
+static void thermal_init(struct device *dev)
+{
+ struct resource *res;
+
+ printk(BIOS_DEBUG, "Thermal init start.\n");
+
+ res = find_resource(dev, 0x10);
+ if (!res)
+ return;
+
+ write32(res->base + 4, 0x3a2b);
+ write8(res->base + 0xe, 0x40);
+ write32(res->base + 0x12, 0x1a40);
+ write16(res->base + 0x16, 0x7746);
+ write16(res->base + 0x1a, 0x10f0);
+ write16(res->base + 0x56, 0xffff);
+ write16(res->base + 0x64, 0xffff);
+ write16(res->base + 0x66, 0xffff);
+ write16(res->base + 0x68, 0xfa);
+
+ write8(res->base + 1, 0xb8);
+
+ printk(BIOS_DEBUG, "Thermal init done.\n");
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor &
+ 0xffff));
+ }
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = set_subsystem,
+};
+
+static struct device_operations thermal_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = thermal_init,
+ .scan_bus = 0,
+ .ops_pci = &pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b32, 0 };
+
+static const struct pci_driver pch_thermal __pci_driver = {
+ .ops = &thermal_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/southbridge/intel/ibexpeak/usb_debug.c b/src/southbridge/intel/ibexpeak/usb_debug.c
new file mode 100644
index 0000000..0fc1829
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/usb_debug.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include "pch.h"
+#include <delay.h>
+#if !defined (__PRE_RAM__) && !defined (__SMM__)
+#define PCI_DEV(bus, dev, fn) dev_find_slot (bus, PCI_DEVFN (dev, fn))
+#endif
+
+void enable_usbdebug(unsigned int port)
+{
+ u32 dbgctl;
+ device_t dev = PCI_DEV(0, 0x1a, 0); /* USB EHCI, D29:F7 */
+ device_t bdev = PCI_DEV(0, 0, 0); /* USB EHCI, D29:F7 */
+
+ /* Set the EHCI BAR address. */
+ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+ /* Enable access to the EHCI memory space registers. */
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+ PCI_COMMAND_SERR);
+
+ pci_write_config16(bdev, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Force ownership of the Debug Port to the EHCI controller. */
+ dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
+ dbgctl |= (1 << 30);
+ write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
+}
+
+/* Required for successful build, but currently empty. */
+void set_debug_port(unsigned int port)
+{
+ /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
+}
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
new file mode 100644
index 0000000..8d312cb
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+#include <usbdebug.h>
+#include <arch/io.h>
+
+static void usb_ehci_init(struct device *dev)
+{
+ u32 reg32;
+
+ /* Disable Wake on Disconnect in RMH */
+ reg32 = RCBA32(0x35b0);
+ reg32 |= 0x22;
+ RCBA32(0x35b0) = reg32;
+
+ printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+
+ pci_write_config32(dev, 0x84, 0x130c8911);
+ pci_write_config32(dev, 0x88, 0xa0);
+ pci_write_config32(dev, 0xf4, 0x80808588);
+ pci_write_config32(dev, 0xf4, 0x00808588);
+ pci_write_config32(dev, 0xf4, 0x00808588);
+ pci_write_config32(dev, 0xfc, 0x301b1728);
+
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ //reg32 |= PCI_COMMAND_SERR;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
+ unsigned device)
+{
+ u8 access_cntl;
+
+ access_cntl = pci_read_config8(dev, 0x80);
+
+ /* Enable writes to protected registers. */
+ pci_write_config8(dev, 0x80, access_cntl | 1);
+
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor &
+ 0xffff));
+ }
+
+ /* Restore protection. */
+ pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static void usb_ehci_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+ u32 usb_debug = 0;
+
+ if (PCI_SLOT(dev->path.pci.devfn) == 0x1a) {
+ usb_debug = get_ehci_debug();
+ set_ehci_debug(0);
+ }
+#endif
+ pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+ if (PCI_SLOT(dev->path.pci.devfn) == 0x1a) {
+ struct resource *res;
+ u32 base;
+ res = find_resource(dev, 0x10);
+ if (!res)
+ return;
+ base = res->base;
+ set_ehci_debug(usb_debug);
+ set_ehci_base(base);
+ report_resource_stored(dev, res, "");
+ }
+#endif
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = &usb_ehci_set_subsystem,
+};
+
+static struct device_operations usb_ehci_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = usb_ehci_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = usb_ehci_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b34, 0x3b3c, 0 };
+
+static const struct pci_driver pch_usb_ehci __pci_driver = {
+ .ops = &usb_ehci_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/southbridge/intel/ibexpeak/watchdog.c b/src/southbridge/intel/ibexpeak/watchdog.c
new file mode 100644
index 0000000..b6d9223
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/watchdog.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <watchdog.h>
+
+ //
+ // Disable PCH Watchdog timer at SB_RCBA+0x3410
+ //
+ // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
+ //
+void watchdog_off(void)
+{
+ device_t dev;
+ unsigned long value, base;
+
+ /* Turn off the ICH7 watchdog. */
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+
+ /* Enable I/O space. */
+ value = pci_read_config16(dev, 0x04);
+ value |= (1 << 10);
+ pci_write_config16(dev, 0x04, value);
+
+ /* Get TCO base. */
+ base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+
+ /* Disable the watchdog timer. */
+ value = inw(base + 0x08);
+ value |= 1 << 11;
+ outw(value, base + 0x08);
+
+ /* Clear TCO timeout status. */
+ outw(0x0008, base + 0x04);
+ outw(0x0002, base + 0x06);
+
+ printk(BIOS_DEBUG, "PCH watchdog disabled\n");
+}
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