[coreboot-gerrit] Patch set updated for coreboot: 235dd0d usbdebug: Support second EHCI controller with Debug Port

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Thu Jun 13 16:39:22 CEST 2013


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3438

-gerrit

commit 235dd0d76a4b22f8a7bed6f8441750551467b032
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Tue Jun 11 23:43:08 2013 +0300

    usbdebug: Support second EHCI controller with Debug Port
    
    Nowadays, chipsets or boards do not only have one USB port with the
    capabilities of a debug port but several ones. Some of these ports are
    easier accessible than others, so making them configurable is also necessary.
    This change adds infrastructure to switch between EHCI controllers,
    but does not implement it for any chipset.
    
    Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/console/Kconfig                                | 29 +++++++++++++++++-----
 src/console/console.c                              |  2 +-
 src/console/usbdebug_console.c                     |  5 ++--
 src/include/device/pci_def.h                       |  3 +++
 src/include/usbdebug.h                             |  6 ++++-
 src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 14 ++++++++---
 src/southbridge/amd/sb600/enable_usbdebug.c        |  9 +++++--
 src/southbridge/amd/sb700/enable_usbdebug.c        | 19 ++++++++------
 src/southbridge/amd/sb800/enable_usbdebug.c        | 14 ++++++++---
 src/southbridge/intel/common/usb_debug.c           |  9 +++++--
 src/southbridge/nvidia/ck804/enable_usbdebug.c     | 11 +++++---
 src/southbridge/nvidia/mcp55/enable_usbdebug.c     | 11 +++++---
 src/southbridge/sis/sis966/enable_usbdebug.c       | 11 +++++---
 13 files changed, 105 insertions(+), 38 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index dc41fd3..11201f1 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -127,9 +127,13 @@ config SPKMODEM
 
 # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
 config HAVE_USBDEBUG
-	def_bool n
+	bool
+	default y if HAVE_USBDEBUG_OPTIONS
+	default n
 
-config USBDEBUG
+# Use "select HAVE_USBDEBUG_OPTIONS" on southbridges with multiple
+# EHCI controllers having Debug Port capability
+config HAVE_USBDEBUG_OPTIONS
 	def_bool n
 
 config USBDEBUG
@@ -153,13 +157,24 @@ config USBDEBUG
 
 	  If unsure, say N.
 
-# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges
-# as those hardcode the physical USB port to be used as Debug Port to 1.
-# It cannot be changed by coreboot.
+config USBDEBUG_HCD_INDEX
+	int "Index for EHCI controller to use with usbdebug"
+	default 0
+	depends on USBDEBUG && HAVE_USBDEBUG_OPTIONS
+	help
+	   Some boards have multiple EHCI controllers with possibly only
+	   one having the Debug Port capability on an external USB port.
+	   
+	   Mapping of this index to PCI device functions is southbridge
+	   specific and mainboard level Kconfig should already provide
+	   a working default value here.
+	   
+	   If unsure, do not change.
+
 config USBDEBUG_DEFAULT_PORT
 	int "Default USB port to use as Debug Port"
 	default 1
-	depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600
+	depends on USBDEBUG && HAVE_USBDEBUG_OPTIONS
 	help
 	  This option selects which physical USB port coreboot will try to
 	  use as EHCI Debug Port first (valid values are: 1-15).
@@ -173,6 +188,8 @@ config USBDEBUG_DEFAULT_PORT
 	  actual port on your mainboard (potentially also USB pin headers
 	  on your mainboard) is highly board-specific, and you'll likely
 	  have to find out by trial-and-error.
+	  
+	  If unsure, do not change.
 
 # TODO: Deps?
 # TODO: Improve description.
diff --git a/src/console/console.c b/src/console/console.c
index 2f7de02..1391cb7 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -104,7 +104,7 @@ void console_init(void)
 #if CONFIG_EARLY_CONSOLE
 
 #if CONFIG_USBDEBUG
-	enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+	enable_usbdebug(CONFIG_USBDEBUG_HCD_INDEX, CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 #if CONFIG_CONSOLE_SERIAL
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 9cfb454..aa520fa 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <pc80/mc146818rtc.h>
 
 static struct ehci_debug_info dbg_info;
@@ -75,7 +76,7 @@ static void pci_ehci_set_resources(struct device *dev)
 
 void pci_ehci_read_resources(struct device *dev)
 {
-	if (!ehci_drv_ops) {
+	if (!ehci_drv_ops && dev->path.pci.devfn == pci_ehci_dbg_devfn(CONFIG_USBDEBUG_HCD_INDEX)) {
 		memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
 		ehci_drv_ops = dev->ops;
 		ehci_dbg_ops.set_resources = pci_ehci_set_resources;
@@ -91,7 +92,7 @@ void pci_ehci_read_resources(struct device *dev)
 static void dbgp_init(void)
 {
 #if !CONFIG_EARLY_CONSOLE
-	enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+	enable_usbdebug(CONFIG_USBDEBUG_HCD_INDEX, CONFIG_USBDEBUG_DEFAULT_PORT);
 #endif
 	usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info);
 }
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 58a7321..688c2f0 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -474,4 +474,7 @@
 #define PCI_FUNC(devfn)		((devfn) & 0x07)
 #define PCI_BDF(bus,dev,func)	((bus) << 16 | (dev) << 11 | (func) << 8)
 
+/* Translation from PCI_DEV() to devicetree path.pci.devfn. */
+#define PCI_DEV2DEVFN(dev)	((dev>>12)&0xff)
+
 #endif /* PCI_DEF_H */
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 961481a..0b773cd 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -22,6 +22,10 @@
 #define USBDEBUG_H
 
 #define EHCI_BAR_INDEX		0x10
+#define PCI_EHCI_CLASSCODE 	0x0c0320	/* USB2.0 with EHCI controller */
+
+unsigned int pci_ehci_dbg_dev(unsigned hcd_idx);
+#define pci_ehci_dbg_devfn(idx) PCI_DEV2DEVFN(pci_ehci_dbg_dev(idx))
 
 #ifndef __PRE_RAM__
 #if !CONFIG_USBDEBUG
@@ -43,7 +47,7 @@ struct ehci_debug_info {
         u8 bufidx;
 };
 
-void enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port);
 int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
 int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
 void set_ehci_base(unsigned ehci_base);
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index c74ac9a..9ba4b17 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -29,6 +29,11 @@
 #define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
 #define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
 
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2);
+}
+
 void set_debug_port(unsigned int port)
 {
 	u32 reg32;
@@ -42,14 +47,15 @@ void set_debug_port(unsigned int port)
 }
 
 
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
 {
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
+
 	/* Enable all of the USB controllers */
 	outb(0xEF, PM_INDEX);
 	outb(0x7F, PM_DATA);
 
-	pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2),
-			   EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), 0x04, 0x6);	/* mem space enabe */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 	set_debug_port(port);
 }
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 305362f..dcab84a 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -23,15 +23,20 @@
 #include <device/pci_def.h>
 #include "sb600.h"
 
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return  PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+}
+
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
 {
 	/* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
 {
-	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Select the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 2a7fc38..aec491c 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -27,6 +27,16 @@
 #define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
 #define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
 
+/*
+ * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
+ * This code currently only supports the first one, i.e., USB Debug devices
+ * attached to physical USB ports belonging to the first EHCI device.
+ */
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return PCI_DEV(0, 0x12, 2);
+}
+
 void set_debug_port(unsigned int port)
 {
 	u32 reg32;
@@ -39,14 +49,9 @@ void set_debug_port(unsigned int port)
 	write32(DEBUGPORT_MISC_CONTROL, reg32);
 }
 
-/*
- * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
- * This code currently only supports the first one, i.e., USB Debug devices
- * attached to physical USB ports belonging to the first EHCI device.
- */
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
 {
-	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Set the EHCI BAR address. */
 	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index f085eab..2577529 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -29,6 +29,11 @@
 #define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
 #define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
 
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2);
+}
+
 void set_debug_port(unsigned int port)
 {
 	u32 reg32;
@@ -42,14 +47,15 @@ void set_debug_port(unsigned int port)
 }
 
 
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
 {
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
+
 	/* Enable all of the USB controllers */
 	outb(0xEF, PM_INDEX);
 	outb(0x7F, PM_DATA);
 
-	pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2),
-			   EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), 0x04, 0x6);	/* mem space enabe */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 	set_debug_port(port);
 }
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 397c686..ea475c4 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -26,16 +26,21 @@
 #include <usbdebug.h>
 #include <device/pci_def.h>
 
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return PCI_DEV(0, 0x1d, 7);
+}
+
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
 {
 	/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
 }
 
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int ehci_idx, unsigned int port)
 {
 	u32 dbgctl;
-	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
+	device_t dev = pci_ehci_dbg_dev(ehci_idx);
 
 	/* Set the EHCI BAR address. */
 	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 659fdc6..ffebcf4 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -33,10 +33,15 @@
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
+}
+
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Write the port number to 0x74[15:12]. */
 	dword = pci_read_config32(dev, 0x74);
@@ -45,9 +50,9 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
 {
-	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Mark the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index f753c78..4855cf2 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -27,10 +27,15 @@
 #include <device/pci_def.h>
 #include "mcp55.h"
 
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+}
+
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Write the port number to 0x74[15:12]. */
 	dword = pci_read_config32(dev, 0x74);
@@ -39,9 +44,9 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
 {
-	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Mark the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index 78a3838..b042b93 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -29,10 +29,15 @@
 #include <device/pci_def.h>
 #include "sis966.h"
 
+unsigned int pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	return PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
+}
+
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Write the port number to 0x74[15:12]. */
 	dword = pci_read_config32(dev, 0x74);
@@ -41,9 +46,9 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
 {
-	device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = pci_ehci_dbg_dev(hcd_idx);
 
 	/* Mark the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);



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