[coreboot-gerrit] Patch set updated for coreboot: 6d1083f usbdebug: Unify Intel southbridge builds
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Jun 12 10:43:04 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3424
-gerrit
commit 6d1083fe695c076ca1c8a2c0fd37d9bd7709d012
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Jun 10 11:40:54 2013 +0300
usbdebug: Unify Intel southbridge builds
EHCI controller enable is identical on the affected chipsets.
Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/southbridge/intel/bd82x6x/Makefile.inc | 6 ++--
src/southbridge/intel/bd82x6x/usb_debug.c | 52 ----------------------------
src/southbridge/intel/i82801gx/usb_debug.c | 2 +-
src/southbridge/intel/i82801ix/Makefile.inc | 3 +-
src/southbridge/intel/lynxpoint/Makefile.inc | 4 ++-
src/southbridge/intel/lynxpoint/usb_debug.c | 49 --------------------------
src/southbridge/intel/sch/Makefile.inc | 4 ++-
src/southbridge/intel/sch/usb_debug.c | 47 -------------------------
8 files changed, 12 insertions(+), 155 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 2e10e03..48bfac1 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -46,9 +46,9 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
-romstage-$(CONFIG_USBDEBUG) += usb_debug.c
-ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
-smm-$(CONFIG_USBDEBUG) += usb_debug.c
+romstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+smm-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
romstage-y += reset.c
romstage-y += early_spi.c
diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c
deleted file mode 100644
index 38f144b..0000000
--- a/src/southbridge/intel/bd82x6x/usb_debug.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <usbdebug.h>
-#include <device/pci_def.h>
-
-#ifdef __PRE_RAM__
-#include "pch.h"
-
-void enable_usbdebug(unsigned int port)
-{
- u32 dbgctl;
- device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
- /* Force ownership of the Debug Port to the EHCI controller. */
- dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
- dbgctl |= (1 << 30);
- write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
-}
-#endif /* __PRE_RAM__ */
-
-/* Required for successful build, but currently empty. */
-void set_debug_port(unsigned int port)
-{
- /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
-}
-
diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index bdea889..008c153 100644
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -20,12 +20,12 @@
#ifndef __PRE_RAM__
#define __PRE_RAM__ // Use simple device model for this file even in ramstage
#endif
+
#include <stdint.h>
#include <arch/io.h>
#include <console/console.h>
#include <usbdebug.h>
#include <device/pci_def.h>
-#include "i82801gx.h"
/* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port)
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index 86b96ba..820172b 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -27,7 +27,6 @@ ramstage-y += sata.c
ramstage-y += hdaudio.c
ramstage-y += thermal.c
-ramstage-y += ../i82801gx/usb_debug.c
ramstage-y += ../i82801gx/reset.c
ramstage-y += ../i82801gx/watchdog.c
@@ -37,6 +36,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += early_init.c
romstage-y += early_smbus.c
romstage-y += dmi_setup.c
+
+ramstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
romstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
smm-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 7d1f894..cfc7aed 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -50,7 +50,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
-romstage-$(CONFIG_USBDEBUG) += usb_debug.c
+romstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+smm-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
romstage-y += reset.c early_spi.c rcba.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c
deleted file mode 100644
index 022cde3..0000000
--- a/src/southbridge/intel/lynxpoint/usb_debug.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <usbdebug.h>
-#include <device/pci_def.h>
-#include "pch.h"
-
-/* Required for successful build, but currently empty. */
-void set_debug_port(unsigned int port)
-{
- /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
-}
-
-void enable_usbdebug(unsigned int port)
-{
- u32 dbgctl;
- device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
- /* Force ownership of the Debug Port to the EHCI controller. */
- dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
- dbgctl |= (1 << 30);
- write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
-}
-
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc
index 9821fed..3d22715 100644
--- a/src/southbridge/intel/sch/Makefile.inc
+++ b/src/southbridge/intel/sch/Makefile.inc
@@ -33,7 +33,9 @@ ramstage-y += reset.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-$(CONFIG_USBDEBUG) += usb_debug.c
+romstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+smm-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
# We don't ship that, but booting without it is bound to fail
cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin
diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c
deleted file mode 100644
index fb436b5..0000000
--- a/src/southbridge/intel/sch/usb_debug.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <usbdebug.h>
-#include <device/pci_def.h>
-
-/* Required for successful build, but currently empty. */
-void set_debug_port(unsigned int port)
-{
- /* Not needed, the southbridges hardcode physical USB port 1. */
-}
-
-void enable_usbdebug(unsigned int port)
-{
- u32 dbgctl;
- device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
- /* Force ownership of the Debug Port to the EHCI controller. */
- dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
- dbgctl |= (1 << 30);
- write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
-}
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