[coreboot-gerrit] Patch set updated for coreboot: 1fc2c4c NOTFORMERGE: VX900 ramstage, and EPIA M850 board
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Sat Jun 8 18:57:02 CEST 2013
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1228
-gerrit
commit 1fc2c4c6dbc7eccf84c3ef682597a9102f20e7ca
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Tue May 21 14:51:26 2013 -0500
NOTFORMERGE: VX900 ramstage, and EPIA M850 board
This is the unsplit part of my VX900 tree. At this time, it contains everything
starting from ramstage and onwards.
I will split this up into pallatable chunks once the dependencies are merged.
This is the patch where all VX900 development is taking place. The
NOTFORMERGE modifier is here to indicate that the code ain't ready.
===========================================================================
== VX900 in ramstage:
---------------------------------------------------------------------------
MP tables and IOAPIC:
VX900 code enables the IOAPICs are enabled as long as they're declared in
devicetree.cb. Since we rely on automatic MP table generation, if an
IOAPIC is not properly declared, the code spits out an error, and continues
without initializing it.
LPC:
Implemented LPC driver with PIC interrupt routing.
VGA:
Still displays garbage and/or nothing.
Video BIOS depends on proprietary interrupt handlers, some of which are
implemented as YABEL interrupt handlers. If run in YABEL mode, the VGA BIOS
requires access to other PCI devices and direct hardware access, it seems.
GRUB2 and Linux are capable of initializing the VGA post-coreboot. Linux
can use the VGA normally, but hangs after a while.
SATA:
The controller does not support AHCI, or a compliant SATA implementation.
Normally SATA is done by setting RAID mode, but then SeaBIOS will not use
it to boot. The only viable option is to keep the controller in native IDE
mode.
SATA device detection works reliably when one drive is attached. ATA DMA
mode works reliably.
===========================================================================
== VIA EPIA M850 board:
---------------------------------------------------------------------------
Minimal infrastructure to compile a coreboot image for this board is
added.
PIRQ_TABLE:
Implemented, Linux can find and use irqs with "noapic acpi=off"
MP_TABLE:
Partially generated from devicetree.cb. Not tested.
KEYBOARD WORKS!!!
Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/mainboard/via/Kconfig | 3 +
src/mainboard/via/epia-m850/Kconfig | 50 ++++
src/mainboard/via/epia-m850/Makefile.inc | 21 ++
src/mainboard/via/epia-m850/devicetree.cb | 111 ++++++++
src/mainboard/via/epia-m850/irq_tables.c | 75 ++++++
src/mainboard/via/epia-m850/mainboard.c | 24 ++
src/mainboard/via/epia-m850/romstage.c | 128 +++++++++
src/northbridge/via/vx900/Makefile.inc | 12 +
src/northbridge/via/vx900/chip.h | 52 ++++
src/northbridge/via/vx900/chrome9hd.c | 420 ++++++++++++++++++++++++++++++
src/northbridge/via/vx900/lpc.c | 201 ++++++++++++++
src/northbridge/via/vx900/northbridge.c | 345 ++++++++++++++++++++++++
src/northbridge/via/vx900/pcie.c | 142 ++++++++++
src/northbridge/via/vx900/sata.c | 270 +++++++++++++++++++
src/northbridge/via/vx900/traf_ctrl.c | 156 +++++++++++
15 files changed, 2010 insertions(+)
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
index 6980548..48f4055 100644
--- a/src/mainboard/via/Kconfig
+++ b/src/mainboard/via/Kconfig
@@ -9,6 +9,8 @@ config BOARD_VIA_EPIA_CN
bool "EPIA-CN"
config BOARD_VIA_EPIA_M700
bool "EPIA-M700"
+config BOARD_VIA_EPIA_M850
+ bool "EPIA-M850"
config BOARD_VIA_EPIA_M
bool "EPIA-M"
config BOARD_VIA_EPIA_N
@@ -23,6 +25,7 @@ endchoice
source "src/mainboard/via/epia/Kconfig"
source "src/mainboard/via/epia-cn/Kconfig"
source "src/mainboard/via/epia-m700/Kconfig"
+source "src/mainboard/via/epia-m850/Kconfig"
source "src/mainboard/via/epia-m/Kconfig"
source "src/mainboard/via/epia-n/Kconfig"
source "src/mainboard/via/pc2500e/Kconfig"
diff --git a/src/mainboard/via/epia-m850/Kconfig b/src/mainboard/via/epia-m850/Kconfig
new file mode 100644
index 0000000..6c840a6
--- /dev/null
+++ b/src/mainboard/via/epia-m850/Kconfig
@@ -0,0 +1,50 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+if BOARD_VIA_EPIA_M850
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_VIA_NANO
+ select NORTHBRIDGE_VIA_VX900
+ select SUPERIO_FINTEK_F81865F
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select HAVE_MP_TABLE
+ #select HAVE_OPTION_TABLE
+ #select HAVE_ACPI_TABLES
+ #select HAVE_ACPI_RESUME
+ #select BOARD_HAS_FADT
+ select BOARD_ROMSIZE_KB_512
+ select DRIVERS_GENERIC_IOAPIC
+
+config MAINBOARD_DIR
+ string
+ default via/epia-m850
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "EPIA-M850"
+
+config IRQ_SLOT_COUNT
+ int
+ default 13
+
+endif # BOARD_VIA_EPIA_M850
diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc
new file mode 100644
index 0000000..9c6d31f
--- /dev/null
+++ b/src/mainboard/via/epia-m850/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c
+
diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb
new file mode 100644
index 0000000..3ee56b4
--- /dev/null
+++ b/src/mainboard/via/epia-m850/devicetree.cb
@@ -0,0 +1,111 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+chip northbridge/via/vx900 # Northbridge
+ register "assign_pex_to_dp" = "0"
+ register "pcie_port1_2_lane_wide" = "1"
+ register "ext_int_route_to_pirq" = "'H'"
+
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/via/nano # VIA NANO
+ device lapic 0 on end # APIC
+ end
+ end
+ device domain 0 on
+ device pci 0.0 on end # [0410] Host controller
+ device pci 0.1 on end # [1410] Error Reporting
+ device pci 0.2 on end # [2410] CPU Bus Control
+ device pci 0.3 on end # [3410] DRAM Bus Control
+ device pci 0.4 on end # [4410] Power Management
+ device pci 0.5 on # [5410] APIC+Traffic Control
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "0"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "1"
+ register "base" = "0xfecc0000"
+ device ioapic 2 on end
+ end
+ end
+ device pci 0.6 off end # [6410] Scratch Registers
+ device pci 0.7 on end # [7410] V4 Link Control
+ device pci 1.0 on # [7122] VGA Chrome9 HD
+ ioapic_irq 2 INTA 0x28
+ end
+ device pci 1.1 on # [9170] Audio Device
+ ioapic_irq 2 INTA 0x29
+ end
+ device pci 3.0 on end # [a410] PEX1
+ device pci 3.1 on end # [b410] PEX2
+ device pci 3.2 on end # [c410] PEX3
+ device pci 3.3 on end # [d410] PEX4
+ device pci 3.4 on end # [e410] PCIE bridge
+ device pci b.0 on end # [a409] USB Device
+ device pci c.0 off end # [95d0] SDIO Host Controller
+ device pci d.0 off end # [9530] Memory Card controller
+ device pci f.0 on # [9001] SATA Controller
+ ioapic_irq 1 INTA 0x15
+ end
+ device pci 10.0 on end # [3038] USB 1.1
+ device pci 10.1 on end # [3038] USB 1.1
+ device pci 10.2 on end # [3038] USB 1.1
+ device pci 10.3 on end # [3038] USB 1.1
+ device pci 10.4 on end # [3104] USB 2.0
+ device pci 11.0 on # [8410] LPC Bus Control
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "1"
+ register "base" = "0xfec00000"
+ device ioapic 1 on end
+ end
+ #chip drivers/generic/generic # DIMM 0 channel 1
+ # device i2c 50 on end
+ #end
+ #chip drivers/generic/generic # DIMM 1 channel 1
+ # device i2c 51 on end
+ #end
+ chip superio/fintek/f81865f # Super duper IO
+ device pnp 4e.0 off end # Floppy
+ device pnp 4e.3 off end # Parallel Port
+ device pnp 4e.4 off end # Hardware Monitor
+ device pnp 4e.5 off end # Keyboard not here
+ device pnp 4e.6 off end # GPIO
+ device pnp 4e.a off end # PME
+ device pnp 4e.10 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.11 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.12 on # COM3
+ io 0x60 = 0x3e8
+ irq 0x70 = 10
+ end
+ device pnp 4e.13 on # COM4
+ io 0x60 = 0x2e8
+ irq 0x70 = 11
+ end
+ end # superio/fintek/f81865f
+ end # LPC
+ device pci 11.7 on end # [a353] North-South control
+ device pci 14.0 on end # [3288] Azalia HDAC
+ end
+end
diff --git a/src/mainboard/via/epia-m850/irq_tables.c b/src/mainboard/via/epia-m850/irq_tables.c
new file mode 100644
index 0000000..28fbb4f
--- /dev/null
+++ b/src/mainboard/via/epia-m850/irq_tables.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <string.h> /* <- For memset */
+
+#define _OFF 0x00
+#define ___OFF 0x0000
+#define LNKA 1
+#define LNKB 2
+#define LNKC 3
+#define LNKD 4
+#define LNKE 5
+#define LNKF 6
+#define LNKG 7
+#define LNKH 8
+#define BITMAP 0xdce0
+/* The link that carries the SATA interrupt has its own mask, just in case
+ * we want to make sure our SATA controller gets mapped to IRQ 14 */
+#define B_SATA BITMAP
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 13, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x11 << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively for PCI */
+ PCI_VENDOR_ID_VIA, /* Vendor */
+ PCI_DEVICE_ID_VIA_VX900_LPC, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x19, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum). */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
+ {0x00, (0x03 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0},
+ {0x00, (0x0b << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
+ {0x00, (0x0c << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
+ {0x00, (0x0d << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
+ {0x00, (0x0f << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
+ {0x00, (0x10 << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0},
+ {0x00, (0x14 << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0},
+ {0x01, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x1, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x2, 0x0},
+ {0x03, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0},
+ {0x04, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c
new file mode 100644
index 0000000..57b12e1
--- /dev/null
+++ b/src/mainboard/via/epia-m850/mainboard.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA EPIA-M850 Mainboard")
+};
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
new file mode 100644
index 0000000..49dd52b
--- /dev/null
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Inspired from the EPIA-M700
+ */
+#undef CONFIG_COLLECT_TIMESTAMPS
+#define CONFIG_COLLECT_TIMESTAMPS 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/io.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <lib.h>
+#include <cpu/x86/bist.h>
+#include <string.h>
+#include <timestamp.h>
+
+#include <console/cbmem_console.h>
+
+#include "northbridge/via/vx900/early_vx900.h"
+#include "northbridge/via/vx900/raminit.h"
+#include "superio/fintek/f81865f/f81865f_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, 0x10)
+
+static inline u64 tsc2u64(tsc_t tsc)
+{
+ return ((u64)tsc.hi << 32) | tsc.lo;
+}
+#define TSC_PER_USEC 1297
+static inline u32 tsc2ms(u64 end, u64 start)
+{
+ return ((u32)(end-start)/TSC_PER_USEC)/1000;
+}
+/* cache_as_ram.inc jumps to here. */
+void main(unsigned long bist);
+void main(unsigned long bist)
+{
+ u32 tolm;
+ tsc_t tsc_at_romstage_start = rdtsc();;
+
+ /* First thing we need to do on the VX900, before anything else */
+ vx900_enable_pci_config_space();
+
+ f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ print_debug("Console initialized. \n");
+
+ vx900_cpu_bus_interface_setup();
+
+ /* Be smart. Get this info */
+ vx900_print_strapping_info();
+ /* DEVEL helper */
+ vx900_disable_auto_reboot();
+ /* Halt if there was a built-in self test failure. */
+ report_bist_failure(bist);
+
+ /* Oh, almighty, give us the SMBUS */
+ enable_smbus();
+
+ tsc_t tsc_before_raminit = rdtsc();
+ /* Now we can worry about raminit.
+ * This board only has DDR3, so no need to worry about which DRAM type
+ * to use */
+ dimm_layout dimms = {{0x50, 0x51, SPD_END_LIST}};
+ vx900_init_dram_ddr3(&dimms);
+ tsc_t tsc_after_raminit = rdtsc();
+
+ ram_check(0, 0x80);
+ ram_check(512<<10, 0x80);
+ ram_check((1<<20) - (1<<10), 0x80);
+ ram_check((1<<24), 0x80);
+ ram_check((512 + 256 -1)<<20, 0x80);
+ ram_check(0x80c0000, 0x80);
+ tolm = ((pci_read_config16(MCU, 0x84) & 0xfff0) >> 4) << 20;
+ if (tolm > (1 * (u32)GiB))
+ ram_check(1024<<10, 0x80);
+ if (tolm > (2 * (u32)GiB))
+ ram_check(2048<<20, 0x80);
+
+ print_debug("We passed RAM verify\n");
+#ifdef GONFIG_EARLY_CBMEM_INIT
+ /* We got RAM working, now we can write the timestamps to RAM */
+ cbmem_initialize();
+ timestamp_init(tsc_at_romstage_start);
+ timestamp_add(TS_START_ROMSTAGE, tsc_at_romstage_start );
+ timestamp_add(TS_BEFORE_INITRAM, tsc_before_raminit );
+ timestamp_add(TS_AFTER_INITRAM, tsc_after_raminit );
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+ /* FIXME: Take this out please */
+ /* This disables our USB */
+ //pci_write_config8(LPC, 0x50, ~(1<<3));
+ /* This eviscerates our VGA out of existence */
+ //pci_mod_config16(MCU, 0xa0, (1 << 15), 0);
+ /* Disable Memcard and SDIO */
+ pci_mod_config8(LPC, 0x51, 0, (1<<7) | (1<<4));
+
+ /* FIXME: They no es belong here */
+ u64 start, end;
+ start = tsc2u64(tsc_at_romstage_start);
+ end = tsc2u64(tsc_before_raminit);
+ printk(BIOS_DEBUG, "Before raminit %ums\n", tsc2ms(end, start));
+
+ start = end;
+ end = tsc2u64(tsc_after_raminit);
+ printk(BIOS_DEBUG, "Actual Raminit %ums\n", tsc2ms(end, start));
+}
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 1586c87..13d7de6 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -31,6 +31,18 @@ romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c
romstage-y += ./../../../drivers/pc80/udelay_io.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += ./../../../lib/cbmem.c
+ramstage-y += pci_util.c
+ramstage-y += pcie.c
+ramstage-y += northbridge.c
+ramstage-y += chrome9hd.c
+ramstage-y += traf_ctrl.c
+ramstage-y += sata.c
+ramstage-y += lpc.c
+
+# The buildsystem only includes this file if CONFIG_VGA is selected.
+# We need to do some VGA I/O before the VGA can be initialized. We can make good
+# use of some of the functions there, so include them unconditionally
+ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h
new file mode 100644
index 0000000..6334a8e
--- /dev/null
+++ b/src/northbridge/via/vx900/chip.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+struct northbridge_via_vx900_config {
+ /**
+ * \brief PCIe Lane[3:0] Function Select
+ *
+ * PCIe Lane3~Lane0 (PEXTX[3:0]P/VCC) can be used by the integrated
+ * graphic controller to output its display data. The PCIe lanes will
+ * be used to output DisplayPort data.
+ */
+ u8 assign_pex_to_dp;
+
+ /**
+ * \brief Lane Width for Root Port 1
+ *
+ * Two PCIe lanes are used for Root port 1. Root port 2 is disabled.
+ */
+ u8 pcie_port1_2_lane_wide;
+
+ /**
+ * \brief PIRQ line to which to route the external interrupt
+ *
+ * The VX900 features an external interrupt which can be routed to any
+ * of the PIRQA->PIRQH lines. Usually, on-board devices are connected
+ * to the external interrupt. In some vendor BIOS's pirq table, this
+ * appears as link 9.
+ *
+ * Setting this line only affects the behavior of the integrated PIC. It
+ * has no effect on the IOAPIC.
+ *
+ * The value of this register must be a literal upper-case character
+ * from 'A' to 'H'.
+ */
+ char ext_int_route_to_pirq;
+};
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
new file mode 100644
index 0000000..b164699
--- /dev/null
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -0,0 +1,420 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arch/io.h>
+#include <config.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/vga_io.h>
+
+#include "vx900.h"
+
+#define CHROME_9_HD_MIN_FB_SIZE 8
+#define CHROME_9_HD_MAX_FB_SIZE 512
+
+/**
+ * @file chrome9hd.c
+ *
+ * \brief Initialization for Chrome9HD integrated graphics adapters
+ *
+ * This takes care of the initialization we need to do before calling the VGA
+ * BIOS. The device is not documented in the VX900 datasheet.
+ *
+ * The device is documented in:
+ *
+ * Open Graphics Programming Manual
+ * Chrome9GraphicsHD Processor
+ * VX900 Series System Processor
+ * Part I: Graphics Core / 2D
+ *
+ * This document was released by VIA to the Xorg project, and is available at:
+ * <http://www.x.org/docs/via/OGPM_Chrome9%20HD%20DX9%20_R100_PartI_Core_2D.pdf>
+ */
+
+/* Helper to determine the framebuffer size */
+u32 chrome9hd_fb_size(void)
+{
+ static u32 fb_size = 0;
+ u8 reg8, ranksize;
+ u32 size_mb, tom_mb, max_size_mb;
+ int i;
+ /* We do some PCI and CMOS IO to find our value, so if we've already
+ * found it, save some time */
+ if (fb_size != 0)
+ return fb_size;
+ /* FIXME: read fb_size from CMOS, but until that is implemented, start
+ * from 512MB */
+ size_mb = 512;
+
+ /* The minimum framebuffer size is 8MB. */
+ size_mb = max(size_mb, CHROME_9_HD_MIN_FB_SIZE);
+
+ const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
+ 0);
+ /*
+ * We have two limitations on the maximum framebuffer size:
+ * 1) (Sanity) No more that 1/4 of system RAM
+ * 2) (Hardware limitation) No larger than DRAM in last rank
+ * Check both of these limitations and apply them to our framebuffer */
+ tom_mb = (pci_read_config16(mcu, 0x88) & 0x07ff) << (24 - 20);
+ max_size_mb = tom_mb >> 2;
+ if (size_mb > max_size_mb) {
+ printk(BIOS_ALERT, "The framebuffer size of of %dMB is larger"
+ " than 1/4 of available memory.\n"
+ " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
+ size_mb = max_size_mb;
+ }
+
+ /* Now handle limitation #2
+ * Look at the ending address of the memory ranks, from last to first,
+ * until we find one that is not zero. That is our last rank, and its
+ * size is the limit of our framebuffer. */
+ /* FIXME: This has a bug. If we remap memory above 4G, we consider the
+ * memory hole as part of our RAM. Thus if we install 3G, with a TOLM of
+ * 2.5G, our TOM will be at 5G and we'll assume we have 5G RAM instead
+ * of the actual 3.5G */
+ for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) {
+ reg8 = pci_read_config8(mcu, 0x40 + i);
+ if (reg8 == 0)
+ continue;
+ /* We've reached the last populated rank */
+ ranksize = reg8 - pci_read_config8(mcu, 0x48 + i);
+ max_size_mb = ranksize << 6;
+ /* That's it. We got what we needed. */
+ break;
+ };
+ if (size_mb > max_size_mb) {
+ printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"
+ " than size of the last DRAM rank.\n"
+ " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
+ size_mb = max_size_mb;
+ }
+
+ /* Now round the framebuffer size to the closest power of 2 */
+ u8 fb_pow = 0;
+ while (size_mb >> fb_pow)
+ fb_pow++;
+ fb_pow--;
+ size_mb = (1 << fb_pow);
+ /* We store the framebuffer size in bytes, for simplicity */
+ fb_size = size_mb << 20;
+ return fb_size;
+}
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+
+#include <arch/interrupt.h>
+#include <x86emu/x86emu.h>
+
+/**
+ * \brief INT15 helpers for Chrome9HD IGP
+ *
+ * These INT15 callbacks are needed for the VGA BIOS to operate correctly. They
+ * are described in:
+ *
+ * VIA/S3Graphics
+ * Video BIOS External Interface Specification for Chrome9 Series IGP
+ * VX900 Series
+ *
+ * This document is only available under NDA, however, the callbacks are very
+ * similar to other VIA/Intel IGP callbacks.
+ *
+ * Callback 0x5f18 is the most important one. It informs the VGA BIOS of the
+ * RAM speed and framebuffer size. The other callbacks seem to be optional.
+ *
+ * Note that SeaBIOS will overwrite these callbacks.
+ */
+#include "vx900_int15.h"
+static int vx900_int15_handler(void)
+{
+ int res;
+
+ printk(BIOS_DEBUG, "%s %0x\n", __func__, X86_AX & 0xffff);
+ /* Set AX return value here so we don't set it every time. Just set it
+ * to something else if the callback is unsupported */
+ res = -1;
+ switch (X86_AX & 0xffff) {
+#if 0
+ case 0x5f01:
+ /* VGA POST - panel type */
+ /* FIXME: Don't hardcode panel type */
+ /* Panel Type Number */
+ X86_CX = 0;
+ res = 0;
+ break;
+ case 0x5f02:
+ {
+ /* Boot device selection */
+ X86_BL = INT15_5F02_BL_HWOPT_CRTCONN;
+ X86_BH = 0;// INT15_5F02_BH_TV_CONN_DEFAULT; /* FIXME: or 0 ? */
+ X86_EBX =0;// INT15_5F02_EBX_HDTV_RGB;
+ X86_ECX = INT15_5F02_ECX_DISPLAY_CRT;
+ //X86_ECX |= INT15_5F02_ECX_TV_MODE_RGB;
+ //X86_ECX |= INT15_5F02_ECX_HDTV_1080P;
+ X86_DL = INT15_5F02_DL_TV_LAYOUT_DEFAULT;
+ res = 0;
+ break;
+ }
+#endif
+ case 0x5f18:
+ {
+ u8 reg8;
+ /*
+ * BL Bit[7:4]
+ * Memory Data Rate (not to be confused with fCLK)
+ * 0000: 66MHz
+ * 0001: 100MHz
+ * 0010: 133MHz
+ * 0011: 200MHz ( DDR200 )
+ * 0100: 266MHz ( DDR266 )
+ * 0101: 333MHz ( DDR333 )
+ * 0110: 400MHz ( DDR400 )
+ * 0111: 533MHz ( DDR I/II 533
+ * 1000: 667MHz ( DDR I/II 667)
+ * 1001: 800MHz
+ * 1010: 1066MHz
+ * 1011: 1333MHz
+ * Bit[3:0]
+ * N: Frame Buffer Size 2^N MB
+ */
+ device_t dev;
+ dev = dev_find_slot(0, PCI_DEVFN(0, 3));
+ reg8 = pci_read_config8(dev, 0xa1);
+ X86_BX = (u32) ((reg8 & 0x70) >> 4) + 2;
+ reg8 = pci_read_config8(dev, 0x90);
+ reg8 = ((reg8 & 0x07) + 3) << 4;
+ X86_BX |= (u32) reg8;
+ res = 0;
+ break;
+ }
+#if 0
+ case 0x5f2a:
+ /* Get SSC Control Settings */
+ /* FIXME: No idea what this does. Just disable this feature
+ * for now */
+ X86_CX = INT15_5F2A_CX_SSC_ENABLE;
+ res = 0;
+ break;
+ case 0x5f2b:
+ /* Engine clock setting */
+ X86_EBX = INT15_5F2B_EBX_ECLK_250MHZ; /* FIXME: ECLK fixed 250MHz ? */
+ break;
+#endif
+ default:
+ printk(BIOS_DEBUG, "Unsupported INT15 call %04x!\n",
+ X86_AX & 0xffff);
+ X86_AX = 0;
+ res = -1;
+ break;
+ }
+
+ if (res == 0)
+ X86_AX = 0x5f;
+ else
+ X86_AX = 0;
+ return res;
+}
+
+static void vx900_vga_set_int15_handler(void)
+{
+ printk(BIOS_DEBUG, "Our int15 handler is at %p\n",
+ &vx900_int15_handler);
+ mainboard_interrupt_handlers(0x15, &vx900_int15_handler);
+};
+
+#else
+static void vx900_vga_set_int15_handler(void)
+{
+ /* Stub */
+};
+#endif
+
+static void chrome9hd_set_sid_vid(u16 vendor, u16 device)
+{
+ vga_sr_write(0x36, vendor >> 8); /* SVID high byte */
+ vga_sr_write(0x35, vendor & 0xff); /* SVID low byte */
+ vga_sr_write(0x38, device >> 8); /* SID high byte */
+ vga_sr_write(0x37, device & 0xff); /* SID low byte */
+}
+
+static void chrome9hd_handle_uma(device_t dev)
+{
+ /* Mirror mirror, shiny glass, tell me that is not my ass */
+ u32 fb_size = chrome9hd_fb_size() >> 20;
+
+ //uma_resource(dev, 0x18, uma_memory_base>>10, uma_memory_size>>10);
+
+ printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base,
+ uma_memory_base >> 20);
+ printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size,
+ uma_memory_size >> 20);
+ u8 fb_pow = 0;
+ while (fb_size >> fb_pow)
+ fb_pow++;
+ fb_pow--;
+
+ /* Step 6 - Let MCU know the framebuffer size */
+ device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
+ pci_mod_config8(mcu, 0xa1, 7 << 4, (fb_pow - 2) << 4);
+
+ /* Step 7 - Let GFX know the framebuffer size (through PCI and IOCTL)
+ * The size we set here affects the behavior of BAR2, and the amount of
+ * MMIO space it requests. The default is 512MB, so if we don't set this
+ * before reading the resources, we could waste space below 4G */
+ pci_write_config8(dev, 0xb2, ((0xff << (fb_pow - 2)) & ~(1 << 7)));
+ vga_sr_write(0x68, (0xff << (fb_pow - 1)));
+ /* And also that the framebuffer is in the system, RAM */
+ pci_mod_config8(dev, 0xb0, 0, 1 << 0);
+}
+
+/**
+ * \brief Initialization sequence before running the VGA BIOS
+ *
+ * This is the initialization sequence described in:
+ *
+ * BIOS Porting Guide
+ * VX900 Series
+ * All-in-One System Processor
+ *
+ * This document is only available under NDA.
+ */
+static void chrome9hd_biosguide_init_seq(device_t dev)
+{
+ device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
+ device_t host = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0);
+
+ /* Step 1 - Enable VGA controller */
+ /* FIXME: This is the VGA hole @ 640k-768k, and the vga port io
+ * We need the port IO, but can we disable the memory hole? */
+ pci_mod_config8(mcu, 0xa4, 0, (1 << 7)); /* VGA memory hole */
+
+ /* Step 2 - Forward MDA cycles to GFX */
+ pci_mod_config8(host, 0x4e, 0, (1 << 1));
+
+ /* Step 3 - Enable GFX I/O space */
+ pci_mod_config8(dev, PCI_COMMAND, 0, PCI_COMMAND_IO);
+
+ /* Step 4 - Enable video subsystem */
+ vga_enable_mask((1 << 0), (1 << 0));
+
+ /* FIXME: VGA IO Address Select. 3B5 or 3D5? */
+ vga_misc_mask((1 << 0), (1 << 0));
+
+ /* Step 5 - Unlock accessing of IO space */
+ vga_sr_write(0x10, 0x01);
+
+ chrome9hd_handle_uma(dev);
+
+ /* Step 8 - Enable memory base register on the GFX */
+ if (uma_memory_base == 0)
+ die("uma_memory_base not set. Abandon ship!\n");
+ printk(BIOS_DEBUG, "UMA base 0x%.10llx (%lluMB)\n", uma_memory_base,
+ uma_memory_base >> 20);
+ vga_sr_write(0x6d, (uma_memory_base >> 21) & 0xff); /* base 28:21 */
+ vga_sr_write(0x6e, (uma_memory_base >> 29) & 0xff); /* base 36:29 */
+ vga_sr_write(0x6f, 0x00); /* base 43:37 */
+
+ /* Step 9 - Set SID/VID */
+ chrome9hd_set_sid_vid(0x1106, 0x7122);
+
+}
+
+static void chrome9hd_init(device_t dev)
+{
+ print_debug("======================================================\n");
+ print_debug("== Chrome9 HD INIT\n");
+ print_debug("======================================================\n");
+
+ chrome9hd_biosguide_init_seq(dev);
+
+ /* Prime PLL FIXME: bad comment */
+ vga_sr_mask(0x3c, 1 << 2, 1 << 2);
+
+ //VGA IO Address Select. 3B5 or 3D5?
+ vga_misc_mask(1 << 0, 1 << 0);
+
+ //enable Base VGA 16 Bits Decode
+ //pci_mod_config8(host, 0x4e, 0, 1<<4);
+
+ vx900_vga_set_int15_handler();
+
+ u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
+ fb_address &= ~0x0F;
+ if (!fb_address) {
+ printk(BIOS_WARNING, "Chrome9HD: No FB BAR assigned!\n");
+ return;
+ }
+
+ printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
+ 256, fb_address);
+
+ printk(BIOS_DEBUG, "Initializing VGA...\n");
+
+ pci_dev_init(dev);
+
+ printk(BIOS_DEBUG, "Enable VGA console\n");
+
+ dump_pci_device(dev);
+}
+
+static void chrome9hd_enable(device_t dev)
+{
+ print_debug("======================================================\n");
+ print_debug("== Chrome9 HD ENABLE\n");
+ print_debug("======================================================\n");
+
+ device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
+ /* FIXME: here? -=- ACLK 250Mhz */
+ pci_mod_config8(mcu, 0xbb, 0, 0x01);
+}
+
+static void chrome9hd_disable(device_t dev)
+{
+ print_debug("======================================================\n");
+ print_debug("== Chrome9 HD DISABLE\n");
+ print_debug("======================================================\n");
+
+ device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
+ /* Disable GFX - This step effectively renders the GFX inert
+ * It won't even show up as a PCI device during enumeration */
+ pci_mod_config8(mcu, 0xa1, 1 << 7, 0);
+}
+
+static struct device_operations chrome9hd_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = chrome9hd_init,
+ .disable = chrome9hd_disable,
+ .enable = chrome9hd_enable,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver chrome9hd_driver __pci_driver = {
+ .ops = &chrome9hd_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_VGA,
+};
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
new file mode 100644
index 0000000..31501bb
--- /dev/null
+++ b/src/northbridge/via/vx900/lpc.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/i8259.h>
+#include <pc80/mc146818rtc.h>
+#include <drivers/generic/ioapic/chip.h>
+
+#include "vx900.h"
+#include "chip.h"
+
+static void vx900_lpc_misc_stuff(device_t dev)
+{
+ char extint;
+ u8 val;
+ struct northbridge_via_vx900_config *nb = (void*)dev->chip_info;
+
+ /* GPIO 11,10 to SATALED [1,0] */
+ pci_mod_config8(dev, 0xe4, 0 , 1<<0);
+
+ /* Route the external interrupt line */
+ extint = nb->ext_int_route_to_pirq;
+ if (extint < 'A' || extint > 'H') {
+ printk(BIOS_WARNING, "Invalid PIRQ%c for external interrupt\n",
+ extint);
+ } else {
+ printk(BIOS_INFO, "Routing external interrupt to PIRQ%c\n",
+ extint);
+ val = extint - 'A';
+ val |= (1 << 3); /* bit3 enables the external int */
+ pci_mod_config8(dev, 0x55, 0xf, val);
+
+ }
+}
+
+static void vx900_lpc_dma_setup(device_t dev)
+{
+ /* These are the steps recommended by VIA in order to get DMA running */
+
+ /* Enable Positive South Module PCI Cycle Decoding */
+ /* FIXME: Setting this seems to hang our system */
+ //pci_mod_config8(dev, 0x58, 0, 1<<4);
+ /* Positive decoding for ROM + APIC + On-board IO ports */
+ pci_mod_config8(dev, 0x6c, 0, (1<<2) | (1<<3) | (1<<7));
+ /* Enable DMA channels. BIOS guide recommends DMA channel 2 off */
+ pci_write_config8(dev, 0x53, 0xfb);
+ /* Disable PCI/DMA Memory Cycles Output to PCI Bus */
+ pci_mod_config8(dev, 0x5b, (1<<5), 0);
+ /* DMA bandwidth control - Improved bandwidth */
+ pci_write_config8(dev, 0x53, 0xff);
+ /* ISA Positive Decoding control */
+ pci_write_config8(dev, 0x6d, 0xdf);
+ pci_write_config8(dev, 0x6e, 0x98);
+ pci_write_config8(dev, 0x6f, 0x30);
+}
+
+/**
+ *\brief VX900: Set up the south module IOAPIC (for the ISA/LPC bus)
+ *
+ * Enable the IOAPIC in the south module, and properly set it up.
+ * \n
+ * This is the hardware specific initialization for the IOAPIC, and complements
+ * the setup done by the generic IOAPIC driver. In order for the IOAPIC to work
+ * properly, it _must_ be declared in devicetree.cb .
+ * \n
+ * We are assuming this is called before the drivers/generic/ioapic code,
+ * which should be the case if devicetree.cb is set up properly.
+ */
+static void vx900_lpc_ioapic_setup(device_t dev)
+{
+ /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb
+ * If it's not, then the generic ioapic driver will not set it up
+ * correctly, and the MP table will not be correctly generated */
+ device_t ioapic;
+ for(ioapic = dev->next; ioapic; ioapic = ioapic->next)
+ {
+ if(ioapic->path.type == DEVICE_PATH_IOAPIC)
+ break;
+ }
+
+ /* You did put an IOAPIC in devicetree.cb, didn't you? */
+ if(ioapic == 0) {
+ /* We don't have enough info to set up the IOAPIC */
+ printk(BIOS_ERR, "ERROR: South module IOAPIC not found. "
+ "Check your devicetree.cb\n");
+ return;
+ }
+
+ /* Found an IOAPIC, now we need to make sure it's the right one */
+ ioapic_config_t *config = (ioapic_config_t*)ioapic->chip_info;
+ if(!config->have_isa_interrupts) {
+ /* Umh, is this the right IOAPIC ? */
+ printk(BIOS_ERR, "ERROR: South module IOAPIC not carrying ISA "
+ "interrupts. Check your devicetree.cb\n");
+ printk(BIOS_ERR, "Will not initialize this IOAPIC.\n");
+ return;
+ }
+
+ /* The base address of this IOAPIC _must_ be at 0xfec00000.
+ * Don't move this value to a #define, as people might think it's
+ * configurable. It is not. */
+ const u32 base = config->base;
+ if(base != 0xfec00000) {
+ printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at "
+ "0xfec00000\n but we found it at 0x%.8x\n",
+ base);
+ return;
+ }
+
+ print_debug("VX900 LPC: Setting up the south module IOAPIC.\n");
+ /* Enable IOAPIC
+ * So much work for one line of code. Talk about bloat :)
+ * The 8259 PIC should still work even if the IOAPIC is enabled, so
+ * there's no crime in enabling the IOAPIC here. */
+ pci_mod_config8(dev, 0x58, 0, 1<<6);
+}
+
+static void vx900_lpc_interrupt_stuff(device_t dev)
+{
+ /* Enable setting trigger mode through 0x4d0, and 0x4d1 ports
+ * And enable I/O recovery time */
+ pci_mod_config8(dev, 0x40, 0, (1<<2)|(1<<6));
+ /* Set serial IRQ frame width to 6 PCI cycles (recommended by VIA)
+ * And enable serial IRQ */
+ pci_mod_config8(dev, 0x52, 3<<0, (1<<3)|(1<<0) );
+
+ /* Disable IRQ12 storm FIXME: bad comment */
+ pci_mod_config8(dev, 0x51, (1<<2), 0);
+
+ pci_write_config8(dev, 0x4c, (1<<6) );
+
+ /* Get the IRQs up and running. SeaBIOS/linux needs these to boot */
+ setup_i8259();
+
+ vx900_lpc_dma_setup(dev);
+
+ /* The IOAPIC is special, and we treat it separately */
+ vx900_lpc_ioapic_setup(dev);
+}
+
+static void vx900_lpc_init(device_t dev)
+{
+ vx900_lpc_interrupt_stuff(dev);
+ vx900_lpc_misc_stuff(dev);
+ dump_pci_device(dev);
+}
+
+static struct device_operations vx900_lpc_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vx900_lpc_init,
+ .scan_bus = scan_static_bus,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+ .ops = &vx900_lpc_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_LPC,
+};
+
+#if CONFIG_PIRQ_ROUTE
+void pirq_assign_irqs(const u8* pirq)
+{
+ device_t lpc;
+
+ lpc = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_LPC, 0);
+
+ /* Take care of INTA -> INTD */
+ pci_mod_config8(lpc, 0x55, (0xf << 4), pirq[0] << 4);
+ pci_write_config8(lpc, 0x56, pirq[1] | (pirq[2] << 4) );
+ pci_write_config8(lpc, 0x57, pirq[3] << 4);
+
+ /* Enable INTE -> INTH to be on separate IRQs */
+ pci_mod_config8(lpc, 0x46, 0, 1<<4);
+ /* Now do INTE -> INTH */
+ pci_write_config8(lpc, 0x44, pirq[4] | (pirq[5] << 4) );
+ pci_write_config8(lpc, 0x45, pirq[6] | (pirq[7] << 4) );
+}
+#endif
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
new file mode 100644
index 0000000..901b3a0
--- /dev/null
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -0,0 +1,345 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "vx900.h"
+#include "chip.h"
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cbmem.h>
+#include <lib.h>
+#include <reset.h>
+#include <string.h>
+
+#define RAM_4GB (((u64)1) << 32)
+
+void hard_reset(void)
+{
+ outb((1 << 2) | (1 << 1), 0xcf9);
+}
+
+static u64 vx900_get_top_of_ram(device_t mcu)
+{
+ u16 reg16;
+ /* The last valid DRAM address is computed by the MCU
+ * One issue might be if we have a hole in the rank mappings, so that
+ * virtual ranks are not mapped successively in the linear address space
+ * (Ex: rank 0 mapped 0-1G, rank 1 mapped 2G-3G)
+ * We don't do this awkward mapping in RAM init, so we don't worry about
+ * it here, but it is something to keep in mind if having RAM issues */
+ reg16 = pci_read_config16(mcu, 0x88) & 0x07ff;
+ return (u64)reg16 << 24;
+}
+
+static void shit_debug_map(u32 shit)
+{
+ if (shit & (1 << 0))
+ print_debug("Mem remapping enabled\n");
+ u64 remapstart = (shit >> 2) & 0x3ff;
+ u64 remapend = (shit >> 14) & 0x3ff;
+ remapstart <<= 26;
+ remapend <<=26;
+ printk(BIOS_DEBUG, "Remapstart %lld(MB) \n", remapstart >> 20);
+ printk(BIOS_DEBUG, "Remapend %lld(MB) \n", remapend >> 20);
+}
+/**
+ * \brief Remap memory colliding with PCI MMIO space, above 4G
+ *
+ * @param mcu The memory controller
+ * @param tolm Top of low memory.
+ *
+ * @return The new top of memory.
+ */
+static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
+{
+ size_t i;
+ u8 reg8, start8, end8, start, end;
+ u16 reg16;
+ u32 reg32;
+ u64 tor, newtor, chunk;
+
+ /*
+ * The remapping mechanism works like this:
+ *
+ * - Choose the top of low memory.
+ * This becomes the "remap from"
+ * - Choose a chunk above 4G where to remap.
+ * This becomes "remap to"
+ * - Choose a chunk above 4G where to end the remapping.
+ * This becomes "remap until"
+ *
+ * This remaps a "chunk" of memory where we want to.
+ * sizeof(chunk) = until - to;
+ *
+ * Therefore the memory region from "from" to " from + sizeof(chunk)"
+ * becomes accessible at "to" to "until"
+ */
+ if (tolm >= vx900_get_top_of_ram(mcu)) {
+ print_debug("Nothing to remap\n");
+ }
+
+ shit_debug_map(0x00180141);
+ /* We can remap with a granularity of 64MB, so align tolm */
+ /*
+ * OK, I know I'll get asked what the hell this bit operation is
+ * supposed to do. We want to align tolm to 64MB, so we need to clear
+ * all bits which are more granular than that. When we take 64MB and
+ * subtract 1 from it, we get all the bits we want to clear to be 1.
+ * This works because 64MiB is a power of two. Now we want to clear the
+ * bits that are 1, so we need to invert them. Now we have a mask which
+ * has the bits we want to clear all 0. AND with that.
+ */
+ tolm &= ~((64 * MiB) - 1);
+
+ /* The "start remapping from where ?" register */
+ reg16 = ((tolm >> 20) & 0xfff) << 4;
+ pci_mod_config16(mcu, 0x84, 0xfff0, reg16);
+
+ /* Find the chunk size */
+ tor = vx900_get_top_of_ram(mcu);
+ printk(BIOS_DEBUG, "tor %lldMB\n", tor>>20);
+
+ if (tor < RAM_4GB) {
+ chunk = tor - tolm;
+ newtor = RAM_4GB + chunk;
+ } else {
+ chunk = (RAM_4GB - tolm);
+ newtor = tor + chunk;
+ }
+ printk(BIOS_DEBUG, "newtor %lldMB\n", newtor>>20);
+
+ reg8 = tolm >> 26;
+ /* Which rank does the PCI TOLM fall on? */
+ for (i = 0; i < VX900_MAX_MEM_RANKS; i++) {
+ end8 = pci_read_config8(mcu, 0x40 + i);
+ if (reg8 > end8)
+ continue;
+ start8 = pci_read_config8(mcu, 0x48 + i);
+ if (reg8 <= start8)
+ continue;
+ printk(BIOS_DEBUG, "Address %x falls on rank %ld\n",
+ tolm, i);
+ break;
+ }
+
+ for (; i < VX900_MAX_MEM_RANKS; i++) {
+ start = pci_read_config8(mcu, 0x48 + i);
+ end = pci_read_config8(mcu, 0x40 + i);
+
+ if (end == 0) {
+ printk(BIOS_DEBUG, "Huh? rank %ld empty?\n", i);
+ continue;
+ }
+
+ if (end < (tolm >> 26)) {
+ printk(BIOS_DEBUG, "Huh? rank %ld don't need remap?\n", i);
+ continue;
+ }
+
+ printk(BIOS_DEBUG, "Physical rank %u is mapped to\n"
+ " Start address: 0x%.10llx (%dMB)\n"
+ " End address: 0x%.10llx (%dMB)\n",
+ (int)i,
+ ((u64)start << 26), (start << (26 - 20)),
+ ((u64)end << 26), (end << (26 - 20)) );
+
+ if (end < (RAM_4GB >> 26))
+ end = (RAM_4GB >> 26);
+
+ if (end >= (tolm >> 26))
+ end += chunk >> 26;
+
+ if (start > (tolm >> 26))
+ start += chunk >> 26;
+
+ pci_write_config8(mcu, 0x48 + i, start);
+ pci_write_config8(mcu, 0x40 + i, end);
+
+ printk(BIOS_DEBUG, "ReMapped Physical rank %u, to\n"
+ " Start address: 0x%.10llx (%dMB)\n"
+ " End address: 0x%.10llx (%dMB)\n",
+ (int)i,
+ ((u64)start << 26), (start << (26 - 20)),
+ ((u64)end << 26), (end << (26 - 20)) );
+ }
+
+
+ /* The "remap to where?" register */
+ reg32 = ((max(tor, RAM_4GB) >> 26) & 0x3ff) << 2;
+ /* The "remap until where?" register */
+ reg32 |= ((newtor >> 26) & 0x3ff) << 14;
+ /* Now enable the goodies */
+ reg32 |= (1 << 0);
+ pci_write_config32(mcu, 0xf8, reg32);
+ printk(BIOS_DEBUG, "Wrote remap map %x\n", reg32);
+ shit_debug_map(reg32);
+
+ printk(BIOS_DEBUG, "New top of memory is at %lldMB\n", newtor>>20);
+ return newtor;
+}
+
+static void vx900_set_resources(device_t dev)
+{
+ u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
+
+ print_debug("========================================"
+ "========================================\n");
+ print_debug("============= VX900 memory sizing & Co. "
+ "========================================\n");
+ print_debug("========================================"
+ "========================================\n");
+
+ int idx = 10;
+ const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
+ 0);
+ if (!mcu) {
+ die("Something is terribly wrong.\n"
+ " We tried locating the MCU on the PCI bus, "
+ "but couldn't find it. Halting.\n");
+ }
+
+ /* How much low adrress space do we have? */
+ pci_tolm = find_pci_tolm(dev->link_list);
+ printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm);
+ printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20);
+
+ /* Figure out the total amount of RAM */
+ tomk = vx900_get_top_of_ram(mcu) >> 10;
+ printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10);
+
+ /* Do the same for top of low RAM */
+ vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4;
+ full_tolmk = vx900_tolm << (20 - 10);
+ /* FIXME: Remap above 4G */
+ full_tolmk = min(full_tolmk, pci_tolm >> 10);
+ printk(BIOS_SPEW, "Found top of low memory at %dMB\n",
+ full_tolmk >> 10);
+
+ /* What about the framebuffer for the integrated GPU? */
+ fbufk = chrome9hd_fb_size() >> 10;
+ printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk >> 10);
+
+ /* Can't use the framebuffer as system RAM, sorry */
+ //tomk -= fbufk;
+ tolmk = min(full_tolmk, tomk);
+ tolmk -= fbufk;
+ ram_resource(dev, idx++, 0, 640);
+ printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10);
+ /* FIXME: how can we avoid leaving this hole?
+ * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */
+ /* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem
+ * to be always mapped to the top of 1M, but this can be overcome with
+ * some smart positive/subtractive resource decoding */
+ ram_resource(dev, idx++, 768, (tolmk - 768));
+ uma_memory_size = fbufk << 10;
+ uma_memory_base = tolmk << 10;
+ ////uma_memory_base = (u64)tomk << 10;
+
+ printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20,
+ uma_memory_size >> 20);
+ /* FIXME: How do we handle remapping above 4G? */
+ u64 tor = vx900_remap_above_4g(mcu, pci_tolm);
+ ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10);
+
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tolmk << 10) - HIGH_MEMORY_SIZE;
+ high_tables_size = HIGH_MEMORY_SIZE;
+ printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n",
+ high_tables_base, high_tables_size);
+ /* Because of the video framebuffer, the high tables may be in a
+ * different location than in romstage, so we need to copy them over */
+/* void* old_tables = (void*)((full_tolmk<<10) - HIGH_MEMORY_SIZE);
+ void* new_tables = (void*)((u32)high_tables_base);
+ printk(BIOS_DEBUG, "Moving CBMEM from %p to %p\n",
+ old_tables, new_tables);
+ memcpy(new_tables, old_tables, HIGH_MEMORY_SIZE);
+ cbmem_reinit(high_tables_base);*/
+
+ print_debug("======================================================\n");
+ assign_resources(dev->link_list);
+}
+
+static void vx900_read_resources(device_t dev)
+{
+ /* Our fixed resources start at 0 */
+ int idx = 0;
+ /* Reserve our ROM mapped space */
+ struct resource *res;
+ res = new_resource(dev, idx++);
+ res->size = 512 * KiB;
+ res->base = 0xffffffff - (res->size - 1);
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ /* Now do the same for our MMCONF */
+ res = new_resource(dev, idx++);
+ res->size = 256 * MiB;
+ res->base = CONFIG_MMCONF_BASE_ADDRESS;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ pci_domain_read_resources(dev);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = vx900_read_resources,
+ .set_resources = vx900_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+ .ops_pci_bus = &pci_ops_mmconf,
+#else
+ .ops_pci_bus = &pci_cf8_conf1,
+#endif
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static void enable_dev(device_t dev)
+{
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
+struct chip_operations northbridge_via_vx900_ops = {
+ CHIP_NAME("VIA VX900 Chipset")
+ .enable_dev = enable_dev,
+};
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c
new file mode 100644
index 0000000..c9b04eb
--- /dev/null
+++ b/src/northbridge/via/vx900/pcie.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+
+static void dump_pci_device(device_t dev)
+{
+ int i;
+ for (i = 0; i <= 255; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+ if ((i & 7) == 0)
+ print_debug(" |");
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\n");
+ }
+ }
+}
+
+static void vx900_pcie_link_init(device_t dev)
+{
+ u8 reg8;
+ u32 reg32;
+
+ u8 fn = dev->path.pci.devfn & 0x07;
+
+ /* Step 1 : Check for presence of PCIE device */
+ reg8 = pci_read_config8(dev, 0x5a);
+
+ if (reg8 & (1 << 6) )
+ printk(BIOS_DEBUG, "Card detected in PEX%i\n", fn);
+ else
+ return;
+
+ /* Step 2: Wait for device to enter L0 state */
+ while (0x8a != pci_read_config8(dev, 0x1c3));
+
+ /* Step 3: Clear PCIe error status, then check for failures */
+ pci_write_config32(dev, 0x104, 0xffffffff);
+ reg32 = pci_read_config32(dev, 0x104);
+ if (0 != reg32) {
+ printk(BIOS_DEBUG, "PEX init error. flags 0x%.8x\n", reg32);
+ return;
+ }
+
+ pci_write_config32(dev, 0x110, 0xffffffff);
+ reg32 = pci_read_config32(dev, 0x110);
+ if (0 != reg32)
+ printk(BIOS_DEBUG, "PEX errors. flags 0x%.8x\n", reg32);
+
+ pci_write_config8(dev, 0xa4, 0xff);
+ if (pci_read_config8(dev, 0x4a) & (1 << 3))
+ print_debug("Unsupported request detected.\n");
+
+ pci_write_config8(dev, 0x15a, 0xff);
+ if (pci_read_config8(dev, 0x15a) & (1 << 1))
+ print_debug("Negotiation pending.\n");
+
+ /* Step 4: Read vendor ID */
+
+}
+
+static void vx900_pex_dev_set_resources(device_t dev)
+{
+ //print_debug("======================================================\n");
+ //print_debug("== PEX set\n");
+ //print_debug("======================================================\n");
+
+ assign_resources(dev->link_list);
+}
+
+static void vx900_pex_init(device_t dev)
+{
+ //print_debug("======================================================\n");
+ //print_debug("== PEX init\n");
+ //print_debug("======================================================\n");
+
+ if ((dev->path.pci.devfn & 0x7) == 0)
+ return;
+ vx900_pcie_link_init(dev);
+
+ if (0) dump_pci_device(dev);
+}
+
+static struct device_operations vx900_pex_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = vx900_pex_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = vx900_pex_init,
+ .scan_bus = pciexp_scan_bridge,
+ .reset_bus = pci_bus_reset,
+};
+
+static const struct pci_driver pex1_driver __pci_driver = {
+ .ops = &vx900_pex_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_PEX1,
+};
+
+static const struct pci_driver pex2_driver __pci_driver = {
+ .ops = &vx900_pex_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_PEX2,
+};
+
+static const struct pci_driver pex3_driver __pci_driver = {
+ .ops = &vx900_pex_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_PEX3,
+};
+
+static const struct pci_driver pex4_driver __pci_driver = {
+ .ops = &vx900_pex_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_PEX4,
+};
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
new file mode 100644
index 0000000..16362cd
--- /dev/null
+++ b/src/northbridge/via/vx900/sata.c
@@ -0,0 +1,270 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include "vx900.h"
+
+static void vx900_print_sata_errors(u32 flags)
+{
+ /* Status flags */
+ printk(BIOS_DEBUG, "\tPhyRdy %s\n",
+ (flags&(1<<16)) ? "changed" : "not changed");
+ printk(BIOS_DEBUG, "\tCOMWAKE %s\n",
+ (flags&(1<<16)) ? "detected" : "not detected");
+ printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n",
+ (flags&(1<<26)) ? "occured" : "not occured");
+ printk(BIOS_DEBUG, "\tPort selector presence %s\n",
+ (flags&(1<<27)) ? "detected" : "not detected");
+ /* Errors */
+ if(flags&(1<<0))
+ print_debug("\tRecovered data integrity ERROR\n");
+ if(flags&(1<<1))
+ print_debug("\tRecovered data communication ERROR\n");
+ if(flags&(1<<8))
+ print_debug("\tNon-recovered Transient Data Integrity ERROR\n");
+ if(flags&(1<<9))
+ print_debug("\tNon-recovered Persistent Communication or"
+ "\tData Integrity ERROR\n");
+ if(flags&(1<<10))
+ print_debug("\tProtocol ERROR\n");
+ if(flags&(1<<11))
+ print_debug("\tInternal ERROR\n");
+ if(flags&(1<<17))
+ print_debug("\tPHY Internal ERROR\n");
+ if(flags&(1<<19))
+ print_debug("\t10B to 8B Decode ERROR\n");
+ if(flags&(1<<20))
+ print_debug("\tDisparity ERROR\n");
+ if(flags&(1<<21))
+ print_debug("\tCRC ERROR\n");
+ if(flags&(1<<22))
+ print_debug("\tHandshake ERROR\n");
+ if(flags&(1<<23))
+ print_debug("\tLink Sequence ERROR\n");
+ if(flags&(1<<24))
+ print_debug("\tTransport State Transition ERROR\n");
+ if(flags&(1<<25))
+ print_debug("\tUNRECOGNIZED FIS type\n");
+}
+
+static void vx900_dbg_sata_errors(device_t dev)
+{
+ /* Port 0 */
+ if (pci_read_config8(dev, 0xa0) & (1<<0) ) {
+ print_debug("Device detected in SATA port 0.\n");
+ u32 flags = pci_read_config32(dev, 0xa8);
+ vx900_print_sata_errors(flags);
+ };
+ /* Port 1 */
+ if (pci_read_config8(dev, 0xa1) & (1<<0) ) {
+ print_debug("Device detected in SATA port 1.\n");
+ u32 flags = pci_read_config32(dev, 0xac);
+ vx900_print_sata_errors(flags);
+ };
+}
+
+typedef u8 sata_phy_config[64];
+
+static sata_phy_config reference_ephy = {
+ 0x80, 0xb8, 0xf0, 0xfe, 0x40, 0x7e, 0xf6, 0xdd,
+ 0x1a, 0x22, 0xa0, 0x10, 0x02, 0xa9, 0x7c, 0x7e,
+ 0x00, 0x00, 0x00, 0x00, 0x40, 0x30, 0x84, 0x8c,
+ 0x75, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x20, 0x40, 0xd0, 0x41, 0x40, 0x00, 0x00, 0x08,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x20, 0x40, 0x50, 0x41, 0x40, 0x00, 0x00, 0x00,
+ 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+static u32 sata_phy_read32(device_t dev, u8 index)
+{
+ /* The SATA PHY control registers are accessed by a funny index/value
+ * scheme. Each byte (0,1,2,3) has its own 4-bit index */
+ index = (index >> 2) & 0xf;
+ u16 i16 = index | (index<<4) | (index<<8)| (index<<12);
+ /* The index */
+ pci_write_config16(dev, 0x68, i16);
+ /* The value */
+ return pci_read_config32(dev, 0x64);
+}
+
+static void sata_phy_write32(device_t dev, u8 index, u32 val)
+{
+ /* The SATA PHY control registers are accessed by a funny index/value
+ * scheme. Each byte (0,1,2,3) has its own 4-bit index */
+ index = (index >> 2) & 0xf;
+ u16 i16 = index | (index<<4) | (index<<8)| (index<<12);
+ /* The index */
+ pci_write_config16(dev, 0x68, i16);
+ /* The value */
+ pci_write_config32(dev, 0x64, val);
+}
+
+static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg)
+{
+ size_t i;
+ u32* data = (u32*)cfg;
+ for(i = 0; i < (sizeof(sata_phy_config) ) >> 2; i++) {
+ data[i] = sata_phy_read32(dev, i<<2);
+ }
+}
+
+static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg)
+{
+ size_t i;
+ u32* data = (u32*)cfg;
+ for(i = 0; i < (sizeof(sata_phy_config) ) >> 2; i++) {
+ sata_phy_write32(dev, i<<2, data[i]);
+ }
+}
+
+static void vx900_sata_dump_phy_config(sata_phy_config cfg)
+{
+ print_debug("SATA PHY config:\n");
+ int i;
+ for (i = 0; i < sizeof(sata_phy_config); i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = cfg[i];
+ if((i & 7) == 0) print_debug(" |");
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\n");
+ }
+ }
+}
+
+/**
+ * \brief VX900: Place the onboard SATA controller in Native IDE mode
+ *
+ * AHCI mode requires a sub-class of 0x06, and Interface of 0x0
+ * SATA mode requires a sub-class of 0x06, and Interface of 0x00
+ * Unfortunately, setting the class to SATA, will prevent us from modyfing the
+ * interface register to an AHCI/SATA compliant value. Thus, payloads or OS may
+ * not properly identify this as a SATA controller.
+ * We could set the class code to 0x04, which would cause the interface register
+ * to become 0x00, which represents a RAID controller. Unfortunately, when we do
+ * this, SeaBIOS will skip this as a storage device, and we will not be able to
+ * boot.
+ * Our only option is to operate in IDE mode. We choose native IDE so that we
+ * can freely assign an IRQ, and are not forced to use IRQ14
+ */
+static void vx900_native_ide_mode(device_t dev)
+{
+ /* Disable subclass write protect */
+ pci_mod_config8(dev, 0x45, 1<<7, 0);
+ /* Change the device class to IDE */
+ pci_write_config16(dev, PCI_CLASS_DEVICE, PCI_CLASS_STORAGE_IDE);
+ /* Re-enable subclass write protect */
+ pci_mod_config8(dev, 0x45, 0, 1<<7);
+ /* Put it in native IDE mode */
+ pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);
+}
+
+static void vx900_sata_init(device_t dev)
+{
+ /* Enable SATA primary channel IO access */
+ pci_mod_config8(dev, 0x40, 0, 1<<1);
+ /* Just SATA, so it makes sense to be in native SATA mode */
+ vx900_native_ide_mode(dev);
+
+ /* TP Layer Idle at least 20us before the Following Command */
+ pci_mod_config8(dev, 0x53, 0, 1<<7);
+ /* Resend COMRESET When Recovering SATA Gen2 Device Error */
+ pci_mod_config8(dev, 0x62, 1<<1, 1<<7);
+
+ /* Fix "PMP Device Can’t Detect HDD Normally" (VIA Porting Guide)
+ * SATA device detection will not work unless we clear these bits.
+ * Without doing this, SeaBIOS (and potentially other payloads) will
+ * timeout when detecting SATA devices */
+ pci_mod_config8(dev, 0x89, (1<<3) | (1<<6), 0);
+
+ /* 12.7 Two Software Resets May Affect the System
+ * When the software does the second reset before the first reset
+ * finishes, it may cause the system hang. It would do one software
+ * reset and check the BSY bit of one port only, and the BSY bit of
+ * other port would be 1, then it does another software reset
+ * immediately and causes the system hang.
+ * This is because the first software reset doesn’t finish, and the
+ * state machine of the host controller conflicts, it can’t finish the
+ * second one anymore. The BSY bit of slave port would be always 1 after
+ * the second software reset issues. BIOS should set the following
+ * bit to avoid this issue. */
+ pci_mod_config8(dev, 0x80, 0, 1<<6);
+
+ /* We need to set the EPHY values before doing anything with the link */
+ sata_phy_config ephy;
+ vx900_sata_read_phy_config(dev, ephy);
+ if(1) {
+ vx900_sata_dump_phy_config(ephy);
+ vx900_sata_write_phy_config(dev, reference_ephy);
+ } else {
+ /* Enable TX and RX driving resistance */
+ /* TX - 50 Ohm */
+ ephy[1] &= ~(0x1f<<3);
+ ephy[1] |= (1<<7) | (8<<3);
+ /* RX - 50 Ohm */
+ ephy[2] &= ~(0x1f<<3);
+ ephy[2] |= (1<<7) | (8<<3);
+ vx900_sata_write_phy_config(dev, ephy);
+ }
+
+ vx900_sata_read_phy_config(dev, ephy);
+ vx900_sata_dump_phy_config(ephy);
+
+ /* Clear error flags */
+ pci_write_config32(dev, 0xa8, 0xffffffff);
+ pci_write_config32(dev, 0xac, 0xffffffff);
+
+ /* Start OOB link negotiation sequence */
+ pci_mod_config8(dev, 0xb9, 0, 3<<4);
+
+ /* FIXME: From now on, we are just doing DEBUG stuff
+ * Wait until PHY communication is enabled */
+ u32 wloops = 0;
+ while(! (pci_read_config8(dev, 0xa0) & (1<<1)) ) wloops ++;
+ printk(BIOS_SPEW, "wloops: %u\n", wloops);
+
+ vx900_dbg_sata_errors(dev);
+}
+
+static void vx900_sata_read_resources(device_t dev)
+{
+ pci_dev_read_resources(dev);
+}
+
+static struct device_operations vga_operations = {
+ .read_resources = vx900_sata_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vx900_sata_init,
+};
+
+static const struct pci_driver chrome9hd_driver __pci_driver = {
+ .ops = &vga_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_SATA,
+};
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
new file mode 100644
index 0000000..daed241
--- /dev/null
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -0,0 +1,156 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <drivers/generic/ioapic/chip.h>
+
+#include "vx900.h"
+#include "chip.h"
+
+/**
+ * \brief VX900: Set up the north module IOAPIC (for PCIE and VGA)
+ *
+ * Enable the IOAPIC in the south module, and properly set it up.
+ * \n
+ * This is the hardware specific initialization for the IOAPIC, and complements
+ * the setup done by the generic IOAPIC driver. In order for the IOAPIC to work
+ * properly, it _must_ be declared in devicetree.cb .
+ * \n
+ * We are assuming this is called before the drivers/generic/ioapic code,
+ * which should be the case if devicetree.cb is set up properly.
+ */
+static void vx900_north_ioapic_setup(device_t dev)
+{
+ u8 base_val;
+ device_t ioapic;
+ ioapic_config_t *config;
+ /* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb
+ * If it's not, then the generic ioapic driver will not set it up
+ * correctly, and the MP table will not be correctly generated */
+ for(ioapic = dev->next; ioapic; ioapic = ioapic->next)
+ {
+ if(ioapic->path.type == DEVICE_PATH_IOAPIC)
+ break;
+ }
+ /* You did put an IOAPIC in devicetree.cb, didn't you? */
+ if(ioapic == 0) {
+ /* We don't have enough info to set up the IOAPIC */
+ printk(BIOS_ERR, "ERROR: North module IOAPIC not found. "
+ "Check your devicetree.cb\n");
+ return;
+ }
+ /* Found our IOAPIC, and it should not carry ISA interrupts */
+ config = (ioapic_config_t*)ioapic->chip_info;
+ if(config->have_isa_interrupts) {
+ /* Umh, is this the right IOAPIC ? */
+ printk(BIOS_ERR, "ERROR: North module IOAPIC should not carry "
+ "ISA interrupts.\n"
+ "Check your devicetree.cb\n");
+ printk(BIOS_ERR, "Will not initialize this IOAPIC.\n");
+ return;
+ }
+ /* The base address of this IOAPIC _must_
+ * be between 0xfec00000 and 0xfecfff00
+ * be 256-byte aligned
+ */
+ if( (config->base < 0xfec0000 || config->base > 0xfecfff00)
+ || (( config->base & 0xff ) != 0) )
+ {
+ printk(BIOS_ERR, "ERROR: North module IOAPIC base should be "
+ "between 0xfec00000 and 0xfecfff00\n"
+ "and must be aligned to a 256-byte boundary, "
+ "but we found it at 0x%.8x\n", config->base);
+ return;
+ }
+
+ printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC "
+ "at 0%.8x\n", config->base);
+
+ /* First register of the IOAPIC base */
+ base_val = (config->base >> 8) & 0xff;
+ pci_write_config8(dev, 0x41, base_val);
+ /* Second register of the base.
+ * Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */
+ base_val = (config->base >> 16) & 0xf;
+ pci_mod_config8(dev, 0x40, 0, base_val | (1<<7) | (1<<5) );
+}
+
+/*
+ * Configures the PCI-express ports
+ *
+ * FIXME: implement this
+ */
+static void vx900_pex_link_setup(device_t dev)
+{
+ u8 reg8;
+ struct northbridge_via_vx900_config *nb = (void*)dev->chip_info;
+
+ print_debug("======================================================\n");
+ print_debug("== PEX link setup\n");
+ print_debug("======================================================\n");
+
+ /* FIXME: We print this before modifying the default values */
+ /* Check the default boot config */
+ reg8 = pci_read_config8(dev, 0xb0);
+ if (reg8 && (1 << 7) )
+ print_debug("PCIE lanes 3:0 used as DP interface\n");
+ else
+ print_debug("PCIE lanes 3:0 used for Root Port 0\n");
+
+ if (reg8 && (1 << 3))
+ print_debug("Root Port 0 is 1 lane wide\n");
+ else
+ print_debug("Root Port 0 is 2 lanes wide\n");
+
+ reg8 &= ~( (1 << 7) | (1 << 3));
+
+ if (nb->assign_pex_to_dp)
+ reg8 |= (1 << 7);
+
+ if (!nb->pcie_port1_2_lane_wide)
+ reg8 |= (1 << 3);
+
+ pci_write_config8(dev, 0xb0, reg8);
+}
+
+static void vx900_traf_ctr_init(device_t dev)
+{
+ vx900_north_ioapic_setup(dev);
+ vx900_pex_link_setup(dev);
+}
+
+
+static struct device_operations traf_ctrl_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vx900_traf_ctr_init,
+ /* Need this here, or the IOAPIC driver won't be called */
+ .scan_bus = scan_static_bus,
+};
+
+static const struct pci_driver traf_ctrl_driver __pci_driver = {
+ .ops = &traf_ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_TRAF,
+};
\ No newline at end of file
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