[coreboot-gerrit] Patch set updated for coreboot: 92acfff My current X201 tree as-is. Works on Lenovo Thinkpad X201

Vladimir Serbinenko (phcoder@gmail.com) gerrit at coreboot.org
Thu Jun 6 16:20:06 CEST 2013


Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3355

-gerrit

commit 92acfff2843c30376e71175c7bde92cce257e237
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Tue Jun 4 04:08:45 2013 +0200

    My current X201 tree as-is. Works on Lenovo Thinkpad X201
    
    Change-Id: Iea3865d21f4651f0c50cdee5b5cb99f1bf65946d
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/arch/x86/boot/smbios.c                         |    4 +-
 src/console/usbdebug_console.c                     |    8 +-
 src/cpu/intel/Kconfig                              |    1 +
 src/cpu/intel/Makefile.inc                         |    1 +
 src/cpu/intel/model_2065x/Kconfig                  |   42 +
 src/cpu/intel/model_2065x/Makefile.inc             |   16 +
 src/cpu/intel/model_2065x/acpi.c                   |  361 ++
 src/cpu/intel/model_2065x/cache_as_ram.inc         |  347 ++
 src/cpu/intel/model_2065x/chip.h                   |   37 +
 src/cpu/intel/model_2065x/finalize.c               |   73 +
 .../model_2065x/microcode-m9220655_00000003.h      |  129 +
 src/cpu/intel/model_2065x/microcode_blob.c         |   22 +
 src/cpu/intel/model_2065x/microcode_blob.h         |   26 +
 src/cpu/intel/model_2065x/model_2065x.h            |  109 +
 src/cpu/intel/model_2065x/model_2065x_init.c       |  483 ++
 src/cpu/intel/model_206ax/bootblock.c              |    5 +-
 src/cpu/x86/lapic/lapic_cpu_init.c                 |    2 +-
 src/cpu/x86/smm/smmhandler_tseg.S                  |    3 +
 src/cpu/x86/smm/smmrelocate.S                      |    5 +-
 src/device/device.c                                |   29 +-
 src/ec/acpi/Makefile.inc                           |    1 +
 src/ec/acpi/ec.c                                   |   13 +
 src/ec/lenovo/h8/acpi/ec.asl                       |  210 +-
 src/ec/lenovo/h8/acpi/thermal.asl                  |   11 +
 src/ec/lenovo/h8/h8.c                              |   45 +-
 src/include/delay.h                                |    1 +
 src/include/usbdebug.h                             |    1 +
 src/lib/usbdebug.c                                 |   22 +
 src/mainboard/lenovo/Kconfig                       |    6 +
 src/mainboard/lenovo/x201/Kconfig                  |   59 +
 src/mainboard/lenovo/x201/Makefile.inc             |   23 +
 src/mainboard/lenovo/x201/acpi/dock.asl            |   82 +
 src/mainboard/lenovo/x201/acpi/ec.asl              |   26 +
 src/mainboard/lenovo/x201/acpi/gpe.asl             |   30 +
 src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl   |   46 +
 src/mainboard/lenovo/x201/acpi/mainboard.asl       |    0
 src/mainboard/lenovo/x201/acpi/platform.asl        |  170 +
 .../lenovo/x201/acpi/sandybridge_pci_irqs.asl      |   87 +
 src/mainboard/lenovo/x201/acpi/superio.asl         |    0
 src/mainboard/lenovo/x201/acpi/video.asl           |   69 +
 src/mainboard/lenovo/x201/acpi_tables.c            |  275 +
 src/mainboard/lenovo/x201/cmos.layout              |  139 +
 src/mainboard/lenovo/x201/devicetree.cb            |  148 +
 src/mainboard/lenovo/x201/dock.c                   |   61 +
 src/mainboard/lenovo/x201/dock.h                   |   28 +
 src/mainboard/lenovo/x201/dsdt.asl                 |   94 +
 src/mainboard/lenovo/x201/fadt.c                   |  159 +
 src/mainboard/lenovo/x201/irq_tables.c             |   62 +
 src/mainboard/lenovo/x201/mainboard.c              |  297 ++
 src/mainboard/lenovo/x201/mptable.c                |   61 +
 src/mainboard/lenovo/x201/romstage.c               |  985 ++++
 src/mainboard/lenovo/x201/smi.h                    |   27 +
 src/mainboard/lenovo/x201/smihandler.c             |  207 +
 src/northbridge/intel/Kconfig                      |    1 +
 src/northbridge/intel/Makefile.inc                 |    1 +
 src/northbridge/intel/calpella/Kconfig             |   83 +
 src/northbridge/intel/calpella/Makefile.inc        |   34 +
 src/northbridge/intel/calpella/acpi.c              |  198 +
 src/northbridge/intel/calpella/acpi/calpella.asl   |   59 +
 src/northbridge/intel/calpella/acpi/hostbridge.asl |  350 ++
 src/northbridge/intel/calpella/acpi/igd.asl        |  338 ++
 src/northbridge/intel/calpella/calpella.h          |  626 +++
 src/northbridge/intel/calpella/chip.h              |   42 +
 src/northbridge/intel/calpella/early_init.c        |  178 +
 src/northbridge/intel/calpella/fake_vbios.c        | 1797 +++++++
 src/northbridge/intel/calpella/finalize.c          |   57 +
 src/northbridge/intel/calpella/gma.c               | 1049 ++++
 src/northbridge/intel/calpella/gma.h               |  168 +
 src/northbridge/intel/calpella/northbridge.c       |  446 ++
 src/northbridge/intel/calpella/pcie_config.c       |   89 +
 src/northbridge/intel/calpella/raminit.c           | 5502 ++++++++++++++++++++
 src/northbridge/intel/calpella/raminit.h           |   29 +
 src/northbridge/intel/calpella/raminit_fake.c      | 1413 +++++
 src/northbridge/intel/calpella/raminit_tables.c    | 1240 +++++
 src/northbridge/intel/calpella/udelay.c            |   55 +
 src/southbridge/intel/Kconfig                      |    1 +
 src/southbridge/intel/Makefile.inc                 |    1 +
 src/southbridge/intel/bd82x6x/Kconfig              |    5 +-
 src/southbridge/intel/bd82x6x/Makefile.inc         |    1 +
 src/southbridge/intel/bd82x6x/azalia.c             |    2 +-
 src/southbridge/intel/bd82x6x/early_smbus.c        |   15 +
 src/southbridge/intel/bd82x6x/finalize.c           |    5 +
 src/southbridge/intel/bd82x6x/lpc.c                |  360 +-
 src/southbridge/intel/bd82x6x/me.c                 |   17 +-
 src/southbridge/intel/bd82x6x/me.h                 |    1 +
 src/southbridge/intel/bd82x6x/me_8.x.c             |    7 +-
 src/southbridge/intel/bd82x6x/pch.h                |    9 +-
 src/southbridge/intel/bd82x6x/smbus.c              |    2 +-
 src/southbridge/intel/bd82x6x/smbus.h              |  144 +
 src/southbridge/intel/bd82x6x/smi.c                |    4 +
 src/southbridge/intel/bd82x6x/smihandler.c         |    9 +-
 src/southbridge/intel/bd82x6x/spi.c                |    8 +-
 src/southbridge/intel/calpella/Kconfig             |   72 +
 src/southbridge/intel/calpella/Makefile.inc        |   77 +
 src/southbridge/intel/calpella/sata.c              |  295 ++
 src/southbridge/intel/calpella/thermal.c           |   84 +
 src/southbridge/intel/calpella/usb_debug.c         |   58 +
 src/southbridge/intel/calpella/usb_ehci.c          |  135 +
 98 files changed, 20160 insertions(+), 55 deletions(-)

diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 308336a..34aa175 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -133,9 +133,9 @@ static int smbios_write_type0(unsigned long *current, int handle)
 	t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
 
 	if (strlen(CONFIG_LOCALVERSION))
-		t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+		t->bios_version = smbios_add_string(t->eos, "CBET4000 " CONFIG_LOCALVERSION);
 	else
-		t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+		t->bios_version = smbios_add_string(t->eos, "CBET4000 " COREBOOT_VERSION);
 #else
 #define SPACES \
 	"                                                                  "
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 58a62b8..38719f2 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -50,12 +50,15 @@ unsigned get_ehci_debug(void)
 
 static void dbgp_init(void)
 {
+	enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+
 	usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info);
 }
 
 static void dbgp_tx_byte(unsigned char data)
 {
-	usbdebug_tx_byte(&dbg_info, data);
+	if (dbg_info.ehci_debug)
+	  usbdebug_tx_byte(&dbg_info, data);
 }
 
 static unsigned char dbgp_rx_byte(void)
@@ -70,7 +73,8 @@ static unsigned char dbgp_rx_byte(void)
 
 static void dbgp_tx_flush(void)
 {
-	usbdebug_tx_flush(&dbg_info);
+	if (dbg_info.ehci_debug)
+	  usbdebug_tx_flush(&dbg_info);
 }
 
 static int dbgp_tst_byte(void)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 106ce1d..2bafa49 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -10,6 +10,7 @@ source src/cpu/intel/model_6fx/Kconfig
 source src/cpu/intel/model_1067x/Kconfig
 source src/cpu/intel/model_106cx/Kconfig
 source src/cpu/intel/model_206ax/Kconfig
+source src/cpu/intel/model_2065x/Kconfig
 source src/cpu/intel/model_f0x/Kconfig
 source src/cpu/intel/model_f1x/Kconfig
 source src/cpu/intel/model_f2x/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index a173329..4116b8b 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -15,6 +15,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_CALPELLA) += model_2065x
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
new file mode 100644
index 0000000..6056e59
--- /dev/null
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -0,0 +1,42 @@
+config CPU_INTEL_MODEL_2065X
+	bool
+
+if CPU_INTEL_MODEL_2065X
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select SMP
+	select SSE
+	select SSE2
+	select UDELAY_LAPIC
+	select SMM_TSEG
+	select HAVE_INIT_TIMER
+	select CPU_MICROCODE_IN_CBFS
+	#select AP_IN_SIPI_WAIT
+	select TSC_SYNC_MFENCE
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/model_206ax/bootblock.c"
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+	default 0x800000
+
+config ENABLE_VMX
+	bool "Enable VMX for virtualization"
+	default n
+
+config MICROCODE_INCLUDE_PATH
+	string
+	default "3rdparty/mainboard/lenovo/x201"
+
+config XIP_ROM_SIZE
+	hex
+	default 0x20000
+
+endif
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
new file mode 100644
index 0000000..963fb1b
--- /dev/null
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -0,0 +1,16 @@
+ramstage-y += model_2065x_init.c
+subdirs-y += ../../x86/name
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../intel/turbo
+subdirs-y += ../../intel/microcode
+subdirs-y += ../../x86/smm
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += microcode_blob.c
+
+cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c
new file mode 100644
index 0000000..7449aa9
--- /dev/null
+++ b/src/cpu/intel/model_2065x/acpi.c
@@ -0,0 +1,361 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "model_2065x.h"
+#include "chip.h"
+
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	result = cpuid_ext(0xb, 1);
+	cores = result.ebx & 0xff;
+
+	return cores;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0) {
+		cstates[c1].ctype = 1;
+		length += acpigen_write_CST_package_entry(&cstates[c1]);
+	}
+	if (c2 > 0) {
+		cstates[c2].ctype = 2;
+		length += acpigen_write_CST_package_entry(&cstates[c2]);
+	}
+	if (c3 > 0) {
+		cstates[c3].ctype = 3;
+		length += acpigen_write_CST_package_entry(&cstates[c3]);
+	}
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_C_state_entries(void)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+	device_t lapic;
+	struct cpu_intel_model_206ax_config *conf = NULL;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic)
+		return 0;
+	conf = lapic->chip_info;
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+static acpi_tstate_t tss_table_fine[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 94, 940, 0, 0x1f, 0 },
+	{ 88, 880, 0, 0x1e, 0 },
+	{ 82, 820, 0, 0x1d, 0 },
+	{ 75, 760, 0, 0x1c, 0 },
+	{ 69, 700, 0, 0x1b, 0 },
+	{ 63, 640, 0, 0x1a, 0 },
+	{ 57, 580, 0, 0x19, 0 },
+	{ 50, 520, 0, 0x18, 0 },
+	{ 44, 460, 0, 0x17, 0 },
+	{ 38, 400, 0, 0x16, 0 },
+	{ 32, 340, 0, 0x15, 0 },
+	{ 25, 280, 0, 0x14, 0 },
+	{ 19, 220, 0, 0x13, 0 },
+	{ 13, 160, 0, 0x12, 0 },
+};
+
+static acpi_tstate_t tss_table_coarse[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 88, 875, 0, 0x1f, 0 },
+	{ 75, 750, 0, 0x1e, 0 },
+	{ 63, 625, 0, 0x1d, 0 },
+	{ 50, 500, 0, 0x1c, 0 },
+	{ 38, 375, 0, 0x1b, 0 },
+	{ 25, 250, 0, 0x1a, 0 },
+	{ 13, 125, 0, 0x19, 0 },
+};
+
+static int generate_T_state_entries(int core, int cores_per_package)
+{
+	int len;
+
+	/* Indicate SW_ALL coordination for T-states */
+	len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+
+	/* Indicate FFixedHW so OS will use MSR */
+	len += acpigen_write_empty_PTC();
+
+	/* Set a T-state limit that can be modified in NVS */
+	len += acpigen_write_TPC("\\TLVL");
+
+	/*
+	 * CPUID.(EAX=6):EAX[5] indicates support
+	 * for extended throttle levels.
+	 */
+	if (cpuid_eax(6) & (1 << 5))
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_fine), tss_table_fine);
+	else
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
+
+	return len;
+}
+
+static int calculate_power(int tdp, int p1_ratio, int ratio)
+{
+	u32 m;
+	u32 power;
+
+	/*
+	 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
+	 *
+	 * Power = (ratio / p1_ratio) * m * tdp
+	 */
+
+	m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
+	m = (m * m) / 1000;
+
+	power = ((ratio * 100000 / p1_ratio) / 100);
+	power *= (m / 100) * (tdp / 1000);
+	power /= 1000;
+
+	return (int)power;
+}
+
+static int generate_P_state_entries(int core, int cores_per_package)
+{
+	int len, len_pss;
+	int ratio_min, ratio_max, ratio_turbo, ratio_step;
+	int coord_type, power_max, num_entries;
+	int ratio, power, clock, clock_max;
+	msr_t msr;
+
+	/* Determine P-state coordination type from MISC_PWR_MGMT[0] */
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
+		coord_type = SW_ANY;
+	else
+		coord_type = HW_ALL;
+
+	/* Get bus ratio limits and calculate clock speeds */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
+
+	/* Determine if this CPU has configurable TDP */
+	if (cpu_config_tdp_levels()) {
+		/* Set max ratio to nominal TDP ratio */
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		ratio_max = msr.lo & 0xff;
+	} else {
+		/* Max Non-Turbo Ratio */
+		ratio_max = (msr.lo >> 8) & 0xff;
+	}
+	clock_max = ratio_max * SANDYBRIDGE_BCLK + ratio_max / 3;
+
+	/* Calculate CPU TDP in mW */
+	power_max = 25000;
+
+	/* Write _PCT indicating use of FFixedHW */
+	len = acpigen_write_empty_PCT();
+
+	/* Write _PPC with no limit on supported P-state */
+	len += acpigen_write_PPC_NVS();
+
+	/* Write PSD indicating configured coordination type */
+	len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
+
+	/* Add P-state entries in _PSS table */
+	len += acpigen_write_name("_PSS");
+
+	/* Determine ratio points */
+	ratio_step = PSS_RATIO_STEP;
+	num_entries = (ratio_max - ratio_min) / ratio_step;
+	while (num_entries > PSS_MAX_ENTRIES-1) {
+		ratio_step <<= 1;
+		num_entries >>= 1;
+	}
+
+	/* P[T] is Turbo state if enabled */
+	if (get_turbo_state() == TURBO_ENABLED) {
+		/* _PSS package count including Turbo */
+		len_pss = acpigen_write_package(num_entries + 2);
+
+		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+		ratio_turbo = msr.lo & 0xff;
+
+		/* Add entry for Turbo ratio */
+		len_pss += acpigen_write_PSS_package(
+			clock_max + 1,		/*MHz*/
+			power_max,		/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio_turbo,	/*control*/
+			ratio_turbo);	/*status*/
+	} else {
+		/* _PSS package count without Turbo */
+		len_pss = acpigen_write_package(num_entries + 1);
+	}
+
+	/* First regular entry is max non-turbo ratio */
+	len_pss += acpigen_write_PSS_package(
+		clock_max,		/*MHz*/
+		power_max,		/*mW*/
+		PSS_LATENCY_TRANSITION,	/*lat1*/
+		PSS_LATENCY_BUSMASTER,	/*lat2*/
+		ratio_max,		/*control*/
+		ratio_max);	/*status*/
+
+	/* Generate the remaining entries */
+	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
+	     ratio >= ratio_min; ratio -= ratio_step) {
+
+		/* Calculate power at this ratio */
+		power = calculate_power(power_max, ratio_max, ratio);
+		clock = ratio * SANDYBRIDGE_BCLK + ratio / 3;
+
+		len_pss += acpigen_write_PSS_package(
+			clock,			/*MHz*/
+			power,			/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio,		/*control*/
+			ratio);		/*status*/
+	}
+
+	/* Fix package length */
+	len_pss--;
+	acpigen_patch_len(len_pss);
+
+	return len + len_pss;
+}
+
+void generate_cpu_entries(void)
+{
+	int len_pr;
+	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+	int totalcores = dev_count_cpu();
+	int cores_per_package = get_cores_per_package();
+	int numcpus = totalcores/cores_per_package;
+
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+	       numcpus, cores_per_package);
+
+	for (cpuID=1; cpuID <=numcpus; cpuID++) {
+		for (coreID=1; coreID<=cores_per_package; coreID++) {
+			if (coreID>1) {
+				pcontrol_blk = 0;
+				plen = 0;
+			}
+
+			/* Generate processor \_PR.CPUx */
+			len_pr = acpigen_write_processor(
+				(cpuID-1)*cores_per_package+coreID-1,
+				pcontrol_blk, plen);
+
+			/* Generate P-state tables */
+			len_pr += generate_P_state_entries(
+				cpuID-1, cores_per_package);
+
+			/* Generate C-state tables */
+			len_pr += generate_C_state_entries();
+
+			/* Generate T-state tables */
+			len_pr += generate_T_state_entries(
+				cpuID-1, cores_per_package);
+
+			len_pr--;
+			acpigen_patch_len(len_pr);
+		}
+	}
+}
+
+struct chip_operations cpu_intel_model_206ax_ops = {
+	CHIP_NAME("Intel SandyBridge/IvyBridge CPU")
+};
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
new file mode 100644
index 0000000..db0eaae
--- /dev/null
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -0,0 +1,347 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cpu/x86/stack.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
+
+#define CPU_PHYSMASK_HI  (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
+
+#define NoEvictMod_MSR 0x2e0
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
+
+cache_as_ram:
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
+
+	/* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+	movl	(%esi), %eax
+	bt	$12, %eax
+	jc	wait_for_sipi
+
+	post_code(0x21)
+	/* Zero out all fixed range and variable range MTRRs. */
+	movl	$mtrr_table, %esi
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+clear_mtrrs:
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	post_code(0x22)
+	/* Configure the default memory type to uncacheable. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	post_code(0x23)
+	/* Set Cache-as-RAM base address. */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	post_code(0x24)
+	/* Set Cache-as-RAM mask. */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx
+	wrmsr
+
+	post_code(0x25)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+        movl	%cr0, %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* enable the 'no eviction' mode */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $1, %eax
+	andl    $~2, %eax
+	wrmsr
+
+       /* Clear the cache memory region. This will also fill up the cache */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	// movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+
+	/* enable the 'no eviction run' state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $3, %eax
+	wrmsr
+
+	post_code(0x26)
+	/* Enable Cache-as-RAM mode by disabling cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
+	/*
+	 * IMPORTANT: The following calculation _must_ be done at runtime. See
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
+	movl    $copy_and_run, %eax
+	andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$CPU_PHYSMASK_HI, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	wrmsr
+
+	post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for ram init code to run faster */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx
+	wrmsr
+#endif
+
+	post_code(0x28)
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	movl	%eax, %cr0
+
+	/* Set up the stack pointer below MRC variable space. */
+	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
+		  CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4 - 4096), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+before_romstage:
+	post_code(0x29)
+	/* Call romstage.c main function. */
+	call	main
+
+	post_code(0x2f)
+
+	/* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+	cld
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	$24, %ecx
+	rep	movsb
+#endif
+
+	post_code(0x30)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	post_code(0x31)
+
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~MTRRdefTypeEn), %eax
+	wrmsr
+
+	post_code(0x31)
+
+	/* Disable the no eviction run state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	andl    $~2, %eax
+	wrmsr
+
+	invd
+
+	/* Disable the no eviction mode */
+	rdmsr
+	andl    $~1, %eax
+	wrmsr
+
+#if CONFIG_CACHE_MRC_BIN
+	/* Clear MTRR that was used to cache MRC */
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	movl	$MTRRphysBase_MSR(2), %ecx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	wrmsr
+#endif
+
+	post_code(0x33)
+
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+	movl	%eax, %cr0
+
+	post_code(0x36)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	post_code(0x38)
+
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
+	movl	$MTRRphysBase_MSR(0), %ecx
+	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(0), %ecx
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
+	wrmsr
+
+#if CONFIG_CACHE_ROM_SIZE
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$CPU_PHYSMASK_HI, %edx
+	wrmsr
+#endif
+
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+	post_code(0x3c)
+
+#if CONFIG_HAVE_ACPI_RESUME
+	movl	CBMEM_BOOT_MODE, %eax
+	cmpl	$0x2, %eax // Resume?
+	jne	__acpi_resume_backup_done
+
+	/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+	 * through stage 2. We could keep stuff like stack and heap in high
+	 * tables memory completely, but that's a wonderful clean up task for
+	 * another day.
+	 */
+	cld
+	movl	$CONFIG_RAMBASE, %esi
+	movl	CBMEM_RESUME_BACKUP, %edi
+	movl	$HIGH_MEMORY_SAVE / 4, %ecx
+	rep	movsl
+
+__acpi_resume_backup_done:
+#endif
+
+	post_code(0x3d)
+
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+
+	movl	$ROMSTAGE_STACK, %esp
+	movl	%esp, %ebp
+	call	copy_and_run
+
+.Lhlt:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.Lhlt
+
+mtrr_table:
+	.word 0x02FF
+
+	/* Fixed MTRRs */
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
+
+	/* Variable MTRRs */
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
+mtrr_table_end:
+
diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h
new file mode 100644
index 0000000..021bc84
--- /dev/null
+++ b/src/cpu/intel/model_2065x/chip.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_model_206ax_config {
+	u8 disable_acpi;	/* Do not generate CPU ACPI tables */
+
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* ACPI C1 on Battery Power */
+	int c2_battery;		/* ACPI C2 on Battery Power */
+	int c3_battery;		/* ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* ACPI C1 on AC Power */
+	int c2_acpower;		/* ACPI C2 on AC Power */
+	int c3_acpower;		/* ACPI C3 on AC Power */
+
+	int tcc_offset;		/* TCC Activation Offset */
+};
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
new file mode 100644
index 0000000..f8747a1
--- /dev/null
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include "model_2065x.h"
+
+static void msr_set_bit(unsigned reg, unsigned bit)
+{
+	msr_t msr = rdmsr(reg);
+
+	if (bit < 32) {
+		if (msr.lo & (1 << bit))
+			return;
+		msr.lo |= 1 << bit;
+	} else {
+		if (msr.hi & (1 << (bit - 32)))
+			return;
+		msr.hi |= 1 << (bit - 32);
+	}
+
+	wrmsr(reg, msr);
+}
+
+void intel_model_206ax_finalize_smm(void)
+{
+	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+
+	/* Lock AES-NI only if supported */
+	if (cpuid_ecx(1) & (1 << 25))
+		msr_set_bit(MSR_FEATURE_CONFIG, 0);
+
+#ifdef LOCK_POWER_CONTROL_REGISTERS
+	/*
+	 * Lock the power control registers.
+	 *
+	 * These registers can be left unlocked if modifying power
+	 * limits from the OS is desirable. Modifying power limits
+	 * from the OS can be especially useful for experimentation
+	 * during  early phases of system bringup while the thermal
+	 * power envelope is being proven.
+	 */
+
+	msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
+	msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
+	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
+#endif
+
+	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
+}
diff --git a/src/cpu/intel/model_2065x/microcode-m9220655_00000003.h b/src/cpu/intel/model_2065x/microcode-m9220655_00000003.h
new file mode 100644
index 0000000..2eb6cca
--- /dev/null
+++ b/src/cpu/intel/model_2065x/microcode-m9220655_00000003.h
@@ -0,0 +1,129 @@
+/*  m9220655_00000003.inc  */
+0x00000001,	0x00000003,	0x09012011,	0x00020655,
+0xc50abfd4,	0x00000001,	0x00000092,	0x000007d0,
+0x00000800,	0x00000000,	0x00000000,	0x00000000,
+0x00000000,	0x000000a1,	0x00020001,	0x00000003,
+0x00000000,	0x00000000,	0x20110831,	0x000001a1,
+0x00000001,	0x00020655,	0x00000000,	0x00000000,
+0x00000000,	0x00000000,	0x00000000,	0x00000000,
+0x00000000,	0x00000000,	0x00000000,	0x00000000,
+0x00000000,	0x00000000,	0x00000000,	0x00000000,
+0xc3323f9e,	0xa2912832,	0xa7a30a2e,	0x9e75a181,
+0x840159be,	0xd1c7dbb0,	0x921c5cf7,	0xb323111b,
+0x5d5f57b5,	0x9926d84a,	0xdaaf70e7,	0x91786b18,
+0x82da740d,	0xae90be68,	0x8b6a07cf,	0xc2c37ebc,
+0xde451f9c,	0x7a1444c0,	0xce6700b1,	0x5c29e58a,
+0x12eb603f,	0xaaf6cb53,	0xd807a1c9,	0xf51ed696,
+0x90d9e2c3,	0x641bff09,	0x732ab820,	0xfef7aa2f,
+0x8f518e1d,	0xf0d8c4d9,	0x73aefe19,	0xf6d7ae12,
+0xd50a095b,	0xdf21cbb8,	0x4b81ff9a,	0xe1a6d1f8,
+0xbe78b0de,	0xda86826f,	0xc4f9c057,	0x306f1761,
+0x7aae81f0,	0xdbab0ae2,	0x789ec0ff,	0xbaacd096,
+0x68fa4733,	0x2f3fd406,	0xd287247f,	0x79eefe4c,
+0x6f674a41,	0xd6948ad8,	0x90388682,	0x5a4bf35d,
+0xadab41ff,	0x89e9dc62,	0xb2eccfee,	0xd4d52153,
+0x34301d19,	0x8a2f38a6,	0x35b05e56,	0x482f029a,
+0x296cb5a3,	0xce64f437,	0xae1dfa06,	0xb9f29132,
+0x1960a103,	0x70bb6f46,	0x152a5d83,	0x171a19d9,
+0xac9aa4b7,	0x54b719f7,	0x5b781cb1,	0xaea548bb,
+0x00000011,	0x649668c5,	0xd3d4e73c,	0x0d7eee17,
+0xc8a4d8f1,	0xa531e67c,	0x0d4e93f9,	0x109a2c8e,
+0xb3a120eb,	0x1cb99ad0,	0xdf7fffa7,	0xcd22ae67,
+0xbe6f61df,	0x1fff8bc4,	0x7d413494,	0xbbc77986,
+0x4648fad1,	0x05a0b769,	0x14a2f426,	0x39081a28,
+0x343c7600,	0x3a9d78ed,	0xa8bcbbb1,	0x1128500a,
+0xb1f08088,	0x16f1cc2e,	0x187920e4,	0x7bd8c616,
+0x416a91ac,	0x2d156cd1,	0xd23473e7,	0xf326b7ff,
+0x991a226f,	0xf1a4f527,	0xe758dc3f,	0x20f89a4a,
+0x9f84858c,	0x9c5bde06,	0x839ea7e7,	0x42cfa525,
+0x869950f9,	0x48e6318f,	0x44314d3e,	0xc946335f,
+0x9439e0ba,	0x16bef497,	0x5dfeb355,	0x062e96dc,
+0x0c5b3442,	0x2317678c,	0x0688e8b9,	0x698df73a,
+0xd87f7a27,	0xc63a05b7,	0xb77b7ed1,	0xee993117,
+0xbffab1d3,	0x455c43b5,	0x5363cb6c,	0x9361cabc,
+0xd5bc2e2b,	0xb0079b02,	0x5b371608,	0x8228cc3c,
+0x97c217b0,	0xef92660a,	0x99e15bc3,	0x610d1881,
+0xa84efd04,	0x35f287c9,	0xc02cbf49,	0xdc291d6f,
+0x7d603a19,	0x420b25dc,	0x6d24d532,	0xf8c2d4b6,
+0x67104704,	0x7ae246b3,	0x24f07636,	0xf88808a0,
+0xcdcf7aed,	0xa78611a3,	0x9dafdde7,	0x5def0b11,
+0xb39ca9d7,	0xd0de1c2a,	0xe6e8cc61,	0x9824df50,
+0x501ef8c9,	0x5bb94ee7,	0x9d75a287,	0xc5b37ebc,
+0x8b7175f8,	0xe9bd1024,	0xc4e004c2,	0xb626e586,
+0xf71c129d,	0xe5562dd2,	0xd1d9c514,	0xaa69cd52,
+0x7ec85bfb,	0x1d6d69da,	0xbd735ff0,	0x496b0cc3,
+0xea10aa85,	0xd968b670,	0xe4674e6b,	0xd7725f8c,
+0xc845a270,	0x15d4b857,	0x0a130ca8,	0x707de71f,
+0x0cf7ba9f,	0xb46fbb4d,	0xc9631c72,	0xe0b4abcd,
+0x0b364ef1,	0xa390747a,	0x5945a462,	0xe0756457,
+0x5f79663c,	0x7418e5be,	0xc7ac38f4,	0x24aceecd,
+0xae762e2b,	0x04c63655,	0x2807f3ba,	0x8a9fdee2,
+0x4705e3b9,	0x0be41abf,	0x360a2475,	0x2188e84c,
+0x6724fa71,	0x0d80d39f,	0x06be8e55,	0xd49f817a,
+0x518f531d,	0x02775181,	0xbd1f8af9,	0x70c91b1f,
+0x67d619f2,	0x0e2f44b0,	0xde3a57b2,	0x0b96a208,
+0x86dbafdf,	0xd81a43ca,	0x894241a6,	0x453cd6c0,
+0x801398e5,	0x8dc7e734,	0x64f5f2f0,	0x023fe4ad,
+0x808b3fbe,	0x677dec2d,	0xc75aa416,	0x8d4a51c1,
+0xcb46efb4,	0x26af2486,	0xf28d384f,	0x1f74bbaa,
+0xb35dbfec,	0xa4acc70a,	0xd0c8ff4b,	0xf40e3136,
+0x24f08d6d,	0xf4a5792f,	0x3423ebc0,	0x47f54044,
+0x42939e1e,	0x3768fe97,	0x0890f228,	0xfe48104e,
+0xd095804b,	0xde7a40cb,	0xc8ed5843,	0x04cc48c5,
+0xa68d1936,	0x554d336f,	0x19cc9df7,	0xf2b5b0cc,
+0xf88858c2,	0x6bef0f07,	0xcff53326,	0xfbebbb76,
+0x63afbd06,	0x6d4b7c27,	0xdd5c8b52,	0x792f665e,
+0x44e8bc2d,	0x53522507,	0xf5971875,	0xef44f472,
+0x0ab3bc03,	0x068d792f,	0x86745dc4,	0xc0e63ca0,
+0xfddb054d,	0x46c23e3c,	0xc8184e1a,	0xb7e77cc7,
+0x59e90ac1,	0xd836bf58,	0xb220f287,	0x3c3a2e8f,
+0xa28a7e28,	0x99a249ec,	0xd2a6641c,	0x24adeb4a,
+0x2bbf323a,	0x618dee6e,	0x093e831a,	0x3f4d3194,
+0xa166732a,	0x0a80f2f3,	0x8f2f80de,	0xc4d2b7ea,
+0x17f9e541,	0x1059766d,	0xc2f7e49d,	0x666bb0a3,
+0xfe8eb21f,	0xa68c8c87,	0x30efe1af,	0x15763eab,
+0x1d18c1f0,	0xcf1907ee,	0xd478498e,	0xb8041744,
+0x1bd93f4b,	0x6bca9af1,	0xa54694db,	0xaccd6971,
+0x92af5474,	0x194c5290,	0xc573b14f,	0xe4d74f3c,
+0xaa128d24,	0xe50848a2,	0xa5001983,	0x9fc5c01f,
+0x495687cb,	0x7795998b,	0xcba451a5,	0x67c54058,
+0x3585e4cc,	0x07eaf375,	0xa1bef51d,	0x730960a4,
+0xc217f8f0,	0xe5779a63,	0x237b7f2f,	0x6d868035,
+0x70987ef1,	0x1ab1e989,	0xf1727403,	0x94cd3133,
+0xbe827fc7,	0x19e198d1,	0xf8f8a4dd,	0x0bdfc02e,
+0x788737f9,	0xf554a473,	0x22488c80,	0x4397d132,
+0x5602e73a,	0x4cbdf8b7,	0x14929ba4,	0xc49645d8,
+0x3a724eb1,	0x44134eef,	0x534f26fc,	0x2c9a2bcf,
+0xc329abc2,	0x79a52a91,	0xc4d8ecb2,	0x4f29e89b,
+0x08e3bc45,	0x02c7516b,	0xe4f79884,	0x21dc828a,
+0xb22adc25,	0xad6b4194,	0xc2e88ec8,	0xab76a868,
+0x3049d043,	0x9781e3b5,	0xa56602b8,	0xb844a1cf,
+0xd0c2f155,	0xfff59242,	0x7c0b1be7,	0x20c337ee,
+0x6eeedede,	0x3d544527,	0x4fa08565,	0x78035c9f,
+0x5ab9652f,	0x1679da28,	0x1d59380f,	0xfd693582,
+0x6647c152,	0xa494f5b7,	0x1e5a44e5,	0x49515666,
+0x80ad6e9f,	0x2857b798,	0x21c78a9c,	0xde2536d4,
+0x8cd0c906,	0x0e101e47,	0xb56139d8,	0x5f29407b,
+0xd86efa56,	0x60c1f662,	0x387dbee9,	0xd57f4fae,
+0xe27b9e73,	0x5e4d81b9,	0x2761f882,	0x923b00c9,
+0xf1d1ee2e,	0xbec5a579,	0xa90ebc17,	0x686554a2,
+0xa83f71fd,	0x8eb862bc,	0xdfd0bb6f,	0x1ac1a2bb,
+0x74d53b49,	0xda9430c4,	0x09797597,	0x35d8f250,
+0x8d33fb7b,	0x21ec9ecd,	0x6bd9041c,	0xf858aae6,
+0x3bb472b5,	0xf43a3d7e,	0x8ced914f,	0x5f5d9ce5,
+0xc0e27757,	0x6afee8ff,	0x45bd08fc,	0x74402451,
+0x5d1e3aff,	0xfe1e6e53,	0xcaf73401,	0x035d5585,
+0xb77a8af9,	0xc869836f,	0x72e43074,	0xf784f07b,
+0x17cf17fd,	0x5785c5c9,	0xa761ee5e,	0xaede1773,
+0xc58bab5a,	0x8fb77743,	0xc20c974e,	0x9f72ce11,
+0xdfdf11f8,	0x0153fda9,	0x87d08d4d,	0x8a8d163c,
+0x2f346fc4,	0x4aabbd39,	0x9866fbe8,	0x4fbc185a,
+0xc30ea07b,	0xc6e2c2e2,	0x6d9bcc5b,	0x292524ac,
+0xaad044e9,	0xd6fcd72b,	0x755b2c1b,	0xbc5f83ee,
+0xbb041dfd,	0x87eefef9,	0x68cdbb47,	0xf423fd81,
+0x1c106165,	0x35b223a3,	0x4212e6b7,	0x0868b1b0,
+0x5288c578,	0x108d97ff,	0x1962e7b9,	0x73d366ec,
+0x8c851ca9,	0x1705746d,	0xc1a261ae,	0xd685b108,
+0x42a77adc,	0x2c454ffe,	0x33b19c19,	0xefae69ca,
+0xa6ae093b,	0x6fdfb131,	0xb6fbe5d9,	0xe872ca64,
+0xecd6df71,	0xe133acfc,	0x3d16c48b,	0x240a15a8,
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
new file mode 100644
index 0000000..c2538e8
--- /dev/null
+++ b/src/cpu/intel/model_2065x/microcode_blob.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+unsigned microcode[] = {
+#include "microcode_blob.h"
+};
diff --git a/src/cpu/intel/model_2065x/microcode_blob.h b/src/cpu/intel/model_2065x/microcode_blob.h
new file mode 100644
index 0000000..1da40d9
--- /dev/null
+++ b/src/cpu/intel/model_2065x/microcode_blob.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+	#include "microcode-m9220655_00000003.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
new file mode 100644
index 0000000..d5fd5cb
--- /dev/null
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_INTEL_MODEL_206AX_H
+#define _CPU_INTEL_MODEL_206AX_H
+
+/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
+#define SANDYBRIDGE_BCLK		133
+
+#define IA32_FEATURE_CONTROL		0x3a
+#define  CPUID_VMX			(1 << 5)
+#define  CPUID_SMX			(1 << 6)
+#define MSR_FEATURE_CONFIG		0x13c
+#define MSR_FLEX_RATIO			0x194
+#define  FLEX_RATIO_LOCK		(1 << 20)
+#define  FLEX_RATIO_EN			(1 << 16)
+#define IA32_PLATFORM_DCA_CAP		0x1f8
+#define IA32_MISC_ENABLE		0x1a0
+#define MSR_TEMPERATURE_TARGET		0x1a2
+#define IA32_PERF_CTL 			0x199
+#define IA32_THERM_INTERRUPT		0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+#define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
+#define MSR_LT_LOCK_MEMORY		0x2e7
+#define IA32_MC0_STATUS 		0x401
+
+#define MSR_PIC_MSG_CONTROL		0x2e
+#define MSR_PLATFORM_INFO		0xce
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
+#define MSR_TURBO_RATIO_LIMIT		0x1ad
+#define MSR_POWER_CTL			0x1fc
+
+#define MSR_PKGC3_IRTL			0x60a
+#define MSR_PKGC6_IRTL			0x60b
+#define MSR_PKGC7_IRTL			0x60c
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
+/* long duration in low dword, short duration in high dword */
+#define MSR_PKG_POWER_LIMIT		0x610
+#define  PKG_POWER_LIMIT_MASK		0x7fff
+#define  PKG_POWER_LIMIT_EN		(1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT	17
+#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+
+#define MSR_PP0_CURRENT_CONFIG		0x601
+#define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG		0x602
+#define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
+#define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
+#define MSR_PKG_POWER_SKU_UNIT		0x606
+#define MSR_PKG_POWER_SKU		0x614
+#define MSR_PP0_POWER_LIMIT		0x638
+#define MSR_PP1_POWER_LIMIT		0x640
+
+#define IVB_CONFIG_TDP_MIN_CPUID	0x306a2
+#define MSR_CONFIG_TDP_NOMINAL		0x648
+#define MSR_CONFIG_TDP_LEVEL1		0x649
+#define MSR_CONFIG_TDP_LEVEL2		0x64a
+#define MSR_CONFIG_TDP_CONTROL		0x64b
+#define MSR_TURBO_ACTIVATION_RATIO	0x64c
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES			16
+#define PSS_RATIO_STEP			1
+#define PSS_LATENCY_TRANSITION		10
+#define PSS_LATENCY_BUSMASTER		10
+
+#ifdef __SMM__
+/* Lock MSRs */
+void intel_model_206ax_finalize_smm(void);
+#else
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+int cpu_config_tdp_levels(void);
+#endif
+
+#endif
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
new file mode 100644
index 0000000..a7794bc
--- /dev/null
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -0,0 +1,483 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/name.h>
+#include <pc80/mc146818rtc.h>
+#include <usbdebug.h>
+#include "model_2065x.h"
+#include "chip.h"
+
+/*
+ * List of suported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* MWAIT State 0 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C3 */
+		.latency = 63,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 4: C6 */
+		.latency = 87,
+		.power = 350,
+		.resource = {
+			.addrl = 0x20,	/* MWAIT State 2 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 5: C7 */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 6: C7S */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{ 0 }
+};
+
+static void enable_vmx(void)
+{
+	struct cpuid_result regs;
+	msr_t msr;
+	int enable = CONFIG_ENABLE_VMX;
+
+	regs = cpuid(1);
+	/* Check that the VMX is supported before reading or writing the MSR. */
+	if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
+		return;
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__);
+		/* VMX locked. If we set it again we get an illegal
+		 * instruction
+		 */
+		return;
+	}
+
+	/* The IA32_FEATURE_CONTROL MSR may initialize with random values.
+	 * It must be cleared regardless of VMX config setting.
+	 */
+	msr.hi = msr.lo = 0;
+
+	printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling");
+
+	/* Even though the Intel manual says you must set the lock bit in addition
+	 * to the VMX bit in order for VMX to work, it is incorrect.  Thus we leave
+	 * it unlocked for the OS to manage things itself.  This is good for a few
+	 * reasons:
+	 * - No need to reflash the bios just to toggle the lock bit.
+	 * - The VMX bits really really should match each other across cores, so
+	 *   hard locking it on one while another has the opposite setting can
+	 *   easily lead to crashes as code using VMX migrates between them.
+	 * - Vendors that want to "upsell" from a bios that disables+locks to
+	 *   one that doesn't is sleazy.
+	 * By leaving this to the OS (e.g. Linux), people can do exactly what they
+	 * want on the fly, and do it correctly (e.g. across multiple cores).
+	 */
+	if (enable) {
+		msr.lo |= (1 << 2);
+		if (regs.ecx & CPUID_SMX)
+			msr.lo |= (1 << 1);
+	}
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+	[0]   = 0x00,
+	[1]   = 0x0a,
+	[2]   = 0x0b,
+	[3]   = 0x4b,
+	[4]   = 0x0c,
+	[5]   = 0x2c,
+	[6]   = 0x4c,
+	[7]   = 0x6c,
+	[8]   = 0x0d,
+	[10]  = 0x2d,
+	[12]  = 0x4d,
+	[14]  = 0x6d,
+	[16]  = 0x0e,
+	[20]  = 0x2e,
+	[24]  = 0x4e,
+	[28]  = 0x6e,
+	[32]  = 0x0f,
+	[40]  = 0x2f,
+	[48]  = 0x4f,
+	[56]  = 0x6f,
+	[64]  = 0x10,
+	[80]  = 0x30,
+	[96]  = 0x50,
+	[112] = 0x70,
+	[128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+	[0x00] = 0,
+	[0x0a] = 1,
+	[0x0b] = 2,
+	[0x4b] = 3,
+	[0x0c] = 4,
+	[0x2c] = 5,
+	[0x4c] = 6,
+	[0x6c] = 7,
+	[0x0d] = 8,
+	[0x2d] = 10,
+	[0x4d] = 12,
+	[0x6d] = 14,
+	[0x0e] = 16,
+	[0x2e] = 20,
+	[0x4e] = 24,
+	[0x6e] = 28,
+	[0x0f] = 32,
+	[0x2f] = 40,
+	[0x4f] = 48,
+	[0x6f] = 56,
+	[0x10] = 64,
+	[0x30] = 80,
+	[0x50] = 96,
+	[0x70] = 112,
+	[0x11] = 128,
+};
+
+int cpu_config_tdp_levels(void)
+{
+	msr_t platform_info;
+
+	/* Minimum CPU revision */
+	if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
+		return 0;
+
+	/* Bits 34:33 indicate how many levels supported */
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return (platform_info.hi >> 1) & 3;
+}
+
+
+static void configure_thermal_target(void)
+{
+	struct cpu_intel_model_206ax_config *conf;
+	device_t lapic;
+	msr_t msr;
+
+	/* Find pointer to CPU configuration */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic || !lapic->chip_info)
+		return;
+	conf = lapic->chip_info;
+
+	/* Set TCC activaiton offset if supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
+	}
+}
+
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+#ifdef DISABLED
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+#endif
+}
+
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+
+static void set_max_ratio(void)
+{
+	msr_t msr, perf_ctl;
+
+	perf_ctl.hi = 0;
+
+	/* Check for configurable TDP option */
+	if (cpu_config_tdp_levels()) {
+		/* Set to nominal TDP ratio */
+		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info bits 15:8 give max ratio */
+		msr = rdmsr(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+	wrmsr(IA32_PERF_CTL, perf_ctl);
+
+	printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
+	       ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+#ifdef DISABLED
+	msr_t msr;
+
+	/* Energy Policy is bits 3:0 */
+	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
+	       policy);
+#endif
+}
+
+static void configure_mca(void)
+{
+	msr_t msr;
+	int i;
+
+	msr.lo = msr.hi = 0;
+	/* This should only be done on a cold boot */
+	for (i = 0; i < 7; i++)
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static void intel_cores_init(device_t cpu)
+{
+	struct cpuid_result result;
+	unsigned threads_per_package, threads_per_core, i;
+
+	/* Logical processors (threads) per core */
+	result = cpuid_ext(0xb, 0);
+	threads_per_core = result.ebx & 0xffff;
+
+	/* Logical processors (threads) per package */
+	result = cpuid_ext(0xb, 1);
+	threads_per_package = result.ebx & 0xffff;
+
+	/* Only initialize extra cores from BSP */
+	if (cpu->path.apic.apic_id)
+		return;
+
+	printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n",
+	       cpu->path.apic.apic_id, threads_per_package/threads_per_core,
+	       threads_per_core);
+
+	for (i = 1; i < threads_per_package; ++i) {
+		struct device_path cpu_path;
+		device_t new;
+
+		/* Build the cpu device path */
+		cpu_path.type = DEVICE_PATH_APIC;
+		cpu_path.apic.apic_id =
+		  cpu->path.apic.apic_id + (i & 1) + ((i & 2) << 1);
+
+		/* Update APIC ID if no hyperthreading */
+		if (threads_per_core == 1)
+			cpu_path.apic.apic_id <<= 1;
+
+		/* Allocate the new cpu device structure */
+		new = alloc_dev(cpu->bus, &cpu_path);
+		if (!new)
+			continue;
+
+		printk(BIOS_DEBUG, "CPU: %u has core %u\n",
+		       cpu->path.apic.apic_id,
+		       new->path.apic.apic_id);
+
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+		/* Start the new cpu */
+		if (!start_cpu(new)) {
+			/* Record the error in cpu? */
+			printk(BIOS_ERR, "CPU %u would not start!\n",
+			       new->path.apic.apic_id);
+		}
+#endif
+	}
+}
+
+static void model_2065x_init(device_t cpu)
+{
+	char processor_name[49];
+	struct cpuid_result cpuid_regs;
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	intel_update_microcode_from_cbfs();
+
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+	printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ());
+#if CONFIG_USBDEBUG
+	// Is this caution really needed?
+	if(!ehci_debug_addr)
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs based on physical address size */
+	cpuid_regs = cpuid(0x80000008);
+	x86_setup_fixed_mtrrs();
+	x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+	x86_mtrr_check();
+
+	/* Setup Page Attribute Tables (PAT) */
+	// TODO set up PAT
+
+#if CONFIG_USBDEBUG
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+	setup_lapic();
+
+	/* Enable virtualization if enabled in CMOS */
+	enable_vmx();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Thermal throttle activation offset */
+	configure_thermal_target();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Set Max Ratio */
+	set_max_ratio();
+
+	/* Enable Turbo */
+	enable_turbo();
+
+	/* Start up extra cores */
+	intel_cores_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_2065x_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x20655 }, /* Intel Calpella */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+	.cstates  = cstate_map,
+};
+
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index d3579f7..f9c774c 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -25,11 +25,14 @@
 #include <arch/io.h>
 
 #include <cpu/intel/microcode/microcode.c>
-#include "model_206ax.h"
 
 #if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
 /* Needed for RCBA access to set Soft Reset Data register */
 #include <southbridge/intel/bd82x6x/pch.h>
+#include "model_206ax.h"
+#elif CONFIG_SOUTHBRIDGE_INTEL_CALPELLA
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "../model_2065x/model_2065x.h"
 #else
 #error "CPU must be paired with Intel BD82X6X or C216 southbridge"
 #endif
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index fbc8aa4..7f18c7c 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -141,7 +141,7 @@ static int lapic_start_cpu(unsigned long apicid)
 		}
 		return 0;
 	}
-#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX
+#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX && !CONFIG_CPU_INTEL_MODEL_2065X
 	mdelay(10);
 #endif
 
diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S
index eb5d63c..7db9701 100644
--- a/src/cpu/x86/smm/smmhandler_tseg.S
+++ b/src/cpu/x86/smm/smmhandler_tseg.S
@@ -60,6 +60,9 @@
 #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#elif CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#include <northbridge/intel/calpella/calpella.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
 #elif CONFIG_NORTHBRIDGE_INTEL_HASWELL
 #include <northbridge/intel/haswell/haswell.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 16d4b9f..ba40369 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -35,7 +35,7 @@
 #include "../../../southbridge/intel/i82801dx/i82801dx.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_SCH
 #include "../../../southbridge/intel/sch/sch.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
+#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 || CONFIG_SOUTHBRIDGE_INTEL_CALPELLA
 #include "../../../southbridge/intel/bd82x6x/pch.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
 #include "../../../southbridge/intel/i82801ix/i82801ix.h"
@@ -48,6 +48,9 @@
 #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#elif CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#include <northbridge/intel/calpella/calpella.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
 #else
 #error "Northbridge must define TSEG_BAR."
 #endif
diff --git a/src/device/device.c b/src/device/device.c
index a971270..e0325d3 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -529,6 +529,12 @@ static void allocate_resources(struct bus *bus, struct resource *bridge,
 		       resource->base, (resource->flags & IORESOURCE_IO)
 		       ? "io" : (resource->flags & IORESOURCE_PREFETCH)
 		       ? "prefmem" : "mem");
+		if (resource->base == 0xe0000000
+		    && 	PCI_SLOT(dev->path.pci.devfn) == 0x2)
+		  {
+		    printk (BIOS_ERR, "moving to 0xd0000000\n");
+		    resource->base = 0xd0000000;
+		  }
 	}
 
 	/*
@@ -586,19 +592,14 @@ static void allocate_resources(struct bus *bus, struct resource *bridge,
 	}
 }
 
-#if CONFIG_PCI_64BIT_PREF_MEM
-#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
-#else
 #define MEM_MASK (IORESOURCE_MEM)
-#endif
-
 #define IO_MASK   (IORESOURCE_IO)
 #define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM)
 #define MEM_TYPE  (IORESOURCE_MEM)
 #define IO_TYPE   (IORESOURCE_IO)
 
 struct constraints {
-	struct resource pref, io, mem;
+	struct resource io, mem;
 };
 
 static void constrain_resources(struct device *dev, struct constraints* limits)
@@ -622,9 +623,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits)
 		}
 
 		/* PREFETCH, MEM, or I/O - skip any others. */
-		if ((res->flags & MEM_MASK) == PREF_TYPE)
-			lim = &limits->pref;
-		else if ((res->flags & MEM_MASK) == MEM_TYPE)
+		if ((res->flags & MEM_MASK) == MEM_TYPE)
 			lim = &limits->mem;
 		else if ((res->flags & IO_MASK) == IO_TYPE)
 			lim = &limits->io;
@@ -669,11 +668,9 @@ static void avoid_fixed_resources(struct device *dev)
 	printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev));
 
 	/* Initialize constraints to maximum size. */
-	limits.pref.base = 0;
-	limits.pref.limit = 0xffffffffffffffffULL;
 	limits.io.base = 0;
 	limits.io.limit = 0xffffffffffffffffULL;
-	limits.mem.base = 0;
+	limits.mem.base = 0xe0000000;
 	limits.mem.limit = 0xffffffffffffffffULL;
 
 	/* Constrain the limits to dev's initial resources. */
@@ -682,9 +679,6 @@ static void avoid_fixed_resources(struct device *dev)
 			continue;
 		printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__,
 		       dev_path(dev), res->index, res->limit);
-		if ((res->flags & MEM_MASK) == PREF_TYPE &&
-		    (res->limit < limits.pref.limit))
-			limits.pref.limit = res->limit;
 		if ((res->flags & MEM_MASK) == MEM_TYPE &&
 		    (res->limit < limits.mem.limit))
 			limits.mem.limit = res->limit;
@@ -704,9 +698,7 @@ static void avoid_fixed_resources(struct device *dev)
 			continue;
 
 		/* PREFETCH, MEM, or I/O - skip any others. */
-		if ((res->flags & MEM_MASK) == PREF_TYPE)
-			lim = &limits.pref;
-		else if ((res->flags & MEM_MASK) == MEM_TYPE)
+		if ((res->flags & MEM_MASK) == MEM_TYPE)
 			lim = &limits.mem;
 		else if ((res->flags & IO_MASK) == IO_TYPE)
 			lim = &limits.io;
@@ -1063,6 +1055,7 @@ void dev_configure(void)
 			}
 		}
 	}
+
 	assign_resources(root->link_list);
 	printk(BIOS_INFO, "Done setting resources.\n");
 	print_resource_tree(root, BIOS_SPEW, "After assigning values.");
diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc
index 34c5136..b39aaa2 100644
--- a/src/ec/acpi/Makefile.inc
+++ b/src/ec/acpi/Makefile.inc
@@ -1,2 +1,3 @@
 ramstage-y += ec.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c
+romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c
diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
index d3a6aaf..ab287d6 100644
--- a/src/ec/acpi/ec.c
+++ b/src/ec/acpi/ec.c
@@ -25,9 +25,18 @@
 #include <delay.h>
 #include "ec.h"
 
+#ifdef __PRE_RAM__
+
+static const int ec_cmd_reg = EC_SC;
+static const int ec_data_reg = EC_DATA;
+
+#else
+
 static int ec_cmd_reg = EC_SC;
 static int ec_data_reg = EC_DATA;
 
+#endif
+
 int send_ec_command(u8 command)
 {
 	int timeout;
@@ -132,12 +141,16 @@ void ec_clr_bit(u8 addr, u8 bit)
 	ec_write(addr, ec_read(addr) &  ~(1 << bit));
 }
 
+#ifndef __PRE_RAM__
+
 void ec_set_ports(u16 cmd_reg, u16 data_reg)
 {
 	ec_cmd_reg = cmd_reg;
 	ec_data_reg = data_reg;
 }
 
+#endif
+
 #if !defined(__SMM__) && !defined(__PRE_RAM__)
 struct chip_operations ec_acpi_ops = {
 	CHIP_NAME("ACPI Embedded Controller")
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index 368afa8..ef09b89 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -20,21 +20,30 @@
  */
 
 #include "smi.h"
+#ifdef CONFIG_BOARD_LENOVO_X201
+#define THINKPAD_EC_GPE 0x11
+#else
+#define THINKPAD_EC_GPE 28
+#endif
 Device(EC)
 {
 	Name (_HID, EISAID("PNP0C09"))
 	Name (_UID, 0)
 
-	Name (_GPE, 28)
+	Name (_GPE, THINKPAD_EC_GPE)
 	Mutex (ECLK, 0)
 
 	OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100)
 	Field (ERAM, ByteAcc, NoLock, Preserve)
 	{
+		Offset (0x02),
+		                DKR1, 1,
 		Offset (0x05),
 				HSPA, 1,
 		Offset (0x0C),
 				LEDS, 8,	/* LED state */
+		Offset (0x1a),
+		                DKR2, 1,
 		Offset (0x2a),
 				EVNT, 8,	/* write will trigger EC event */
 		Offset (0x3a),
@@ -50,7 +59,10 @@ Device(EC)
 				TMP0, 8,	/* Thermal Zone 0 temperature */
 				TMP1, 8,	/* Thermal Zone 1 temperature */
 		Offset (0x81),
-				PAGE, 8		/* Information Page Selector */
+				PAGE, 8,	/* Information Page Selector */
+		Offset (0xfe),
+		                    , 4,
+		                DKR3, 1
         }
 
 	Method (_CRS, 0)
@@ -86,9 +98,28 @@ Device(EC)
 	/* Sleep Button pressed */
 	Method(_Q13, 0, NotSerialized)
 	{
-		Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80)
+		Notify(^SLPB, 0x80)
 	}
 
+#if CONFIG_BOARD_LENOVO_X201
+	/* Brightness up GPE */
+	Method(_Q14, 0, NotSerialized)
+	{
+                Notify (\_SB.PCI0.GFX0.LCD0, 0x86)
+	}
+
+	/* Brightness down GPE */
+	Method(_Q15, 0, NotSerialized)
+	{
+                Notify (\_SB.PCI0.GFX0.LCD0, 0x87)
+	}
+
+	/* Next display GPE */
+	Method(_Q16, 0, NotSerialized)
+	{
+                Notify (\_SB.PCI0.GFX0, 0x82)
+	}
+#else
 	/* Brightness up GPE */
 	Method(_Q14, 0, NotSerialized)
 	{
@@ -100,7 +131,7 @@ Device(EC)
 	{
 		\DSPC.BRTD()
 	}
-
+#endif
 	/* AC status change: present */
 	Method(_Q26, 0, NotSerialized)
 	{
@@ -116,14 +147,181 @@ Device(EC)
 
        Method(_Q2A, 0, NotSerialized)
        {
-               Notify(\_SB.PCI0.LPCB.EC.LID, 0x80)
+               Notify(^LID, 0x80)
        }
 
        Method(_Q2B, 0, NotSerialized)
        {
-               Notify(\_SB.PCI0.LPCB.EC.LID, 0x80)
+               Notify(^LID, 0x80)
+       }
+
+
+       /* IBM proprietary buttons.  */
+
+       Method (_Q10, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x01)
+       }
+
+       Method (_Q11, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x02)
+       }
+
+       Method (_Q12, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x03)
+       }
+
+       Method (_Q64, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x05)
+       }
+
+       Method (_Q65, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x06)
+       }
+
+       Method (_Q17, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x08)
+       }
+
+       Method (_Q66, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x0A)
+       }
+
+       Method (_Q6A, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x1B)
+       }
+
+       Method (_Q1A, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x0B)
        }
 
+       Method (_Q1B, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x0C)
+       }
+
+       Method (_Q62, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x0D)
+       }
+
+       Method (_Q60, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x0E)
+       }
+
+       Method (_Q61, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x0F)
+       }
+
+       Method (_Q1F, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x12)
+       }
+
+       Method (_Q67, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x13)
+       }
+
+       Method (_Q63, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x14)
+       }
+
+       Method (_Q19, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x18)
+       }
+
+#if CONFIG_BOARD_LENOVO_X201
+       Method (_Q1C, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x19)
+       }
+
+       Method (_Q1D, 0, NotSerialized)
+       {
+            ^HKEY.RHK (0x1A)
+       }
+#endif
+
+       Device (HKEY)
+       {
+               Name (_HID, EisaId ("IBM0068"))
+  	       Name (BTN, 0)
+	       /* MASK */
+	       Name (DHKN, 0x080C)
+	       /* Effective Mask */
+	       Name (EMSK, 0)
+	       Name (EN, 0)
+               Method (_STA, 0, NotSerialized)
+               {
+                    Return (0x0F)
+               }
+               Method (MHKP, 0, NotSerialized)
+               {
+	            Store (BTN, Local0)
+		    If (LEqual (Local0, Zero)) {
+		       Return (Zero)
+                    }
+		    Store (Zero, BTN)
+		    Add (Local0, 0x1000, Local0)
+		    Return (Local0)
+               }
+	       /* Report event  */
+               Method (RHK, 1, NotSerialized) {
+                      ShiftLeft (One, Subtract (Arg0, 1), Local0)
+	              If (And (EMSK, Local0)) {
+                         Store (Arg0, BTN)
+                         Notify (HKEY, 0x80)
+                      }
+               }
+               Method (MHKC, 1, NotSerialized) {
+	                 If (Arg0) {
+		                Store (DHKN, EMSK)
+			 }
+			 Else
+			 {
+				Store (Zero, EMSK)
+			 }
+                         Store (Arg0, EN)
+               }
+               Method (MHKM, 2, NotSerialized) {
+                    If (LLessEqual (Arg0, 0x20)) {
+                                ShiftLeft (One, Subtract (Arg0, 1), Local0)
+                                If (Arg1)
+                                {
+                                    Or (DHKN, Local0, DHKN)
+                                }
+                                Else
+                                {
+                                    And (DHKN, Not (Local0), DHKN)
+                                }
+                                If (EN)
+				{
+				     Store (DHKN, EMSK)
+				}
+                    }
+               }
+               Method (MHKA, 0, NotSerialized)
+               {
+                    Return (0x07FFFFFF)
+               }
+               Method (MHKV, 0, NotSerialized)
+               {
+                    Return (0x0100)
+               }
+       }
 
 #include "ac.asl"
 #include "battery.asl"
diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl
index 35b6f14..70259f4 100644
--- a/src/ec/lenovo/h8/acpi/thermal.asl
+++ b/src/ec/lenovo/h8/acpi/thermal.asl
@@ -1,5 +1,9 @@
 Scope(\_TZ)
 {
+#ifdef CONFIG_BOARD_LENOVO_X201
+	Name (MEBT, 0)
+#endif
+
 	Method(C2K, 1, NotSerialized)
 	{
 		Multiply(Arg0, 10, Local0)
@@ -20,6 +24,13 @@ Scope(\_TZ)
 			Return (C2K(127))
 		}
 		Method(_TMP) {
+#ifdef CONFIG_BOARD_LENOVO_X201
+		        /* Avoid tripping alarm if ME isn't booted at all yet */
+		        If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) {
+                            Return (C2K(40))
+                        }
+#endif
+			Store (1, MEBT)
 			Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
 		}
 	}
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 9ffdfc1..5e859aa 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -27,6 +27,10 @@
 #include "chip.h"
 #include <pc80/mc146818rtc.h>
 
+#ifdef CONFIG_BOARD_LENOVO_X201
+#include "mainboard/lenovo/x201/dock.h"
+#endif
+
 static void h8_bluetooth_enable(int on)
 {
 	if (on)
@@ -37,8 +41,7 @@ static void h8_bluetooth_enable(int on)
 
 void h8_trackpoint_enable(int on)
 {
-	ec_write(H8_TRACKPOINT_CTRL,
-		 on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF);
+	ec_write(H8_TRACKPOINT_CTRL, on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF);
 
 }
 
@@ -50,6 +53,14 @@ void h8_wlan_enable(int on)
 		ec_clr_bit(0x3a, 5);
 }
 
+static void h8_3g_enable(int on)
+{
+	if (on)
+		ec_set_bit(0x3a, 6);
+	else
+		ec_clr_bit(0x3a, 6);
+}
+
 static void h8_log_ec_version(void)
 {
 	unsigned char ecfw[9], c;
@@ -150,17 +161,31 @@ static void h8_enable(device_t dev)
 	if (!get_option(&val, "volume"))
 		ec_write(H8_VOLUME_CONTROL, val);
 
+	if (get_option(&val, "bluetooth"))
+		val = 1;
+	h8_bluetooth_enable(val);
 
-	if (!get_option(&val, "bluetooth"))
-		h8_bluetooth_enable(val);
+	if (get_option(&val, "umts"))
+		val = 1;
 
-	if (!get_option(&val, "first_battery")) {
-		tmp = ec_read(H8_CONFIG3);
-		tmp &= ~(1 << 4);
-		tmp |= (val & 1)<< 4;
-		ec_write(H8_CONFIG3, tmp);
-	}
+	h8_3g_enable(val);
+
+	if (get_option(&val, "first_battery"))
+		val = 1;
+
+	tmp = ec_read(H8_CONFIG3);
+	tmp &= ~(1 << 4);
+	tmp |= (val & 1) << 4;
+	ec_write(H8_CONFIG3, tmp);
 	h8_set_audio_mute(0);
+
+#ifdef CONFIG_BOARD_LENOVO_X201
+	if (dock_present()) {
+		printk(BIOS_DEBUG, "dock is connected\n");
+		dock_connect();
+	} else
+		printk(BIOS_DEBUG, "dock is not connected\n");
+#endif
 }
 
 struct chip_operations ec_lenovo_h8_ops = {
diff --git a/src/include/delay.h b/src/include/delay.h
index 676579b..b0f7f7b 100644
--- a/src/include/delay.h
+++ b/src/include/delay.h
@@ -10,4 +10,5 @@ void init_timer(void);
 void udelay(unsigned usecs);
 void mdelay(unsigned msecs);
 void delay(unsigned secs);
+
 #endif /* DELAY_H */
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index c3b3437..09152cd 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -45,4 +45,5 @@ int early_usbdebug_init(void);
 void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data);
 void usbdebug_tx_flush(struct ehci_debug_info *info);
 int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info);
+unsigned char usbdebug_rx_byte(struct ehci_debug_info *dbg_info);
 #endif
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index 24d7967..974aba4 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -607,3 +607,25 @@ void usbdebug_tx_flush(struct ehci_debug_info *dbg_info)
 		dbg_info->bufidx = 0;
 	}
 }
+
+unsigned char usbdebug_rx_byte(struct ehci_debug_info *dbg_info)
+{
+	if (!dbg_info) {
+		/* "Find" dbg_info structure in Cache */
+		dbg_info = (struct ehci_debug_info *)
+		    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info));
+	}
+
+	if (dbg_info->ehci_debug) {
+		unsigned char c = 0xff;
+		u32 pids;
+		usbdebug_tx_flush (dbg_info);
+		pids = read32((unsigned long)&((struct ehci_dbg_port *) dbg_info->ehci_debug)->pids);
+		while (dbgp_bulk_read_x (dbg_info, &c, 1) <= 0);
+		write32((unsigned long)&((struct ehci_dbg_port *) dbg_info->ehci_debug)->pids, pids);
+		usbdebug_tx_byte(dbg_info, c);
+		usbdebug_tx_flush (dbg_info);
+		return c;
+	}
+	return 0xff;
+}
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index 8ee2778..7def45a 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -12,6 +12,11 @@ config BOARD_LENOVO_X60
 	    ThinkPad X60s (Model 1702, 1703)
 	    ThinkPad X60  (Model 1709)
 
+config BOARD_LENOVO_X201
+	bool "ThinkPad X201"
+	help
+	  New port.
+
 config BOARD_LENOVO_T60
 	bool "ThinkPad T60 / T60p"
 	help
@@ -23,6 +28,7 @@ config BOARD_LENOVO_T60
 endchoice
 
 source "src/mainboard/lenovo/x60/Kconfig"
+source "src/mainboard/lenovo/x201/Kconfig"
 source "src/mainboard/lenovo/t60/Kconfig"
 
 config MAINBOARD_VENDOR
diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
new file mode 100644
index 0000000..8450118
--- /dev/null
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -0,0 +1,59 @@
+if BOARD_LENOVO_X201
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_MODEL_2065X
+	select NORTHBRIDGE_INTEL_CALPELLA
+	select SOUTHBRIDGE_INTEL_CALPELLA
+	select SOUTHBRIDGE_RICOH_RL5C476
+	select SUPERIO_NSC_PC87382
+	select SUPERIO_NSC_PC87392
+	select EC_LENOVO_PMH7
+	select EC_LENOVO_H8
+	select DRIVERS_ICS_954309
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select MMCONF_SUPPORT
+	select GFXUMA
+	select BOARD_ROMSIZE_KB_8192
+	select CHANNEL_XOR_RANDOMIZATION
+	select HAVE_ACPI_TABLES
+	select HAVE_ACPI_RESUME
+	select UDELAY_TSC
+	select EARLY_CBMEM_INIT
+
+config MAINBOARD_DIR
+	string
+	default lenovo/x201
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "3626EN1"
+
+config MAINBOARD_VERSION
+	string
+	default "ThinkPad X201"
+
+config MAINBOARD_VENDOR
+	string
+	default "LENOVO"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 4
+
+config CPU_ADDR_BITS
+	int
+	default 36
+
+endif
diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc
new file mode 100644
index 0000000..1ed3999
--- /dev/null
+++ b/src/mainboard/lenovo/x201/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
+romstage-y += dock.c
+ramstage-y += dock.c
+
diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl
new file mode 100644
index 0000000..732ee90
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/dock.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB)
+{
+	Device(DOCK)
+	{
+		Name(_HID, "ACPI0003")
+		Name(_UID, 0x00)
+		Name(_PCL, Package() { \_SB } )
+
+		Method(_DCK, 1, NotSerialized)
+		{
+			if (Arg0) {
+			   /* connect dock */
+			   Store (1, \_SB.PCI0.LPCB.EC.DKR1)
+			   Store (1, \_SB.PCI0.LPCB.EC.DKR2)
+			   Store (1, \_SB.PCI0.LPCB.EC.DKR3)
+			} else {
+			   /* disconnect dock */
+			   Store (0, \_SB.PCI0.LPCB.EC.DKR1)
+			   Store (0, \_SB.PCI0.LPCB.EC.DKR2)
+			   Store (0, \_SB.PCI0.LPCB.EC.DKR3)
+			}
+			Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0)
+			Return (Local0)
+		}
+
+		Method(_STA, 0, NotSerialized)
+		{
+			Return (\_SB.PCI0.LPCB.EC.DKR1)
+		}
+	}
+}
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+	Method(_Q18, 0, NotSerialized)
+	{
+	       Notify(\_SB.DOCK, 3)
+	}
+
+	Method(_Q45, 0, NotSerialized)
+	{
+	       Notify(\_SB.DOCK, 3)
+	}
+
+	Method(_Q50, 0, NotSerialized)
+	{
+	       Notify(\_SB.DOCK, 3)
+	}
+
+	Method(_Q58, 0, NotSerialized)
+	{
+	       Notify(\_SB.DOCK, 0)
+	}
+
+	Method(_Q37, 0, NotSerialized)
+	{
+	       Notify(\_SB.DOCK, 0)
+	}
+}
diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl
new file mode 100644
index 0000000..4b3e72c
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl
new file mode 100644
index 0000000..b160b50
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/gpe.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+Scope (\_GPE)
+{
+	Method(_L18, 0, NotSerialized)
+	{
+		/* Read EC register to clear wake status */
+		Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
+	}
+}
diff --git a/src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..548996c
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+		Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+		Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+		Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+		Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 },
+		Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 },
+		Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }
+	})
+ } Else {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+		Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }
+	})
+}
diff --git a/src/mainboard/lenovo/x201/acpi/mainboard.asl b/src/mainboard/lenovo/x201/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl
new file mode 100644
index 0000000..2bf3a2b
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/platform.asl
@@ -0,0 +1,170 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	\_SB.PCI0.LPCB.EC.MUTE(1)
+	\_SB.PCI0.LPCB.EC.USBP(0)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4?
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	Return(Package(){0,0})
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+	/* This method is placed on the top level, so we can make sure it's the
+	 * first executed _INI method.
+	 */
+	Method(_INI, 0)
+	{
+		/* The DTS data in NVS is probably not up to date.
+		 * Update temperature values and make sure AP thermal
+		 * interrupts can happen
+		 */
+
+		// TRAP(71) // TODO
+
+		/* Determine the Operating System and save the value in OSYS.
+		 * We have to do this in order to be able to work around
+		 * certain windows bugs.
+		 *
+		 *    OSYS value | Operating System
+		 *    -----------+------------------
+		 *       2000    | Windows 2000
+		 *       2001    | Windows XP(+SP1)
+		 *       2002    | Windows XP SP2
+		 *       2006    | Windows Vista
+		 *       ????    | Windows 7
+		 */
+
+		/* Let's assume we're running at least Windows 2000 */
+		Store (2000, OSYS)
+
+		If (CondRefOf(_OSI, Local0)) {
+			/* Linux answers _OSI with "True" for a couple of
+			 * Windows version queries. But unlike Windows it
+			 * needs a Video repost, so let's determine whether
+			 * we're running Linux.
+			 */
+/*
+			If (_OSI("Linux")) {
+				Store (1, LINX)
+			}*/
+
+			If (_OSI("Windows 2001")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP1")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP2")) {
+				Store (2002, OSYS)
+			}
+
+			If (_OSI("Windows 2006")) {
+				Store (2006, OSYS)
+			}
+		}
+
+		/* And the OS workarounds start right after we know what we're
+		 * running: Windows XP SP1 needs to have C-State coordination
+		 * enabled in SMM.
+		 */
+		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+			// TRAP(61) // TODO
+		}
+
+		/* SMM power state and C4-on-C3 settings need to be updated */
+		// TRAP(43) // TODO
+	}
+}
+
diff --git a/src/mainboard/lenovo/x201/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..1fdef91
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			Package() { 0x0001ffff, 0, 0, 0x10 },
+			Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
+			Package() { 0x0003ffff, 0, 0, 0x10 },
+			Package() { 0x0016ffff, 0, 0, 0x10 }, // ME
+			Package() { 0x0016ffff, 1, 0, 0x11 }, // ME
+			Package() { 0x0016ffff, 2, 0, 0x12 }, // ME
+			Package() { 0x0016ffff, 3, 0, 0x13 }, // ME
+			Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet
+			Package() { 0x001affff, 0, 0, 0x14 }, // USB
+			Package() { 0x001affff, 1, 0, 0x15 }, // USB
+			Package() { 0x001affff, 2, 0, 0x16 }, // USB
+			Package() { 0x001affff, 3, 0, 0x17 }, // USB
+			Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
+			Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
+			Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
+			Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
+			Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
+			Package() { 0x001dffff, 0, 0, 0x10 }, // USB
+			Package() { 0x001dffff, 1, 0, 0x11 }, // USB
+			Package() { 0x001dffff, 2, 0, 0x12 }, // USB
+			Package() { 0x001dffff, 3, 0, 0x13 }, // USB
+			Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
+			Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
+			Package() { 0x001fffff, 2, 0, 0x11 }, // SATA
+			Package() { 0x001fffff, 3, 0, 0x13 }  // SMBUS
+		})
+	} Else {
+		Return (Package() {
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME
+			Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME
+			Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME
+			Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME
+			Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB
+			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB
+			Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB
+			Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB
+			Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }  // SMBus
+		})
+	}
+}
diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x201/acpi/video.asl b/src/mainboard/lenovo/x201/acpi/video.asl
new file mode 100644
index 0000000..95b7008
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/video.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB.PCI0.GFX0)
+{
+        Device (LCD0)
+        {
+              Name (_ADR, 0x0400)
+
+              Name (BRIG, Package (0x12)
+              {
+	      0xb2,
+	      0xb2,
+	      0x3,
+	      0x7,
+	      0x9,
+	      0xd,
+	      0x11,
+	      0x16,
+	      0x1a,
+	      0x21,
+	      0x27,
+	      0x2e,
+	      0x37,
+	      0x3f,
+	      0x4e,
+	      0x61,
+	      0x81,
+	      0xb2,
+              })
+
+
+              Method (_BCL, 0, NotSerialized)
+              {
+                  Return (BRIG)
+              }
+
+              Method (_BCM, 1, NotSerialized)
+              {
+                 Store (ShiftLeft (Arg0, 3), ^^BCLV)
+              }
+              Method (_BQC, 0, NotSerialized)
+              {
+                 Store (^^BCLV, Local0)
+		 ShiftRight (Local0, 3, Local0)
+                 Return (Local0)
+              }
+        }
+}
diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c
new file mode 100644
index 0000000..665d7be
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi_tables.c
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+
+	/* Enable both COM ports */
+	gnvs->cmap = 0x01;
+	gnvs->cmbp = 0x01;
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+					   1, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, MP_IRQ_POLARITY_DEFAULT | MP_IRQ_TRIGGER_DEFAULT);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
+
+	/* LAPIC_NMI */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+					      current, 0,
+					      MP_IRQ_POLARITY_HIGH |
+					      MP_IRQ_TRIGGER_EDGE, 0x01);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 1, MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 2, MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 3, MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+	void *gnvs;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	/* Fix up global NVS region for SMI handler. The GNVS region lives
+	 * in the (high) table area. The low memory map looks like this:
+	 *
+	 * 0x00000000 - 0x000003ff	Real Mode IVT
+	 * 0x00000020 - 0x0000019c	Low MP Table (XXX conflict?)
+	 * 0x00000400 - 0x000004ff	BDA (somewhat unused)
+	 * 0x00000500 - 0x0000052f	Moved GDT
+	 * 0x00000530 - 0x00000b64	coreboot table
+	 * 0x0007c000 - 0x0007dfff	OS boot sector (unused?)
+	 * 0x0007e000 - 0x0007ffff	free to use (so no good for acpi+smi)
+	 * 0x00080000 - 0x0009fbff	usable ram
+	 * 0x0009fc00 - 0x0009ffff	EBDA (unused?)
+	 * 0x000a0000 - 0x000bffff	VGA memory
+	 * 0x000c0000 - 0x000cffff	VGA option rom
+	 * 0x000d0000 - 0x000dffff	free for other option roms?
+	 * 0x000e0000 - 0x000fffff	SeaBIOS? (conflict with low tables:)
+	 * 0x000f0000 - 0x000f03ff	PIRQ table
+	 * 0x000f0400 - 0x000f66??	ACPI tables
+	 * 0x000f66?? - 0x000f????	DMI tables
+	 */
+
+	ALIGN_CURRENT;
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* Keep pointer around */
+	gnvs = (void *)current;
+
+	current += 0x100;
+	ALIGN_CURRENT;
+
+	/* And tell SMI about it */
+	smm_setup_structures(gnvs, NULL, NULL);
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+
+	/* Enable Dummy DCC ON# for DVI */
+	printk(BIOS_DEBUG, "Laptop handling...\n");
+	outb(inb(0x60f) & ~(1 << 5), 0x60f);
+
+	return current;
+}
diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout
new file mode 100644
index 0000000..6d2ac45
--- /dev/null
+++ b/src/mainboard/lenovo/x201/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# Stumpy USB reset workaround disable
+400         8         r       0        stumpy_usb_reset_disable
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+960         16        r       0        mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
new file mode 100644
index 0000000..c7b8716
--- /dev/null
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -0,0 +1,148 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/sandybridge
+
+
+	# Enable DisplayPort Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Enable Panel as LVDS and configure power delays
+	register "gpu_panel_port_select" = "0"			# LVDS
+	register "gpu_panel_power_cycle_delay" = "3"
+	register "gpu_panel_power_up_delay" = "250"
+	register "gpu_panel_power_down_delay" = "250"		
+	register "gpu_panel_power_backlight_on_delay" = "2500"	
+	register "gpu_panel_power_backlight_off_delay" = "2500"	
+	register "gpu_cpu_backlight" = "0x58d"
+	register "gpu_pch_backlight" = "0x061a061a"
+
+	chip ec/lenovo/pmh7
+	     device pnp ff.1 on # dummy
+	     end
+	     register "backlight_enable" = "0x01"
+	     register "dock_event_enable" = "0x01"
+	end
+
+				chip ec/lenovo/h8
+					device pnp ff.2 on # dummy
+						io 0x60 = 0x62
+						io 0x62 = 0x66
+						io 0x64 = 0x1600
+						io 0x66 = 0x1604
+					end
+
+					register "config0" = "0xa6"
+					register "config1" = "0x05"
+					register "config2" = "0xa0"
+					register "config3" = "0x01"
+
+					register "beepmask0" = "0xfe"
+					register "beepmask1" = "0x96"
+
+					register "event2_enable" = "0xff"
+					register "event3_enable" = "0xff"
+					register "event4_enable" = "0xf4"
+					register "event5_enable" = "0x3c"
+					register "event6_enable" = "0x80"
+					register "event7_enable" = "0x01"
+					register "eventc_enable" = "0x3c"
+					register "event8_enable" = "0x01"
+					register "event9_enable" = "0xff"
+					register "eventa_enable" = "0xff"
+					register "eventb_enable" = "0xff"
+					register "eventc_enable" = "0xff"
+					register "eventd_enable" = "0xff"
+
+					register "wlan_enable" = "0x01"
+					register "trackpoint_enable" = "0x03"
+				end
+
+	device cpu_cluster 0 on
+		chip cpu/intel/model_206ax
+			device lapic 0 on end
+		end
+	end
+
+	device domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x17aa 0x2193
+		end
+		device pci 02.0 on # VGA controller
+			subsystemid 0x17aa 0x215a
+		end
+		chip southbridge/intel/bd82x6x
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x0b"
+			register "pirqf_routing" = "0x0b"
+			register "pirqg_routing" = "0x0b"
+			register "pirqh_routing" = "0x0b"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi1_routing" = "2"
+			register "gpi13_routing" = "2"
+
+			register "sata_ahci" = "0x1"
+			register "sata_port_map" = "0x33"
+
+			register "gpe0_en" = "0x20022046"
+			register "alt_gp_smi_en" = "0x0000"
+
+			device pci 16.2 on # IDE/SATA
+				subsystemid 0x17aa 0x2161
+			end
+
+			device pci 19.0 on # Ethernet
+				subsystemid 0x17aa 0x2153
+			end 
+
+			device pci 1a.0 on # USB2 EHCI
+				subsystemid 0x17aa 0x2163
+			end
+
+#			register "c4onc3_enable" = "1"
+			device pci 1b.0 on # Audio Controller
+				subsystemid 0x17aa 0x215e
+			end
+			device pci 1d.0 on # USB2 EHCI
+				subsystemid 0x17aa 0x2163
+			end
+			device pci 1f.0 on # PCI-LPC bridge
+				subsystemid 0x17aa 0x2166
+			end
+			device pci 1f.2 on # IDE/SATA
+				subsystemid 0x17aa 0x2168
+			end
+			device pci 1f.3 on # SMBUS
+				subsystemid 0x17aa 0x2167
+			end
+		end
+		chip southbridge/ricoh/rl5c476
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c
new file mode 100644
index 0000000..6fae2cd
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dock.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#if !defined (__PRE_RAM__) && !defined (__SMM__)
+#define PCI_DEV(bus, dev, fn) dev_find_slot (bus, PCI_DEVFN (dev, fn))
+#endif
+#include <delay.h>
+#include "dock.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <ec/acpi/ec.h>
+
+int dock_connect(void)
+{
+	ec_set_bit (0x02, 0);
+	ec_set_bit (0x1a, 0);
+	ec_set_bit (0xfe, 4);
+	return 0;
+}
+
+void dock_disconnect(void)
+{
+	ec_clr_bit (0x02, 0);
+	ec_clr_bit (0x1a, 0);
+	ec_clr_bit (0xfe, 4);
+}
+
+int dock_present(void)
+{
+	u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+	u8 st = inb(gpiobase + 0x0c);
+	printk (BIOS_DEBUG, "GPIO status is 0x%x\n", st);
+
+	return !((st >> 3) & 1);
+}
+
+int dock_ultrabay_device_present(void)
+{
+	return 0;
+}
diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h
new file mode 100644
index 0000000..141ae48
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dock.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef THINKPAD_X60_DOCK_H
+#define THINKPAD_X60_DOCK_H
+
+extern int dock_connect(void);
+extern void dock_disconnect(void);
+extern int dock_present(void);
+extern int dlpc_init(void);
+extern int dock_ultrabay_device_present(void);
+#endif
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
new file mode 100644
index 0000000..bdee49b
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+	// General Purpose Events
+	#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+        #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/calpella/acpi/calpella.asl>
+			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+                Device (UNCR)
+                {
+                        Name (_BBN, 0xFF)
+                        Name (_ADR, 0x00)
+                        Name (RID, 0x00)
+                        Name (_HID, EisaId ("PNP0A03"))
+                        Name (_CRS, ResourceTemplate ()
+                              {
+                                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                                               0x0000,             // Granularity
+                                               0x00FF,             // Range Minimum
+                                               0x00FF,             // Range Maximum
+                                               0x0000,             // Translation Offset
+                                               0x0001,             // Length
+                                                ,, )
+                              })
+                       Device (SAD)
+                       {
+                              Name (_ADR, 0x01)
+                              Name (RID, 0x00)
+                              OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
+                              Field (SADC, DWordAcc, NoLock, Preserve)
+                              {
+                                  Offset (0x40), 
+                                  PAM0,   8, 
+                                  PAM1,   8, 
+                                  PAM2,   8, 
+                                  PAM3,   8, 
+                                  PAM4,   8, 
+                                  PAM5,   8, 
+                                  PAM6,   8
+                              }
+                       }
+                }
+	}
+
+	#include "acpi/video.asl"
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+
+	// Dock support code
+	#include "acpi/dock.asl"
+}
diff --git a/src/mainboard/lenovo/x201/fadt.c b/src/mainboard/lenovo/x201/fadt.c
new file mode 100644
index 0000000..8fbd0ac
--- /dev/null
+++ b/src/mainboard/lenovo/x201/fadt.c
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 0x00;
+	fadt->preferred_pm_profile = PM_MOBILE;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 0x10;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 0x23;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x32;
+	fadt->iapc_boot_arch = 0x00;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_DOCKING_SUPPORTED;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 0;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 32;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 0;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 128;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 0;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/lenovo/x201/irq_tables.c b/src/mainboard/lenovo/x201/irq_tables.c
new file mode 100644
index 0000000..f1ab06d
--- /dev/null
+++ b/src/mainboard/lenovo/x201/irq_tables.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 15,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xf5,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x00 << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* Host      0:00.0 */
+		{0x00, (0x02 << 3) | 0x0, {{0x60, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA       0:02.0 */
+		{0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio  0:1b.0 */
+		{0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.0 */
+		{0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.1 */
+		{0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.2 */
+		{0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.3 */
+		{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.0 */
+		{0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.1 */
+		{0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.2 */
+		{0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.3 */
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI       0:1e.0 */
+		{0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC       0:1f.0 */
+		{0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE       0:1f.1 */
+		{0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA      0:1f.2 */
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
new file mode 100644
index 0000000..ad92c5e
--- /dev/null
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -0,0 +1,297 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <northbridge/intel/calpella/calpella.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#include <pc80/mc146818rtc.h>
+#include "dock.h"
+#include <arch/x86/include/arch/acpigen.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+#include <x86emu/regs.h>
+#include <arch/interrupt.h>
+#endif
+#include <pc80/keyboard.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <smbios.h>
+
+static acpi_cstate_t cst_entries[] = {
+	{ 1,  1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
+	{ 2,  1,  500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
+	{ 2, 17,  250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
+};
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+	*entries = cst_entries;
+	return ARRAY_SIZE(cst_entries);
+}
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+
+static int int15_handler(void)
+{
+	switch((X86_EAX & 0xffff)) {
+	  /* Get boot display.  */
+	case 0x5f35:
+	        X86_EAX = 0x5f;
+#if 0
+		/* DisplayPort */
+	        X86_ECX = 0x4;
+		/* VGA */
+	        X86_ECX = 0x1;
+#endif
+		/* LCD */
+	        X86_ECX = 0x8;
+
+		return 1;
+	case 0x5f40:
+	        X86_EAX = 0x5f;
+	        X86_ECX = 0x2;
+		return 1;
+        default:
+		printk(BIOS_WARNING, "Unknown INT15 function %04x!\n",
+				X86_EAX & 0xffff);
+		return 0;
+	}
+}
+#endif
+
+static void rcba_config(void)
+{
+#if 0
+#if 0
+	u32 reg32;
+
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC (MSI)
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQB
+	 * D31IP_SIP   SATA   INTA -> PIRQA (MSI)
+	 * D31IP_SMIP  SMBUS  INTC -> PIRQH
+	 * D31IP_TTIP  THRT   INTB -> PIRQG
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 *
+	 * LIGHTSENSOR             -> PIRQE (Edge Triggered)
+	 * TRACKPAD                -> PIRQF (Edge Triggered)
+	 */
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) |
+	  (INTD << D31IP_UNKIP) | (INTA << D31IP_SMIP) | (INTB << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = 0x40043214;//(INTA << D29IP_E1P);
+	RCBA32(D28IP) = 0x00014321;//(INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+	//		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = 0x00000002;//(INTA << D27IP_ZIP);
+	RCBA32(D26IP) = 0x30003214;//(INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+#endif
+	RCBA32 (0x30fc) = 0x00000000;
+	(void) RCBA32 (0x30fc);
+	RCBA32 (0x3100) = 0x04341200;
+	(void) RCBA32 (0x3100);
+	RCBA32 (0x3104) = 0x00000000;
+	(void) RCBA32 (0x3104);
+	RCBA32 (0x3108) = 0x40043214;
+	(void) RCBA32 (0x3108);
+	RCBA32 (0x310c) = 0x00014321;
+	(void) RCBA32 (0x310c);
+	RCBA32 (0x3110) = 0x00000002;
+	(void) RCBA32 (0x3110);
+	RCBA32 (0x3114) = 0x30003214;
+	(void) RCBA32 (0x3114);
+	RCBA32 (0x311c) = 0x00000002;
+	(void) RCBA32 (0x311c);
+	RCBA32 (0x3120) = 0x00000000;
+	(void) RCBA32 (0x3120);
+	RCBA32 (0x3124) = 0x00002321;
+	(void) RCBA32 (0x3124);
+	RCBA32 (0x313c) = 0x00000000;
+	(void) RCBA32 (0x313c);
+	RCBA32 (0x3140) = 0x00003107;
+	(void) RCBA32 (0x3140);
+	RCBA32 (0x3144) = 0x76543210;
+	(void) RCBA32 (0x3144);
+	RCBA32 (0x3148) = 0x00000010;
+	(void) RCBA32 (0x3148);
+	RCBA32 (0x314c) = 0x00007654;
+	(void) RCBA32 (0x314c);
+	RCBA32 (0x3150) = 0x00000004;
+	(void) RCBA32 (0x3150);
+	RCBA32 (0x3158) = 0x00000000;
+	(void) RCBA32 (0x3158);
+	RCBA32 (0x315c) = 0x00003210;
+	(void) RCBA32 (0x315c);
+	RCBA32 (0x31fc) = 0x03000000;
+	(void) RCBA32 (0x31fc);
+
+#if 0
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
+	/* Disable unused devices (board specific) */
+	reg32 = RCBA32(FD);
+	reg32 |= PCH_DISABLE_ALWAYS;
+	RCBA32(FD) = reg32;
+#endif
+
+#if 0
+	RCBA32 (0x3418) = 0x16e61fe1;
+	(void) RCBA32 (0x3418);
+#endif
+#endif
+}
+
+const char *smbios_mainboard_version(void)
+{
+  return "Lenovo X201";
+}
+
+static void mainboard_enable(device_t dev)
+{
+	device_t dev0;
+	u8 defaults_loaded = 0;
+	u16 pmbase;
+
+	printk(BIOS_SPEW, "starting SPI configure\n");
+
+	/* Configure SPI.  */
+	RCBA32 (0x3800) = 0x07ff0500;
+	RCBA32 (0x3804) = 0x3f046008;
+	RCBA32 (0x3808) = 0x0058efc0;
+	RCBA32 (0x384c) = 0x92000000;
+	RCBA32 (0x3850) = 0x00000a0b;
+	RCBA32 (0x3858) = 0x07ff0500;
+	RCBA32 (0x385c) = 0x04ff0003;
+	RCBA32 (0x3860) = 0x00020001;
+	RCBA32 (0x3864) = 0x00000fff;
+	RCBA32 (0x3874) = 0x9fff07d0;
+	RCBA32 (0x3890) = 0xf8400000;
+	RCBA32 (0x3894) = 0x143b5006;
+	RCBA32 (0x3898) = 0x05200302;
+	RCBA32 (0x389c) = 0x0601209f;
+	RCBA32 (0x38b0) = 0x00000004;
+	RCBA32 (0x38b4) = 0x03040002;
+	RCBA32 (0x38c0) = 0x00000007;
+	RCBA32 (0x38c4) = 0x00802005;
+	RCBA32 (0x38c8) = 0x00002005;
+	RCBA32 (0x3804) = 0x3f04e008;
+
+	printk(BIOS_SPEW, "SPI configured\n");
+
+	pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+							PMBASE) & 0xff80;
+
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
+
+	outl(0, pmbase + SMI_EN);
+
+	printk(BIOS_ERR, " smi_en = 0x%08x\n", inl(pmbase + SMI_EN));
+
+	enable_lapic();
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, 0x10);
+
+	rcba_config();
+
+#ifdef DISABLED
+	ec_clr_bit(0x03, 2);
+
+	if (inb(0x164c) & 0x08) {
+		ec_set_bit(0x03, 2);
+		ec_write(0x0c, 0x88);
+	}
+#endif
+	/* If we're resuming from suspend, blink suspend LED */
+	dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
+	if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+		ec_write(0x0c, 0xc7);
+
+#ifdef DISABLED
+	idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
+	if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
+		struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
+		config->ide_enable_primary = 1;
+		/* enable Ultrabay power */
+		outb(inb(0x1628) | 0x01, 0x1628);
+		ec_write(0x0c, 0x84);
+	} else {
+		/* disable Ultrabay power */
+		outb(inb(0x1628) & ~0x01, 0x1628);
+		ec_write(0x0c, 0x04);
+	}
+#endif
+
+	if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
+		printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
+		defaults_loaded = 0;
+	}
+
+	if (!defaults_loaded) {
+		printk(BIOS_INFO, "Restoring CMOS defaults\n");
+		set_option("tft_brightness", &(u8[]){ 0xff });
+		set_option("volume", &(u8[]){ 0x03 });
+		/* set baudrate to 115200 baud */
+		set_option("baud_rate", &(u8[]){ 0x00 });
+		/* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
+		set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
+		set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
+	}
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+
+	/* This sneaked in here, because X201 SuperIO chip isn't really
+	   connected to anything and hence we don't init it.
+	 */
+	pc_keyboard_init(0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/lenovo/x201/mptable.c b/src/mainboard/lenovo/x201/mptable.c
new file mode 100644
index 0000000..a83a3a2
--- /dev/null
+++ b/src/mainboard/lenovo/x201/mptable.c
@@ -0,0 +1,61 @@
+/* generated by MPTable, version 2.0.15*/
+/* as modified by RGM for coreboot */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#define INTA 0x00
+#define INTB 0x01
+#define INTC 0x02
+#define INTD 0x03
+
+static void *smp_write_config_table(void *v)
+{
+        struct mp_config_table *mc;
+	int isa_bus;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+        mptable_init(mc, LOCAL_APIC_ADDR);
+
+        smp_write_processors(mc);
+
+	mptable_write_buses(mc, NULL, &isa_bus);
+	/* I/O APICs: APIC ID  Version  State  Address */
+	smp_write_ioapic(mc, 0x2, 0x20, 0xfec00000);
+
+	mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
+
+	/* I/O Ints: Type  Polarity  Trigger  Bus ID  IRQ  APIC ID  PIN#*/ 
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x1, 0x2, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x3, 0x2, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x4, 0x2, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x5, 0x2, 0x5);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x6, 0x2, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x7, 0x2, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x8, 0x2, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x9, 0x2, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xa, 0x2, 0xa);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xb, 0x2, 0xb);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xc, 0x2, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xd, 0x2, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xe, 0x2, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xf, 0x2, 0xf);
+	/* Local Ints: Type  Polarity  Trigger  Bus ID  IRQ  APIC ID  PIN# */
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x1);
+
+	return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
new file mode 100644
index 0000000..8259265
--- /dev/null
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -0,0 +1,985 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/car.h>
+#include <lib.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <ec/acpi/ec.h>
+#include <delay.h>
+#include <timestamp.h>
+
+#include "dock.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include "northbridge/intel/calpella/calpella.h"
+
+#include "northbridge/intel/calpella/calpella.h"
+#include "northbridge/intel/calpella/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include "southbridge/intel/bd82x6x/me.h"
+
+//#define SERIALICE 1
+
+static void pch_enable_lpc(void)
+{
+	/* Parrot EC Decode Range Port60/64, Port62/66 */
+	/* Enable EC, PS/2 Keyboard/Mouse */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | COMA_LPC_EN);
+
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001);
+
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+}
+
+
+static void rcba_config(void)
+{
+  static const u32 rcba_dump3[] = {
+    /* 30fc */    0x00000000,
+    /* 3100 */    0x04341200, 0x00000000, 0x40043214, 0x00014321, 
+    /* 3110 */    0x00000002, 0x30003214, 0x00000001, 0x00000002,
+    /* 3120 */    0x00000000, 0x00002321, 0x00000000, 0x00000000, 
+    /* 3130 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3140 */    0x00003107, 0x76543210, 0x00000010, 0x00007654,
+    /* 3150 */    0x00000004, 0x00000000, 0x00000000, 0x00003210,
+    /* 3160 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3170 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3180 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3190 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 31a0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    /* 31b0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 31c0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 31d0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 31e0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,    
+    /* 31f0 */    0x00000000, 0x00000000, 0x00000000, 0x03000000, 
+    /* 3200 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3210 */    0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    /* 3220 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3230 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3240 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3250 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3260 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3270 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3280 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3290 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 32a0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 32b0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 32c0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 32d0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,    
+    /* 32e0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    /* 32f0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    /* 3300 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3310 */    0x02060100, 0x0000000f, 0x01020000, 0x80000000,
+    /* 3320 */    0x00000000, 0x04000000, 0x00000000, 0x00000000,
+    /* 3330 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3340 */    0x000fffff, 0x00000000, 0x00000000, 0x00000000,
+    /* 3350 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3360 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3370 */    0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
+    /* 3380 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3390 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 33a0 */    0x00003900, 0x00000000, 0x00000000, 0x00000000,
+    /* 33b0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 33c0 */    0x00010000, 0x00000000, 0x00000000, 0x0001004b,
+    /* 33d0 */    0x06000008, 0x00010000, 0x00000000, 0x00000000,
+    /* 33e0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 33f0 */    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    /* 3400 */    0x0000001c, 0x00000080, 0x00000000, 0x00000000,
+    /* 3410 */    0x00000c61, 0x00000000, 0x16e61fe1, 0xbf4f001f,
+    /* 3420 */    0x00000000, 0x00060010, 0x0000001d, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,    
+    0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
+    0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
+    0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
+    0x20000557, 0x2000055f, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000001, 0x000026a3, 0x00040002, 0x01000052,
+    0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
+    0x00010000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x089c0018, 0x00000000, 0x00000000, 
+    0x11111111, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
+  };
+  unsigned i;
+  for (i = 0; i < sizeof (rcba_dump3) / 4; i++)
+    {
+      RCBA32 (4 * i + 0x30fc) = rcba_dump3[i];
+      (void) RCBA32 (4 * i + 0x30fc);
+    }
+
+#if 0
+	RCBA32 (0x30fc) = 0x00000000;
+	(void) RCBA32 (0x30fc);
+	RCBA32 (0x3100) = 0x04341200;
+	(void) RCBA32 (0x3100);
+	RCBA32 (0x3104) = 0x00000000;
+	(void) RCBA32 (0x3104);
+	RCBA32 (0x3108) = 0x40043214;
+	(void) RCBA32 (0x3108);
+	RCBA32 (0x310c) = 0x00014321;
+	(void) RCBA32 (0x310c);
+	RCBA32 (0x3110) = 0x00000002;
+	(void) RCBA32 (0x3110);
+	RCBA32 (0x3114) = 0x30003214;
+	(void) RCBA32 (0x3114);
+	RCBA32 (0x311c) = 0x00000002;
+	(void) RCBA32 (0x311c);
+	RCBA32 (0x3120) = 0x00000000;
+	(void) RCBA32 (0x3120);
+	RCBA32 (0x3124) = 0x00002321;
+	(void) RCBA32 (0x3124);
+	RCBA32 (0x313c) = 0x00000000;
+	(void) RCBA32 (0x313c);
+	RCBA32 (0x3140) = 0x00003107;
+	(void) RCBA32 (0x3140);
+	RCBA32 (0x3144) = 0x76543210;
+	(void) RCBA32 (0x3144);
+	RCBA32 (0x3148) = 0x00000010;
+	(void) RCBA32 (0x3148);
+	RCBA32 (0x314c) = 0x00007654;
+	(void) RCBA32 (0x314c);
+	RCBA32 (0x3150) = 0x00000004;
+	(void) RCBA32 (0x3150);
+	RCBA32 (0x3158) = 0x00000000;
+	(void) RCBA32 (0x3158);
+	RCBA32 (0x315c) = 0x00003210;
+	(void) RCBA32 (0x315c);
+	RCBA32 (0x31fc) = 0x03000000;
+	(void) RCBA32 (0x31fc);
+#endif
+}
+
+#include <cbmem.h>
+
+#ifdef SERIALICE
+static void
+sio_putc (char c)
+{
+  usbdebug_tx_byte(0, c);
+  usbdebug_tx_flush (0);
+}
+
+static char
+sio_getc (void)
+{
+  return usbdebug_rx_byte(0);
+}
+
+/* SIO helpers */
+
+static void sio_putstring(const char *string)
+{
+	/* Very simple, no %d, %x etc. */
+	while (*string) {
+		if (*string == '\n')
+			sio_putc('\r');
+		sio_putc(*string);
+		string++;
+	}
+}
+
+#define sio_put_nibble(nibble)	\
+	if (nibble > 9)		\
+		nibble += ('a' - 10);	\
+	else			\
+		nibble += '0';	\
+	sio_putc(nibble)
+
+static void sio_put8(u8 data)
+{
+	u8 c;
+		
+	c = (data >> 4) & 0xf;
+	sio_put_nibble(c);
+
+	c = data & 0xf;
+	sio_put_nibble(c);
+}
+
+static void sio_put16(u16 data)
+{
+	int i;
+	for (i=12; i >= 0; i -= 4) {
+		u8 c = (data >> i) & 0xf;
+		sio_put_nibble(c);
+	}
+}
+
+static void sio_put32(u32 data)
+{
+	int i;
+	for (i=28; i >= 0; i -= 4) {
+		u8 c = (data >> i) & 0xf;
+		sio_put_nibble(c);
+	}
+}
+
+static void sio_put64(u64 data)
+{
+	int i;
+	for (i=60; i >= 0; i -= 4) {
+		u8 c = (data >> i) & 0xf;
+		sio_put_nibble(c);
+	}
+}
+
+typedef struct _u128
+{
+  u64 lo;
+  u64 hi;
+} u128;
+
+static void sio_put128(u128 data)
+{
+	sio_put64 (data.hi);
+	sio_put64 (data.lo);
+}
+
+static u8 sio_get_nibble(void)
+{
+	u8 ret = 0;
+	u8 nibble = sio_getc();
+
+	if (nibble >= '0' && nibble <= '9') {
+		ret = (nibble - '0');
+	} else if (nibble >= 'a' && nibble <= 'f') {
+		ret = (nibble - 'a') + 0xa;
+	} else if (nibble >= 'A' && nibble <= 'F') {
+		ret = (nibble - 'A') + 0xa;
+	} else {
+		sio_putstring("ERROR: parsing number\n");
+	}
+	return ret;
+}
+
+static u8 sio_get8(void)
+{
+	u8 data;
+	data = sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	return data;
+}
+
+static u16 sio_get16(void)
+{
+	u16 data;
+
+	data = sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+
+	return data;
+}
+
+static u32 sio_get32(void)
+{
+	u32 data;
+
+	data = sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+
+	return data;
+}
+
+static u64 sio_get64(void)
+{
+	u64 data = 0;
+	int i;
+
+	for (i = 0; i < 64; i+=4)
+	  {
+	    data |= sio_get_nibble();
+	    data = data << 4;
+	  }
+
+	return data;
+}
+
+static u128 sio_get128(void)
+{
+	u128 data;
+	data.hi = sio_get64 ();
+	data.lo = sio_get64 ();
+
+	return data;
+}
+
+static u64
+read64 (u32 addr)
+{
+  u64 ret;
+  u64 stor;
+  asm volatile ("movq %%xmm0, %0\n"
+                "movq (%2), %%xmm0\n"
+		"movq %%xmm0, %1\n"
+		"movq %0, %%xmm0":"+m"(stor),"=m"(ret):"r"(addr));
+
+  return ret;
+}
+
+static void
+write64 (u32 addr, u64 val)
+{
+  u64 stor;
+  asm volatile ("movq %%xmm0, %0\n"
+		"movq %%xmm0, %1\n"
+                "movq (%2), %%xmm0\n"
+		"movq %0, %%xmm0":"+m"(stor):"m"(val),"r"(addr));
+}
+
+static u128
+read128 (u32 addr)
+{
+  u128 ret;
+  u128 stor;
+  asm volatile ("movdqu %%xmm0, %0\n"
+                "movdqa (%2), %%xmm0\n"
+		"movdqu %%xmm0, %1\n"
+		"movdqu %0, %%xmm0":"+m"(stor),"=m"(ret):"r"(addr));
+
+  return ret;
+}
+
+static void
+write128 (u32 addr, u128 val)
+{
+  u128 stor;
+  asm volatile ("movdqu %%xmm0, %0\n"
+		"movdqu %%xmm0, %1\n"
+                "movdqa (%2), %%xmm0\n"
+		"movdqu %0, %%xmm0":"+m"(stor):"m"(val),"r"(addr));
+}
+
+/* Accessor functions */
+
+static void serialice_read_memory(void)
+{
+	u8 width;
+	u32 addr;
+
+	// Format:
+	// *rm00000000.w
+	addr = sio_get32();
+	sio_getc();	// skip .
+	width = sio_getc();
+
+	sio_putc('\r'); sio_putc('\n');
+
+	switch (width) {
+	case 'b': sio_put8(read8(addr)); break;
+	case 'w': sio_put16(read16(addr)); break;
+	case 'l': sio_put32(read32(addr)); break;
+	case 'q': sio_put64(read64(addr)); break;
+	case 'p': sio_put128(read128(addr)); break;
+	}
+}
+
+static void serialice_clflush(void)
+{
+	u32 addr;
+
+	// Format:
+	// *fm00000000
+	addr = sio_get32();
+
+	sio_putc('\r'); sio_putc('\n');
+
+	asm volatile ("clflush (%0)" : : "r" (addr));
+}
+
+static void serialice_write_memory(void)
+{
+	u8 width;
+	u32 addr;
+	u64 data;
+	u128 data128;
+
+	// Format:
+	// *wm00000000.w=0000
+	addr = sio_get32();
+	sio_getc();	// skip .
+	width = sio_getc();
+	sio_getc();	// skip =
+
+	switch (width) {
+	case 'b': data = sio_get8(); write8(addr, (u8)data); break;
+	case 'w': data = sio_get16(); write16(addr, (u16)data); break;
+	case 'l': data = sio_get32(); write32(addr, (u32)data); break;
+	case 'q': data = sio_get64(); write64(addr, data); break;
+	case 'p': data128 = sio_get128(); write128(addr, data128); break;
+	}
+}
+
+static void serialice_read_io(void)
+{
+	u8 width;
+	u16 port;
+
+	// Format:
+	// *ri0000.w
+	port = sio_get16();
+	sio_getc();	// skip .
+	width = sio_getc();
+
+	sio_putc('\r'); sio_putc('\n');
+
+	switch (width) {
+	case 'b': sio_put8(inb(port)); break;
+	case 'w': sio_put16(inw(port)); break;
+	case 'l': sio_put32(inl(port)); break;
+	}
+}
+
+static void serialice_write_io(void)
+{
+	u8 width;
+	u16 port;
+	u32 data;
+
+	// Format:
+	// *wi0000.w=0000
+	port = sio_get16();
+	sio_getc();	// skip .
+	width = sio_getc();
+	sio_getc();	// skip =
+
+	switch (width) {
+	case 'b': data = sio_get8(); outb((u8)data, port); break;
+	case 'w': data = sio_get16(); outw((u16)data, port); break;
+	case 'l': data = sio_get32(); outl((u32)data, port); break;
+	}
+}
+
+static inline msr_t serialice_rdmsr(u32 index, u32 key)
+{
+	msr_t result;
+	__asm__ __volatile__ (
+		"rdmsr"
+		: "=a" (result.lo), "=d" (result.hi)
+		: "c" (index), "D" (key)
+	);
+	return result;
+}
+
+static inline void serialice_wrmsr(u32 index, msr_t msr, u32 key)
+{
+	__asm__ __volatile__ (
+		"wrmsr"
+		: /* No outputs */
+		: "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key)
+	);
+}
+
+
+static void serialice_read_msr(void)
+{
+	u32 addr, key;
+	msr_t msr;
+
+	// Format:
+	// *rc00000000.9c5a203a
+	addr = sio_get32();
+	sio_getc();	   // skip .
+	key = sio_get32(); // key in %edi
+
+	sio_putc('\r'); sio_putc('\n');
+
+	msr = serialice_rdmsr(addr, key);
+	sio_put32(msr.hi);
+	sio_putc('.');
+	sio_put32(msr.lo);
+}
+
+static void serialice_write_msr(void)
+{
+	u32 addr, key;
+	msr_t msr;
+
+	// Format:
+	// *wc00000000.9c5a203a=00000000.00000000
+	addr = sio_get32();
+	sio_getc();	// skip .
+	key = sio_get32(); // read key in %edi
+	sio_getc();	// skip =
+	msr.hi = sio_get32();
+	sio_getc();	// skip .
+	msr.lo = sio_get32();
+
+	serialice_wrmsr(addr, msr, key);
+}
+
+/* CPUID functions */
+
+static inline u32 cpuid_eax(u32 op, u32 op2)
+{
+        u32 eax;
+
+        __asm__("cpuid"
+                : "=a" (eax)
+                : "a" (op), "c" (op2)
+                : "ebx", "edx" );
+        return eax;
+}
+
+static inline u32 cpuid_ebx(u32 op, u32 op2)
+{
+        u32 ebx;
+
+        __asm__("cpuid"
+                : "=b" (ebx)
+                : "a" (op), "c" (op2)
+                : "edx");
+        return ebx;
+}
+
+static inline u32 cpuid_ecx(u32 op, u32 op2)
+{
+        u32 ecx;
+
+        __asm__("cpuid"
+                : "=c" (ecx)
+                : "a" (op), "c" (op2)
+                : "ebx", "edx" );
+        return ecx;
+}
+
+static inline u32 cpuid_edx(u32 op, u32 op2)
+{
+        u32 edx;
+
+        __asm__("cpuid"
+                : "=d" (edx)
+                : "a" (op), "c" (op2)
+                : "ebx");
+        return edx;
+}
+
+static void serialice_cpuinfo(void)
+{
+	u32 eax, ecx;
+	u32 reg32;
+
+	// Format:
+	//    --EAX--- --ECX---
+	// *ci00000000.00000000
+	eax = sio_get32();
+	sio_getc(); // skip .
+	ecx = sio_get32();
+
+	sio_putc('\r'); sio_putc('\n');
+
+	/* This code looks quite crappy but this way we don't
+ 	 * have to worry about running out of registers if we
+ 	 * occupy eax, ebx, ecx, edx at the same time 
+ 	 */
+	reg32 = cpuid_eax(eax, ecx);
+	sio_put32(reg32);
+	sio_putc('.');
+
+	reg32 = cpuid_ebx(eax, ecx);
+	sio_put32(reg32);
+	sio_putc('.');
+
+	reg32 = cpuid_ecx(eax, ecx);
+	sio_put32(reg32);
+	sio_putc('.');
+
+	reg32 = cpuid_edx(eax, ecx);
+	sio_put32(reg32);
+}
+
+static void serialice_mainboard(void)
+{
+	sio_putc('\r'); sio_putc('\n');
+
+	/* must be defined in mainboard/<boardname>.c */
+	sio_putstring("Lenovo X201");
+}
+
+static void serialice_version(void)
+{
+	sio_putstring("\nSerialICE vphcoder (" __DATE__ ")\n");
+}
+
+static void s3_checksum (void)
+{
+		int i, j;
+		u32 s;
+		u32 b = 0;
+
+		printk (BIOS_ERR, "S3 test\n")		;
+
+		for (i = 0; i < 2048; i++)
+		  {
+		    s = 0;
+		    for (j = ((i == 72) ? 0x800 : 0); j < (i ? 0x100000 : 0xa0000); j += 4)
+		      {
+			u32 v = *(u32 *) ((i << 20) | j);
+			if (v != ((i << 20) | j) && i >= 1)
+			  b++;
+			s += v;
+		      }
+		    if (((u8 *)(72 << 20))[i] != s % 255)
+		      {
+			printk (BIOS_ERR, "MiB %d corrupted %x vs %x\n", i,
+				((u8 *)(72 << 20))[i], s % 255);
+		      }
+		  }
+
+		printk (BIOS_ERR, "S3 test end, bad=%x\n", b);
+}
+
+
+static void serialice (void)
+{
+	serialice_version();
+
+	while(1) {
+		u16 c;
+		sio_putstring("\n> ");
+
+		c = sio_getc();
+		if (c != '*')
+			continue;
+
+		c = sio_getc() << 8;
+		c |= sio_getc();
+
+		switch(c) {
+		case (('r' << 8)|'a'):
+		{
+			u32 addr, len;
+			sio_getc();	// skip .
+			addr = sio_get32();
+			sio_getc();	// skip .
+			len = sio_get32 ();
+			ram_check (addr, len);
+			break;
+		}
+		case (('c' << 8)|'s'):
+			s3_checksum();
+			break;
+		case (('q' << 8)|'r'):
+			quick_ram_check();
+			break;
+		case (('q' << 8)|'s'):
+			return;
+		case (('r' << 8)|'m'): // Read Memory *rm
+			serialice_read_memory();
+			break;
+		case (('f' << 8)|'m'): // Flush Memory *fm
+			serialice_clflush();
+			break;
+		case (('w' << 8)|'m'): // Write Memory *wm
+			serialice_write_memory();
+			break;
+		case (('r' << 8)|'i'): // Read IO *ri
+			serialice_read_io();
+			break;
+		case (('w' << 8)|'i'): // Write IO *wi
+			serialice_write_io();
+			break;
+		case (('r' << 8)|'c'): // Read CPU MSR *rc
+			serialice_read_msr();
+			break;
+		case (('w' << 8)|'c'): // Write CPU MSR *wc
+			serialice_write_msr();
+			break;
+		case (('c' << 8)|'i'): // Read CPUID *ci
+			serialice_cpuinfo();
+			break;
+		case (('m' << 8)|'b'): // Read mainboard type *mb
+			serialice_mainboard();
+			break;
+		case (('v' << 8)|'i'): // Read version info *vi
+			serialice_version();
+			break;
+		case (('s' << 8)|'i'):
+			raminit (0);
+			break;
+		case (('s' << 8)|'3'):
+			raminit (1);
+			break;
+		case (('s' << 8)|'f'):
+			raminit (2);
+			break;
+		default:
+			sio_putstring("ERROR\n");
+			break;
+		}
+	}
+}
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t before_spd CAR_GLOBAL, after_spd CAR_GLOBAL, before_training CAR_GLOBAL, after_training CAR_GLOBAL;
+#endif
+
+void main(unsigned long bist)
+{
+	u32 reg32;
+	int s3resume = 0;
+#if CONFIG_COLLECT_TIMESTAMPS
+        tsc_t start_romstage_time;
+        tsc_t before_dram_time;
+        tsc_t after_dram_time;
+        tsc_t base_time = rdtsc ();
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	start_romstage_time = base_time;
+#endif
+
+	if (bist == 0)
+		enable_lapic();
+
+	/* Force PCIRST# */
+	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+	pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR);
+	udelay(200 * 1000);
+	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+	pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0);
+
+	/* Enable USB Power.  */
+	ec_set_bit(0x3b, 4);
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+	inw (DEFAULT_GPIOBASE | 0x38); // = 0x10
+	outl (0x7963a5ff, DEFAULT_GPIOBASE);
+	outl (0xffffffff, DEFAULT_GPIOBASE | 0xc);
+	outl (0x87bf6aff, DEFAULT_GPIOBASE | 0x4);
+	outl (0x0, DEFAULT_GPIOBASE | 0x18);
+	outl (0x120c6, DEFAULT_GPIOBASE | 0x2c);
+	outl (0x27706fe, DEFAULT_GPIOBASE | 0x30);
+	outl (0x29fffff, DEFAULT_GPIOBASE | 0x38);
+	outl (0x1b01f9f4, DEFAULT_GPIOBASE | 0x34);
+	outl (0x0, DEFAULT_GPIOBASE | 0x40);
+	outl (0x0, DEFAULT_GPIOBASE | 0x48);
+	outl (0xf00, DEFAULT_GPIOBASE | 0x44);
+	outl (0x41000000, DEFAULT_GPIOBASE | 0x60);
+
+	calpella_early_initialization(CALPELLA_MOBILE);
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+
+	console_init();
+
+#ifdef SERIALICE
+	serialice ();
+#endif
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	/* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+	  u8 reg8;
+	  reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
+	  printk(BIOS_DEBUG, "a2: %02x\n", reg8);
+	  if (!(reg8 & 0x20))
+	    {
+	      outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+	      printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
+	    }
+	  else
+	    {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		s3resume = 1;
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	    }
+	}
+
+#ifndef SERIALICE
+#if CONFIG_COLLECT_TIMESTAMPS
+        before_dram_time = rdtsc ();
+#endif
+	raminit(s3resume);
+#if CONFIG_COLLECT_TIMESTAMPS
+        after_dram_time = rdtsc ();
+#endif
+#endif
+
+	intel_early_me_status();
+
+	if (s3resume)
+	  {
+	    /* Clear SLP_TYPE. This will break stage2 but
+	     * we care for that when we get there.
+	     */
+	    reg32 = inl(DEFAULT_PMBASE + 0x04);
+	    outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+	  }
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Start address of high memory tables */
+	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+	if (s3resume && cbmem_reinit((u64)high_ram_base)) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+#if 0
+		s3_checksum ();
+#endif
+		/*		for (i = 0; i < 65536; i++)
+		  if (read8 (i) != read8 (i + 0x100000))
+			printk (BIOS_ERR, "Corruption at %x: %x vs %x\n", i,
+			read8 (i), read8 (i + 0x100000));*/
+
+
+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+		 * through stage 2. We could keep stuff like stack and heap in high tables
+		 * memory completely, but that's a wonderful clean up task for another
+		 * day.
+		 */
+		if (resume_backup_memory)
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+#if 0
+		printk (BIOS_ERR, "move: %x, %x, %x\n",(unsigned)resume_backup_memory, (unsigned)CONFIG_RAMBASE, (unsigned)HIGH_MEMORY_SAVE);
+
+		s = 0;
+		for (j = 0; j <  0x100000; j += 4)
+		  s += ((u32 *)resume_backup_memory)[j / 4];
+		if (((u8 *)(72 << 20))[1] != s % 255)
+		  {
+		    printk (BIOS_ERR, "MiB 1 (copy) corrupted %x vs %x\n",
+			    ((u8 *)(72 << 20))[1], s % 255);
+		  }
+		else
+		    printk (BIOS_ERR, "MiB 1 (copy) ok %x == %x\n",
+			    ((u8 *)(72 << 20))[1], s % 255);
+#endif
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	}
+	else if (s3resume) {
+		printk(BIOS_ERR, "Failed S3 resume.\n");
+		ram_check (0x100000, 0x200000);
+
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0xe, 0xcf9);
+		hlt();
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+		quick_ram_check();
+	}
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+        timestamp_init(base_time);
+        timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
+        timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
+        timestamp_add(101, before_spd);
+        timestamp_add(102, after_spd);
+        timestamp_add(103, before_training);
+        timestamp_add(104, after_training);
+        timestamp_add(TS_AFTER_INITRAM, after_dram_time);
+        timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+
+#if CONFIG_CONSOLE_CBMEM
+        /* Keep this the last thing this function does. */
+        cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/lenovo/x201/smi.h b/src/mainboard/lenovo/x201/smi.h
new file mode 100644
index 0000000..c5f48a1
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smi.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef MAINBOARD_LENOVO_X60_SMI_H
+#define MAINBOARD_LENOVO_X60_SMI_H
+
+#define SMI_DOCK_CONNECT 0x01
+#define SMI_DOCK_DISCONNECT 0x02
+#define SMI_SAVE_CMOS	0x03
+
+#endif
diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c
new file mode 100644
index 0000000..5a7130f
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c
@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "dock.h"
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+	printk(BIOS_DEBUG, "initializing SMI\n");
+	/* Enable 0x1600/0x1600 register pair */
+	ec_set_bit(0x00, 0x05);
+}
+
+static void mainboard_smi_save_cmos(void)
+{
+	u8 val;
+	u8 tmp70, tmp72;
+
+	tmp70 = inb(0x70);
+	tmp72 = inb(0x72);
+
+	val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+	set_option("tft_brightness", &val);
+	val = ec_read(H8_VOLUME_CONTROL);
+	set_option("volume", &val);
+
+	outb(tmp70, 0x70);
+	outb(tmp72, 0x72);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+	static int smm_initialized;
+
+	if (!smm_initialized) {
+		mainboard_smm_init();
+		smm_initialized = 1;
+	}
+
+	switch (smif) {
+	case SMI_DOCK_CONNECT:
+		ec_clr_bit(0x03, 2);
+		udelay(250000);
+		if (!dock_connect()) {
+			ec_set_bit(0x03, 2);
+			/* set dock LED to indicate status */
+			ec_write(0x0c, 0x09);
+			ec_write(0x0c, 0x88);
+		} else {
+			/* blink dock LED to indicate failure */
+			ec_write(0x0c, 0x08);
+			ec_write(0x0c, 0xc9);
+		}
+		break;
+
+	case SMI_DOCK_DISCONNECT:
+		ec_clr_bit(0x03, 2);
+		dock_disconnect();
+		break;
+
+	case SMI_SAVE_CMOS:
+		mainboard_smi_save_cmos();
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 1
+	 * On failure, the IO Trap Handler returns a value != 1 */
+	return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+	u8 value;
+
+	if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+		pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+	u8 value;
+
+	if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+		pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+	u8 status = inb(EC_SC);
+	u8 event;
+
+	if (!(status & EC_SCI_EVT))
+		return;
+
+	event = ec_query();
+	printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+	switch(event) {
+		/* brightness up */
+		case 0x14:
+			mainboard_smi_brightness_up();
+			mainboard_smi_save_cmos();
+			break;
+		/* brightness down */
+		case 0x15:
+			mainboard_smi_brightness_down();
+			mainboard_smi_save_cmos();
+			break;
+			/* Fn-F9 key */
+		case 0x18:
+			/* Power loss */
+		case 0x27:
+			/* Undock Key */
+		case 0x50:
+			mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
+			break;
+			/* Dock Event */
+		case 0x37:
+		case 0x58:
+			mainboard_io_trap_handler(SMI_DOCK_CONNECT);
+			break;
+		default:
+			break;
+	}
+}
+
+void mainboard_smi_gpi(u16 gpi)
+{
+	if (gpi & (1 << 12))
+		mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+	u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	u8 tmp;
+
+	printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+	if (!pmbase)
+		return 0;
+
+	switch(data) {
+		case APM_CNT_ACPI_ENABLE:
+			/* use 0x1600/0x1604 to prevent races with userspace */
+			ec_set_ports(0x1604, 0x1600);
+			/* route H8SCI to SCI */
+			outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x02;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			/* discard all events, and enable attention */
+			ec_write(0x80, 0x01);
+			break;
+		case APM_CNT_ACPI_DISABLE:
+			/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+			   provide a EC query function */
+			ec_set_ports(0x66, 0x62);
+			/* route H8SCI# to SMI */
+			outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x01;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			/* discard all events, and enable attention */
+			ec_write(0x80, 0x01);
+			break;
+		default:
+			break;
+	}
+	return 0;
+}
diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index a20f7b0..0ffa632 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -12,5 +12,6 @@ source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/gm45/Kconfig
 source src/northbridge/intel/sch/Kconfig
 source src/northbridge/intel/i5000/Kconfig
+source src/northbridge/intel/calpella/Kconfig
 source src/northbridge/intel/sandybridge/Kconfig
 source src/northbridge/intel/haswell/Kconfig
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 62e427d..061c4af 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -12,6 +12,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_CALPELLA) += calpella
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
diff --git a/src/northbridge/intel/calpella/Kconfig b/src/northbridge/intel/calpella/Kconfig
new file mode 100644
index 0000000..1451d23
--- /dev/null
+++ b/src/northbridge/intel/calpella/Kconfig
@@ -0,0 +1,83 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_CALPELLA
+	bool
+	select CACHE_MRC_BIN
+	select CPU_INTEL_MODEL_2065X
+	select VGA
+
+if NORTHBRIDGE_INTEL_CALPELLA
+
+config VGA_BIOS_ID
+	string
+	default "8086,0046"
+
+config CACHE_MRC_SIZE_KB
+	int
+	default 256
+
+# FIXME: build from rom size
+config MRC_CACHE_BASE
+	hex
+	default 0xff800000
+
+config MRC_CACHE_LOCATION
+	hex
+	depends on !CHROMEOS
+	default 0x500000
+
+config MRC_CACHE_SIZE
+	hex
+	depends on !CHROMEOS
+	default 0x10000
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	hex
+	default 0x4000
+
+config MARK_GRAPHICS_MEM_WRCOMB
+	bool "Mark graphics memory as write-combining."
+	default n
+	help
+	 The graphics performance may increase if the graphics
+	 memory is set as write-combining cache type. This option
+	 enables marking the graphics memory as write-combining.
+
+config CBFS_SIZE
+	hex "Size of CBFS filesystem in ROM"
+	default 0x100000
+	help
+	  On Sandybridge and Ivybridge systems the firmware image has to
+	  store a lot more than just coreboot, including:
+	   - a firmware descriptor
+	   - Intel Management Engine firmware
+	   - MRC cache information
+	  This option allows to limit the size of the CBFS portion in the
+	  firmware image.
+
+endif
diff --git a/src/northbridge/intel/calpella/Makefile.inc b/src/northbridge/intel/calpella/Makefile.inc
new file mode 100644
index 0000000..3f2af6c
--- /dev/null
+++ b/src/northbridge/intel/calpella/Makefile.inc
@@ -0,0 +1,34 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ramstage-y += northbridge.c
+ramstage-y += gma.c
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+ramstage-y += ../sandybridge/mrccache.c
+
+romstage-y += raminit.c
+romstage-y += early_init.c
+romstage-y += ../sandybridge/mrccache.c
+romstage-y += ../../../arch/x86/lib/walkcbfs.S
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+$(obj)/northbridge/intel/calpella/acpi.ramstage.o : $(obj)/build.h
diff --git a/src/northbridge/intel/calpella/acpi.c b/src/northbridge/intel/calpella/acpi.c
new file mode 100644
index 0000000..ba68c57
--- /dev/null
+++ b/src/northbridge/intel/calpella/acpi.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <build.h>
+#include "calpella.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	u32 pciexbar = 0;
+	u32 pciexbar_reg;
+	int max_buses;
+
+	dev = dev_find_slot(0xff, PCI_DEVFN (0, 1));
+
+	pciexbar_reg=read32 (0xeff01050);
+
+	// MMCFG not supported or not enabled.
+	if (!(pciexbar_reg & (1 << 0)))
+		return current;
+
+	switch ((pciexbar_reg >> 1) & 3) {
+	case 0: // 256MB
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		max_buses = 256;
+		break;
+	case 1: // 128M
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		max_buses = 128;
+		break;
+	case 2: // 64M
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		max_buses = 64;
+		break;
+	default: // RSVD
+		return current;
+	}
+
+	if (!pciexbar)
+		return current;
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+			pciexbar, 0x0, 0x0, max_buses - 1);
+
+	return current;
+}
+
+static void *get_intel_vbios(void)
+{
+	/* This should probably be looking at CBFS or we should always
+	 * deploy the VBIOS on Intel systems, even if we don't run it
+	 * in coreboot (e.g. SeaBIOS only scenarios).
+	 */
+	u8 *vbios = (u8 *)0xc0000;
+
+	optionrom_header_t *oprom = (optionrom_header_t *)vbios;
+	optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
+						oprom->pcir_offset);
+
+
+	printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
+		oprom->signature, pcir->vendor, pcir->classcode[0],
+		pcir->classcode[1], pcir->classcode[2]);
+
+
+	if ((oprom->signature == OPROM_SIGNATURE) &&
+		(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
+		(pcir->classcode[0] == 0x00) &&
+		(pcir->classcode[1] == 0x00) &&
+		(pcir->classcode[2] == 0x03))
+		return (void *)vbios;
+
+	return NULL;
+}
+
+static int init_opregion_vbt(igd_opregion_t *opregion)
+{
+	void *vbios;
+	vbios = get_intel_vbios();
+	if (!vbios) {
+		printk(BIOS_DEBUG, "VBIOS not found.\n");
+		return 1;
+	}
+
+	printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
+	optionrom_header_t *oprom = (optionrom_header_t *)vbios;
+	optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
+						oprom->vbt_offset);
+
+	if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+		printk(BIOS_DEBUG, "VBT not found!\n");
+		return 1;
+	}
+
+	memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
+	memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
+						vbt->hdr_vbt_size : 7168);
+
+	return 0;
+}
+
+
+/* Initialize IGD OpRegion, called from ACPI code */
+int init_igd_opregion(igd_opregion_t *opregion)
+{
+	device_t igd;
+	u16 reg16;
+
+	memset((void *)opregion, 0, sizeof(igd_opregion_t));
+
+	// FIXME if IGD is disabled, we should exit here.
+
+	memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+		sizeof(IGD_OPREGION_SIGNATURE));
+
+	/* 8kb */
+	opregion->header.size = sizeof(igd_opregion_t) / 1024;
+	opregion->header.version = IGD_OPREGION_VERSION;
+
+	// FIXME We just assume we're mobile for now
+	opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+	// TODO Initialize Mailbox 1
+
+	// TODO Initialize Mailbox 3
+	opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+	opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+	opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
+	opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+	opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+	opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+	opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+	opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+	opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+	opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+	opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+	opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+	opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+	opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+	opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+	init_opregion_vbt(opregion);
+
+	/* TODO This needs to happen in S3 resume, too.
+	 * Maybe it should move to the finalize handler
+	 */
+	igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
+
+	pci_write_config32(igd, ASLS, (u32)opregion);
+	reg16 = pci_read_config16(igd, SWSCI);
+	reg16 &= ~(1 << 0);
+	reg16 |= (1 << 15);
+	pci_write_config16(igd, SWSCI, reg16);
+
+	/* clear dmisci status */
+	reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
+	reg16 |= DMISCI_STS; // reference code does an &=
+	outw(DEFAULT_PMBASE + TCO1_STS, reg16);
+
+	/* clear acpi tco status */
+	outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
+
+	/* enable acpi tco scis */
+	reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
+	reg16 |= TCOSCI_EN;
+	outw(DEFAULT_PMBASE + GPE0_EN, reg16);
+
+	return 0;
+}
+
+
diff --git a/src/northbridge/intel/calpella/acpi/calpella.asl b/src/northbridge/intel/calpella/acpi/calpella.asl
new file mode 100644
index 0000000..757b29c
--- /dev/null
+++ b/src/northbridge/intel/calpella/acpi/calpella.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "../calpella.h"
+#include "hostbridge.asl"
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 1)
+
+	Name (PDRS, ResourceTemplate() {
+		Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
+		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
+		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+
+#if CONFIG_CHROMEOS_RAMOOPS
+		Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+					 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
+#endif
+
+		/* Required for SandyBridge sighting 3715511 */
+		Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
+		Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
+	})
+
+	// Current Resource Settings
+	Method (_CRS, 0, Serialized)
+	{
+		Return(PDRS)
+	}
+}
+
+// Integrated graphics 0:2.0
+#include "igd.asl"
diff --git a/src/northbridge/intel/calpella/acpi/hostbridge.asl b/src/northbridge/intel/calpella/acpi/hostbridge.asl
new file mode 100644
index 0000000..ded393b
--- /dev/null
+++ b/src/northbridge/intel/calpella/acpi/hostbridge.asl
@@ -0,0 +1,350 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+Name(_HID,EISAID("PNP0A08"))	// PCIe
+Name(_CID,EISAID("PNP0A03"))	// PCI
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Device (MCHC)
+{
+	Name(_ADR, 0x00000000)	// 0:0.0
+
+	OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
+	Field (MCHP, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x40),	// EPBAR
+		EPEN,	 1,	// Enable
+		,	11,	//
+		EPBR,	24,	// EPBAR
+
+		Offset (0x48),	// MCHBAR
+		MHEN,	 1,	// Enable
+		,	13,	//
+		MHBR,	22,	// MCHBAR
+
+		Offset (0x60),	// PCIe BAR
+		PXEN,	 1,	// Enable
+		PXSZ,	 2,	// BAR size
+		,	23,	//
+		PXBR,	10,	// PCIe BAR
+
+		Offset (0x68),	// DMIBAR
+		DMEN,	 1,	// Enable
+		,	11,	//
+		DMBR,	24,	// DMIBAR
+
+
+		Offset (0xa0),
+		TOM,	 16,
+		TUUD,	 16,
+
+		Offset (0xb0),	// Top of Low Used Memory
+		TLUD,	 16,
+	}
+
+	Mutex (CTCM, 1)		/* CTDP Switch Mutex (sync level 1) */
+	Name (CTCC, 0)		/* CTDP Current Selection */
+	Name (CTCN, 0)		/* CTDP Nominal Select */
+	Name (CTCD, 1)		/* CTDP Down Select */
+	Name (CTCU, 2)		/* CTDP Up Select */
+
+	OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
+	Field (MCHB, DWordAcc, Lock, Preserve)
+	{
+		Offset (0x5930),
+		CTDN, 15,	/* CTDP Nominal PL1 */
+		Offset (0x59a0),
+		PL1V, 15,	/* Power Limit 1 Value */
+		PL1E, 1,	/* Power Limit 1 Enable */
+		PL1C, 1,	/* Power Limit 1 Clamp */
+		PL1T, 7,	/* Power Limit 1 Time */
+		Offset (0x59a4),
+		PL2V, 15,	/* Power Limit 2 Value */
+		PL2E, 1,	/* Power Limit 2 Enable */
+		PL2C, 1,	/* Power Limit 2 Clamp */
+		PL2T, 7,	/* Power Limit 2 Time */
+		Offset (0x5f3c),
+		TARN, 8,	/* CTDP Nominal Turbo Activation Ratio */
+		Offset (0x5f40),
+		CTDD, 15,	/* CTDP Down PL1 */
+		, 1,
+		TARD, 8,	/* CTDP Down Turbo Activation Ratio */
+		Offset (0x5f48),
+		CTDU, 15,	/* CTDP Up PL1 */
+		, 1,
+		TARU, 8,	/* CTDP Up Turbo Activation Ratio */
+		Offset (0x5f50),
+		CTCS, 2,	/* CTDP Select */
+		Offset (0x5f54),
+		TARS, 8,	/* Turbo Activation Ratio Select */
+	}
+
+	/*
+	 * Search CPU0 _PSS looking for control=arg0 and then
+	 * return previous P-state entry number for new _PPC
+	 *
+	 * Format of _PSS:
+	 *   Name (_PSS, Package () {
+	 *     Package (6) { freq, power, tlat, blat, control, status }
+	 *   }
+	 */
+	External (\_PR.CPU0._PSS)
+	Method (PSSS, 1, NotSerialized)
+	{
+		Store (One, Local0) /* Start at P1 */
+		Store (SizeOf (\_PR.CPU0._PSS), Local1)
+
+		While (LLess (Local0, Local1)) {
+			/* Store _PSS entry Control value to Local2 */
+			ShiftRight (DeRefOf (Index (DeRefOf (Index
+			      (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2)
+			If (LEqual (Local2, Arg0)) {
+				Return (Subtract (Local0, 1))
+			}
+			Increment (Local0)
+		}
+
+		Return (0)
+	}
+
+	/* Set TDP Down */
+	Method (STND, 0, Serialized)
+	{
+		If (Acquire (CTCM, 100)) {
+			Return (0)
+		}
+		If (LEqual (CTCD, CTCC)) {
+			Release (CTCM)
+			Return (0)
+		}
+
+		Store ("Set TDP Down", Debug)
+
+		/* Set CTC */
+		Store (CTCD, CTCS)
+
+		/* Set TAR */
+		Store (TARD, TARS)
+
+		/* Set PPC limit and notify OS */
+		Store (PSSS (TARD), PPCM)
+		PPCN ()
+
+		/* Set PL2 to 1.25 * PL1 */
+		Divide (Multiply (CTDD, 125), 100, Local0, PL2V)
+
+		/* Set PL1 */
+		Store (CTDD, PL1V)
+
+		/* Store the new TDP Down setting */
+		Store (CTCD, CTCC)
+
+		Release (CTCM)
+		Return (1)
+	}
+
+	/* Set TDP Nominal from Down */
+	Method (STDN, 0, Serialized)
+	{
+		If (Acquire (CTCM, 100)) {
+			Return (0)
+		}
+		If (LEqual (CTCN, CTCC)) {
+			Release (CTCM)
+			Return (0)
+		}
+
+		Store ("Set TDP Nominal", Debug)
+
+		/* Set PL1 */
+		Store (CTDN, PL1V)
+
+		/* Set PL2 to 1.25 * PL1 */
+		Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
+
+		/* Set PPC limit and notify OS */
+		Store (PSSS (TARN), PPCM)
+		PPCN ()
+
+		/* Set TAR */
+		Store (TARN, TARS)
+
+		/* Set CTC */
+		Store (CTCN, CTCS)
+
+		/* Store the new TDP Nominal setting */
+		Store (CTCN, CTCC)
+
+		Release (CTCM)
+		Return (1)
+	}
+}
+
+// Current Resource Settings
+
+Method (_CRS, 0, Serialized)
+{
+	Name (MCRS, ResourceTemplate()
+	{
+		// Bus Numbers
+		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+		// IO Region 0
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+		// PCI Config Space
+		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		// IO Region 1
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+		// VGA memory (0xa0000-0xbffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000,,, ASEG)
+
+		// OPROM reserved (0xc0000-0xc3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000,,, OPR0)
+
+		// OPROM reserved (0xc4000-0xc7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000,,, OPR1)
+
+		// OPROM reserved (0xc8000-0xcbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000,,, OPR2)
+
+		// OPROM reserved (0xcc000-0xcffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000,,, OPR3)
+
+		// OPROM reserved (0xd0000-0xd3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000,,, OPR4)
+
+		// OPROM reserved (0xd4000-0xd7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000,,, OPR5)
+
+		// OPROM reserved (0xd8000-0xdbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000,,, OPR6)
+
+		// OPROM reserved (0xdc000-0xdffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000,,, OPR7)
+
+		// BIOS Extension (0xe0000-0xe3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000,,, ESG0)
+
+		// BIOS Extension (0xe4000-0xe7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000,,, ESG1)
+
+		// BIOS Extension (0xe8000-0xebfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000,,, ESG2)
+
+		// BIOS Extension (0xec000-0xeffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000,,, ESG3)
+
+		// System BIOS (0xf0000-0xfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000,,, FSEG)
+
+		// PCI Memory Region (Top of memory-0xfebfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
+				0xfec00000,,, PM01)
+
+		// TPM Area (0xfed40000-0xfed44fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+				0x00005000,,, TPMR)
+	})
+
+	// Find PCI resource area in MCRS
+	CreateDwordField(MCRS, PM01._MIN, PMIN)
+	CreateDwordField(MCRS, PM01._MAX, PMAX)
+	CreateDwordField(MCRS, PM01._LEN, PLEN)
+
+	// Fix up PCI memory region
+	// Start with Top of Lower Usable DRAM
+	Store (^MCHC.TLUD, Local0)
+	ShiftRight (Local0, 4, Local0)
+	Store (^MCHC.TUUD, Local1)
+
+	// Check if ME base is equal
+	If (LEqual (Local0, Local1)) {
+		// Use Top Of Memory instead
+		Store (^MCHC.TOM, Local0)
+		ShiftRight (Local0, 6, Local0)
+	}
+
+	ShiftLeft (Local0, 20, Local0)
+	Store (Local0, PMIN)
+	Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+	Return (MCRS)
+}
+
+/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
+#include "acpi/sandybridge_pci_irqs.asl"
+
+
diff --git a/src/northbridge/intel/calpella/acpi/igd.asl b/src/northbridge/intel/calpella/acpi/igd.asl
new file mode 100644
index 0000000..eaa55f2
--- /dev/null
+++ b/src/northbridge/intel/calpella/acpi/igd.asl
@@ -0,0 +1,338 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+
+	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+        Field (GFXC, DWordAcc, NoLock, Preserve)
+        {
+           Offset (0x10),
+	   BAR0, 64
+        }
+ 
+        OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+	Field (GFRG, DWordAcc, NoLock, Preserve)
+        {
+	   Offset (0x48254),
+           BCLV, 16
+        }
+
+	/* Display Output Switching */
+	Method (_DOS, 1)
+	{
+		/* Windows 2000 and Windows XP call _DOS to enable/disable
+		 * Display Output Switching during init and while a switch
+		 * is already active
+		 */
+		Store (And(Arg0, 7), DSEN)
+	}
+
+	/* We try to support as many i945 systems as possible,
+	 * so keep the number of DIDs flexible.
+	 */
+	Method (_DOD, 0)
+	{
+		If (LEqual(NDID, 1)) {
+			Name(DOD1, Package() {
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD1, 0))
+			Return(DOD1)
+		}
+
+		If (LEqual(NDID, 2)) {
+			Name(DOD2, Package() {
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID2), Index(DOD2, 0))
+			Store (Or(0x00010000, DID2), Index(DOD2, 1))
+			Return(DOD2)
+		}
+
+		If (LEqual(NDID, 3)) {
+			Name(DOD3, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID3), Index(DOD3, 0))
+			Store (Or(0x00010000, DID3), Index(DOD3, 1))
+			Store (Or(0x00010000, DID3), Index(DOD3, 2))
+			Return(DOD3)
+		}
+
+		If (LEqual(NDID, 4)) {
+			Name(DOD4, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID4), Index(DOD4, 0))
+			Store (Or(0x00010000, DID4), Index(DOD4, 1))
+			Store (Or(0x00010000, DID4), Index(DOD4, 2))
+			Store (Or(0x00010000, DID4), Index(DOD4, 3))
+			Return(DOD4)
+		}
+
+		If (LGreater(NDID, 4)) {
+			Name(DOD5, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID5), Index(DOD5, 0))
+			Store (Or(0x00010000, DID5), Index(DOD5, 1))
+			Store (Or(0x00010000, DID5), Index(DOD5, 2))
+			Store (Or(0x00010000, DID5), Index(DOD5, 3))
+			Store (Or(0x00010000, DID5), Index(DOD5, 4))
+			Return(DOD5)
+		}
+
+		/* Some error happened, but we have to return something */
+		Return (Package() {0x00000400})
+	}
+
+	Device(DD01)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID1, 0)) {
+				Return (1)
+			} Else {
+				Return (And(0xffff, DID1))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 1)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 1)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+	Device(DD02)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID2, 0)) {
+				Return (2)
+			} Else {
+				Return (And(0xffff, DID2))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 2)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 2)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD03)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID3, 0)) {
+				Return (3)
+			} Else {
+				Return (And(0xffff, DID3))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 4)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD04)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID4, 0)) {
+				Return (4)
+			} Else {
+				Return (And(0xffff, DID4))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 8)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD05)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID5, 0)) {
+				Return (5)
+			} Else {
+				Return (And(0xffff, DID5))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 16)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+}
+
diff --git a/src/northbridge/intel/calpella/calpella.h b/src/northbridge/intel/calpella/calpella.h
new file mode 100644
index 0000000..50e8e30
--- /dev/null
+++ b/src/northbridge/intel/calpella/calpella.h
@@ -0,0 +1,626 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __NORTHBRIDGE_INTEL_CALPELLA_CALPELLA_H__
+#define __NORTHBRIDGE_INTEL_CALPELLA_CALPELLA_H__ 1
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+typedef enum {
+	FSB_CLOCK_1067MHz	= 0,
+	FSB_CLOCK_800MHz	= 1,
+	FSB_CLOCK_667MHz	= 2,
+} fsb_clock_t;
+
+typedef enum { /* Steppings below B1 were pre-production,
+		  conversion stepping A1 is... ?
+		  We'll support B1, B2, B3, and conversion stepping A1. */
+	STEPPING_A0 = 0,
+	STEPPING_A1 = 1,
+	STEPPING_A2 = 2,
+	STEPPING_A3 = 3,
+	STEPPING_B0 = 4,
+	STEPPING_B1 = 5,
+	STEPPING_B2 = 6,
+	STEPPING_B3 = 7,
+	STEPPING_CONVERSION_A1 = 9,
+} stepping_t;
+
+typedef enum {
+	GMCH_GM45 = 0,
+	GMCH_GM47,
+	GMCH_GM49,
+	GMCH_GE45,
+	GMCH_GL40,
+	GMCH_GL43,
+	GMCH_GS40,
+	GMCH_GS45,
+	GMCH_PM45,
+	GMCH_UNKNOWN
+} gmch_gfx_t;
+
+typedef enum {
+	MEM_CLOCK_533MHz  = 0,
+	MEM_CLOCK_400MHz  = 1,
+	MEM_CLOCK_333MHz  = 2,
+	MEM_CLOCK_1067MT  = 0,
+	MEM_CLOCK_800MT   = 1,
+	MEM_CLOCK_667MT   = 2,
+} mem_clock_t;
+
+typedef enum {
+	DDR1 = 1,
+	DDR2 = 2,
+	DDR3 = 3,
+} ddr_t;
+
+typedef enum {
+	CHANNEL_MODE_SINGLE,
+	CHANNEL_MODE_DUAL_ASYNC,
+	CHANNEL_MODE_DUAL_INTERLEAVED,
+} channel_mode_t;
+
+typedef enum { /* as in DDR3 spd */
+	CHIP_WIDTH_x4	= 0,
+	CHIP_WIDTH_x8	= 1,
+	CHIP_WIDTH_x16	= 2,
+	CHIP_WIDTH_x32	= 3,
+} chip_width_t;
+
+typedef enum { /* as in DDR3 spd */
+	CHIP_CAP_256M	= 0,
+	CHIP_CAP_512M	= 1,
+	CHIP_CAP_1G	= 2,
+	CHIP_CAP_2G	= 3,
+	CHIP_CAP_4G	= 4,
+	CHIP_CAP_8G	= 5,
+	CHIP_CAP_16G	= 6,
+} chip_capacity_t;
+
+typedef struct {
+	unsigned int	CAS;
+	fsb_clock_t	fsb_clock;
+	mem_clock_t	mem_clock;
+	channel_mode_t	channel_mode;
+	unsigned int	tRAS;
+	unsigned int	tRP;
+	unsigned int	tRCD;
+	unsigned int	tRFC;
+	unsigned int	tWR;
+	unsigned int	tRD;
+	unsigned int	tRRD;
+	unsigned int	tFAW;
+	unsigned int	tWL;
+} timings_t;
+
+typedef struct {
+	unsigned int	card_type; /* 0x0: unpopulated,
+				      0xa - 0xf: raw card type A - F */
+	chip_width_t	chip_width;
+	chip_capacity_t	chip_capacity;
+	unsigned int	page_size; /* of whole DIMM in Bytes (4096 or 8192) */
+	unsigned int	banks;
+	unsigned int	ranks;
+	unsigned int	rank_capacity_mb; /* per rank in Mega Bytes */
+} dimminfo_t;
+
+/* The setup is one DIMM per channel, so there's no need to find a
+   common timing setup between multiple chips (but chip and controller
+   still need to be coordinated */
+typedef struct {
+	stepping_t	stepping;
+	int		txt_enabled;
+	int		cores;
+	gmch_gfx_t	gfx_type;
+	int		gs45_low_power_mode; /* low power mode of GMCH_GS45 */
+	int		max_ddr2_mhz;
+	int		max_ddr3_mt;
+	fsb_clock_t	max_fsb;
+	int		max_fsb_mhz;
+	int		max_render_mhz;
+
+	int		spd_type;
+	timings_t	selected_timings;
+	dimminfo_t	dimms[2];
+} sysinfo_t;
+
+#define TOTAL_CHANNELS 2
+#define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
+#define CHANNEL_IS_CARDF(dimms, idx) (dimms[idx].card_type == 0xf)
+#define IF_CHANNEL_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)
+#define FOR_EACH_CHANNEL(idx) \
+	for (idx = 0; idx < TOTAL_CHANNELS; ++idx)
+#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \
+	FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx)
+
+#define RANKS_PER_CHANNEL 4 /* Only two may be populated */
+#define IF_RANK_POPULATED(dimms, ch, r) \
+	if (dimms[ch].card_type && ((r) < dimms[ch].ranks))
+#define FOR_EACH_RANK_IN_CHANNEL(r) \
+	for (r = 0; r < RANKS_PER_CHANNEL; ++r)
+#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \
+	FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r)
+#define FOR_EACH_RANK(ch, r) \
+	FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r)
+#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \
+	FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r)
+
+#define DDR3_MAX_CAS 18
+
+
+enum {
+	VCO_2666 = 4,
+	VCO_3200 = 0,
+	VCO_4000 = 1,
+	VCO_5333 = 2,
+};
+
+#endif
+
+/* Offsets of read/write training results in CMOS.
+   They will be restored upon S3 resumes. */
+#define CMOS_READ_TRAINING	0x80 /* 16 bytes */
+#define CMOS_WRITE_TRAINING	0x90 /* 16 bytes
+					(could be reduced to 10 bytes) */
+
+
+#define DEFAULT_HECIBAR		0xfed17000
+
+				/* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
+
+#define IOMMU_BASE1 0xfed90000
+#define IOMMU_BASE2 0xfed91000
+#define IOMMU_BASE3 0xfed92000
+#define IOMMU_BASE4 0xfed93000
+
+/*
+ * D0:F0
+ */
+#define D0F0_EPBAR_LO 0x40
+#define D0F0_EPBAR_HI 0x44
+#define D0F0_MCHBAR_LO 0x48
+#define D0F0_MCHBAR_HI 0x4c
+#define D0F0_GGC 0x52
+#define D0F0_DEVEN 0x54
+#define  DEVEN_PEG60	(1 << 13)
+#define  DEVEN_IGD	(1 << 4)
+#define  DEVEN_PEG10	(1 << 3)
+#define  DEVEN_PEG11	(1 << 2)
+#define  DEVEN_PEG12	(1 << 1)
+#define  DEVEN_HOST	(1 << 0)
+#define D0F0_PCIEXBAR_LO 0x60
+#define D0F0_PCIEXBAR_HI 0x64
+#define D0F0_DMIBAR_LO 0x68
+#define D0F0_DMIBAR_HI 0x6c
+#define D0F0_PMBASE 0x78
+#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/
+#define D0F0_REMAPBASE 0x98
+#define D0F0_REMAPLIMIT 0x9a
+#define D0F0_SMRAM 0x9d
+#define D0F0_ESMRAMC 0x9e
+#define D0F0_TOM 0xa0
+#define D0F0_TOUUD 0xa2
+#define D0F0_IGD_BASE 0xa4
+#define D0F0_GTT_BASE 0xa8
+#define D0F0_TOLUD 0xb0
+#define D0F0_SKPD 0xdc /* Scratchpad Data */
+
+#define SKPAD_ACPI_S3_MAGIC	0xcafed00d
+#define SKPAD_NORMAL_BOOT_MAGIC	0xcafebabe
+
+
+#define D0F0_CAPID0 0xe0
+
+#define TSEG		0xac	/* TSEG base */
+
+/*
+ * D1:F0 PEG
+ */
+#define PEG_CAP 0xa2
+#define SLOTCAP 0xb4
+#define PEGLC 0xec
+#define D1F0_VCCAP 0x104
+#define D1F0_VC0RCTL 0x114
+
+/*
+ * Graphics frequencies
+ */
+#define GCFGC_PCIDEV		PCI_DEV(0, 2, 0)
+#define GCFGC_OFFSET		0xf0
+#define GCFGC_CR_SHIFT		0
+#define GCFGC_CR_MASK		(0xf << GCFGC_CR_SHIFT)
+#define GCFGC_CS_SHIFT		8
+#define GCFGC_CS_MASK		(0xf << GCFGC_CS_SHIFT)
+#define GCFGC_CD_SHIFT		12
+#define GCFGC_CD_MASK		(0x1 << GCFGC_CD_SHIFT)
+#define GCFGC_UPDATE_SHIFT	5
+#define GCFGC_UPDATE		(0x1 << GCFGC_UPDATE_SHIFT)
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+
+#define PMSTS_MCHBAR		0x0f14	/* Self refresh channel status */
+#define PMSTS_WARM_RESET	(1 << 1)
+#define PMSTS_BOTH_SELFREFRESH	(1 << 0)
+
+#define CLKCFG_MCHBAR		0x0c00
+#define CLKCFG_FSBCLK_SHIFT	0
+#define CLKCFG_FSBCLK_MASK	(7 << CLKCFG_FSBCLK_SHIFT)
+#define CLKCFG_MEMCLK_SHIFT	4
+#define CLKCFG_MEMCLK_MASK	(7 << CLKCFG_MEMCLK_SHIFT)
+#define CLKCFG_UPDATE		(1 << 12)
+
+#define SSKPD_MCHBAR		0x0c1c
+#define SSKPD_CLK_SHIFT		0
+#define SSKPD_CLK_MASK		(7 << SSKPD_CLK_SHIFT)
+
+#define DCC_MCHBAR		0x200
+#define DCC_NO_CHANXOR		(1 << 10)
+#define DCC_INTERLEAVED		(1 <<  1)
+#define DCC_CMD_SHIFT		16
+#define DCC_CMD_MASK		(7 << DCC_CMD_SHIFT)
+#define DCC_CMD_NOP		(1 << DCC_CMD_SHIFT)
+				/* For mode register mr0: */
+#define DCC_SET_MREG		(3 << DCC_CMD_SHIFT)
+				/* For extended mode registers mr1 to mr3: */
+#define DCC_SET_EREG		(4 << DCC_CMD_SHIFT)
+#define DCC_SET_EREG_SHIFT	21
+#define DCC_SET_EREG_MASK	(DCC_CMD_MASK | (3 << DCC_SET_EREG_SHIFT))
+#define DCC_SET_EREGx(x)	((DCC_SET_EREG |			   \
+					((x - 1) << DCC_SET_EREG_SHIFT)) & \
+				 DCC_SET_EREG_MASK)
+
+/* Per channel DRAM Row Attribute registers (32-bit) */
+#define CxDRA_MCHBAR(x)		(0x1208 + (x * 0x0100))
+#define CxDRA_PAGESIZE_SHIFT(r)	(r * 4)		/* Per rank r */
+#define CxDRA_PAGESIZE_MASKr(r)	(0x7 << CxDRA_PAGESIZE_SHIFT(r))
+#define CxDRA_PAGESIZE_MASK	0x0000ffff
+#define CxDRA_PAGESIZE(r, p)	/* for log2(dimm page size in bytes) p */ \
+	(((p - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r))
+#define CxDRA_BANKS_SHIFT(r)	((r * 3) + 16)
+#define CxDRA_BANKS_MASKr(r)	(0x3 << CxDRA_BANKS_SHIFT(r))
+#define CxDRA_BANKS_MASK	0x07ff0000
+#define CxDRA_BANKS(r, b)	/* for number of banks b */ \
+	((b << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r))
+
+/*
+ * Per channel DRAM Row Boundary registers (32-bit)
+ * Every two ranks share one register and must be programmed at the same time.
+ * All registers (4 ranks per channel) have to be set.
+ */
+#define CxDRBy_MCHBAR(x, r)	(0x1200 + (x * 0x0100) + ((r/2) * 4))
+#define CxDRBy_BOUND_SHIFT(r)	((r % 2) * 16)
+#define CxDRBy_BOUND_MASK(r)	(0x1fc << CxDRBy_BOUND_SHIFT(r))
+#define CxDRBy_BOUND_MB(r, b)	/* for boundary in MB b */ \
+	(((b >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r))
+
+#define CxDRC0_MCHBAR(x)	(0x1230 + (x * 0x0100))
+#define CxDRC0_RANKEN0		(1 << 24)	/* Rank Enable */
+#define CxDRC0_RANKEN1		(1 << 25)
+#define CxDRC0_RANKEN2		(1 << 26)
+#define CxDRC0_RANKEN3		(1 << 27)
+#define CxDRC0_RANKEN(r)	(1 << (24 + r))
+#define CxDRC0_RANKEN_MASK	(0xf << 24)
+#define CxDRC0_RMS_SHIFT	8		/* Refresh Mode Select */
+#define CxDRC0_RMS_MASK		(7 << CxDRC0_RMS_SHIFT)
+#define CxDRC0_RMS_78US		(2 << CxDRC0_RMS_SHIFT)
+#define CxDRC0_RMS_39US		(3 << CxDRC0_RMS_SHIFT)
+
+#define CxDRC1_MCHBAR(x)	(0x1234 + (x * 0x0100))
+#define CxDRC1_SSDS_SHIFT	24
+#define CxDRC1_SSDS_MASK	(0xff << CxDRC1_SSDS_SHIFT)
+#define CxDRC1_DS		(0x91 << CxDRC1_SSDS_SHIFT)
+#define CxDRC1_SS		(0xb1 << CxDRC1_SSDS_SHIFT)
+#define CxDRC1_NOTPOP(r)	(1 << (16 + r)) /* Write 1 for Not Populated */
+#define CxDRC1_NOTPOP_MASK	(0xf << 16)
+#define CxDRC1_MUSTWR		(3 << 11)
+
+#define CxDRC2_MCHBAR(x)	(0x1238 + (x * 0x0100))
+#define CxDRC2_NOTPOP(r)	(1 << (24 + r)) /* Write 1 for Not Populated */
+#define CxDRC2_NOTPOP_MASK	(0xf << 24)
+#define CxDRC2_MUSTWR		(1 << 12)
+#define CxDRC2_CLK1067MT	(1 << 0)
+
+/* DRAM Timing registers (32-bit each) */
+#define CxDRT0_MCHBAR(x)	(0x1210 + (x * 0x0100))
+#define CxDRT0_BtB_WtP_SHIFT	26
+#define CxDRT0_BtB_WtP_MASK	(0x1f << CxDRT0_BtB_WtP_SHIFT)
+#define CxDRT0_BtB_WtR_SHIFT	20
+#define CxDRT0_BtB_WtR_MASK	(0x1f << CxDRT0_BtB_WtR_SHIFT)
+#define CxDRT1_MCHBAR(x)	(0x1214 + (x * 0x0100))
+#define CxDRT2_MCHBAR(x)	(0x1218 + (x * 0x0100))
+#define CxDRT3_MCHBAR(x)	(0x121c + (x * 0x0100))
+#define CxDRT4_MCHBAR(x)	(0x1220 + (x * 0x0100))
+#define CxDRT5_MCHBAR(x)	(0x1224 + (x * 0x0100))
+#define CxDRT6_MCHBAR(x)	(0x1228 + (x * 0x0100))
+
+/* Clock disable registers (32-bit each) */
+#define CxDCLKDIS_MCHBAR(x)	(0x120c + (x * 0x0100))
+#define CxDCLKDIS_MASK		3
+#define CxDCLKDIS_ENABLE	3 /* Always enable both clock pairs. */
+
+/* On-Die-Termination registers (2x 32-bit per channel) */
+#define CxODT_HIGH(x)		(0x124c + (x * 0x0100))
+#define CxODT_LOW(x)		(0x1248 + (x * 0x0100))
+
+/* Write Training registers. */
+#define CxWRTy_MCHBAR(ch, s)	(0x1470 + (ch * 0x0100) + ((3 - s) * 4))
+
+#define CxGTEW(x)		(0x1270+(x*0x100))
+#define CxGTC(x)		(0x1274+(x*0x100))
+#define CxDTPEW(x)		(0x1278+(x*0x100))
+#define CxDTAEW(x)		(0x1280+(x*0x100))
+#define CxDTC(x)		(0x1288+(x*0x100))
+
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+#define DMIVC0RCTL 0x14
+#define DMIESD  0x44
+
+
+/*
+ * EPBAR
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+
+#ifndef __ASSEMBLER__
+void gm45_early_init(void);
+void gm45_early_reset(void);
+
+void enter_raminit_or_reset(void);
+void get_gmch_info(sysinfo_t *);
+void raminit_thermal(const sysinfo_t *);
+void init_igd(const sysinfo_t *, int no_igd, int no_peg);
+void init_pm(const sysinfo_t *);
+
+int raminit_read_vco_index(void);
+u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
+
+void raminit_rcomp_calibration(stepping_t stepping);
+void raminit_reset_readwrite_pointers(void);
+void raminit_receive_enable_calibration(const timings_t *, const dimminfo_t *);
+void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
+void raminit_read_training(const dimminfo_t *, int s3resume);
+
+void gm45_late_init(stepping_t);
+
+u32 decode_igd_memory_size(u32 gms);
+u32 decode_igd_gtt_size(u32 gsm);
+
+void init_iommu(void);
+#endif
+
+/* Chipset types */
+#define CALPELLA_MOBILE	0
+#define CALPELLA_DESKTOP	1
+#define CALPELLA_SERVER	2
+
+/* Device ID for SandyBridge and IvyBridge */
+#define BASE_REV_SNB	0x00
+#define BASE_REV_IVB	0x50
+#define BASE_REV_MASK	0x50
+
+/* SandyBridge CPU stepping */
+#define SNB_STEP_D0	(BASE_REV_SNB + 5) /* Also J0 */
+#define SNB_STEP_D1	(BASE_REV_SNB + 6)
+#define SNB_STEP_D2	(BASE_REV_SNB + 7) /* Also J1/Q0 */
+
+/* IvyBridge CPU stepping */
+#define IVB_STEP_A0	(BASE_REV_IVB + 0)
+#define IVB_STEP_B0	(BASE_REV_IVB + 2)
+#define IVB_STEP_C0	(BASE_REV_IVB + 4)
+#define IVB_STEP_K0	(BASE_REV_IVB + 5)
+#define IVB_STEP_D0	(BASE_REV_IVB + 6)
+
+/* Intel Enhanced Debug region must be 4MB */
+#define IED_SIZE	0x400000
+
+/* Northbridge BARs */
+#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */
+#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
+#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
+#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+#define DEFAULT_RCBABASE	0xfed1c000
+
+#define QUICKPATH_BUS 0xff
+
+#include <southbridge/intel/bd82x6x/pch.h>
+
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define X60BAR		0x60
+
+#define LAC		0x87	/* Legacy Access Control */
+#define SMRAM		0x88	/* System Management RAM Control */
+#define  D_OPEN		(1 << 6)
+#define  D_CLS		(1 << 5)
+#define  D_LCK		(1 << 4)
+#define  G_SMRAME	(1 << 3)
+#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+#define SKPAD		0xdc	/* Scratchpad Data */
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+
+#define BCTRL1		0x3e	/* 16bit */
+
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define MSAC		0x62	/* Multi Size Aperture Control */
+#define SWSCI		0xe8	/* SWSCI  enable */
+#define ASLS		0xfc	/* OpRegion Base */
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))
+
+#define SSKPD		0x5d14	/* 16bit (scratchpad) */
+#define BIOS_RESET_CPL	0x5da8	/* 8bit */
+
+/*
+ * EPBAR - Egress Port Root Complex Register Block
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+#define EPPVCCAP1	0x004	/* 32bit */
+#define EPPVCCAP2	0x008	/* 32bit */
+
+#define EPVC0RCAP	0x010	/* 32bit */
+#define EPVC0RCTL	0x014	/* 32bit */
+#define EPVC0RSTS	0x01a	/* 16bit */
+
+#define EPVC1RCAP	0x01c	/* 32bit */
+#define EPVC1RCTL	0x020	/* 32bit */
+#define EPVC1RSTS	0x026	/* 16bit */
+
+#define EPVC1MTS	0x028	/* 32bit */
+#define EPVC1IST	0x038	/* 64bit */
+
+#define EPESD		0x044	/* 32bit */
+
+#define EPLE1D		0x050	/* 32bit */
+#define EPLE1A		0x058	/* 64bit */
+#define EPLE2D		0x060	/* 32bit */
+#define EPLE2A		0x068	/* 64bit */
+
+#define PORTARB		0x100	/* 256bit */
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+#define DMIVCECH	0x000	/* 32bit */
+#define DMIPVCCAP1	0x004	/* 32bit */
+#define DMIPVCCAP2	0x008	/* 32bit */
+
+#define DMIPVCCCTL	0x00c	/* 16bit */
+
+#define DMIVC0RCAP	0x010	/* 32bit */
+#define DMIVC0RCTL0	0x014	/* 32bit */
+#define DMIVC0RSTS	0x01a	/* 16bit */
+
+#define DMIVC1RCAP	0x01c	/* 32bit */
+#define DMIVC1RCTL	0x020	/* 32bit */
+#define DMIVC1RSTS	0x026	/* 16bit */
+
+#define DMILE1D		0x050	/* 32bit */
+#define DMILE1A		0x058	/* 64bit */
+#define DMILE2D		0x060	/* 32bit */
+#define DMILE2A		0x068	/* 64bit */
+
+#define DMILCAP		0x084	/* 32bit */
+#define DMILCTL		0x088	/* 16bit */
+#define DMILSTS		0x08a	/* 16bit */
+
+#define DMICTL1		0x0f0	/* 32bit */
+#define DMICTL2		0x0fc	/* 32bit */
+
+#define DMICC		0x208	/* 32bit */
+
+#define DMIDRCCFG	0xeb4	/* 32bit */
+
+#ifndef __ASSEMBLER__
+static inline void barrier(void) { asm("" ::: "memory"); }
+
+struct ied_header {
+	char signature[10];
+	u32 size;
+	u8 reserved[34];
+} __attribute__ ((packed));
+
+#define PCI_DEVICE_ID_SB 0x0104
+#define PCI_DEVICE_ID_IB 0x0154
+
+#ifdef __SMM__
+void intel_sandybridge_finalize_smm(void);
+#else /* !__SMM__ */
+int bridge_silicon_revision(void);
+void calpella_early_initialization(int chipset_type);
+void calpella_late_initialization(void);
+
+/* debugging functions */
+void print_pci_devices(void);
+void dump_pci_device(unsigned dev);
+void dump_pci_devices(void);
+void dump_spd_registers(void);
+void dump_mem(unsigned start, unsigned end);
+void report_platform_info(void);
+#endif /* !__SMM__ */
+
+
+#define MRC_DATA_ALIGN           0x1000
+#define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
+
+struct mrc_data_container {
+	u32	mrc_signature;	// "MRCD"
+	u32	mrc_data_size;	// Actual total size of this structure
+	u32	mrc_checksum;	// IP style checksum
+	u32	reserved;	// For header alignment
+	u8	mrc_data[0];	// Variable size, platform/run time dependent.
+} __attribute__ ((packed));
+
+struct mrc_data_container *find_current_mrc_cache(void);
+#if !defined(__PRE_RAM__)
+#include "gma.h"
+int init_igd_opregion(igd_opregion_t *igd_opregion);
+#endif
+
+#endif
+#endif
+#endif
diff --git a/src/northbridge/intel/calpella/chip.h b/src/northbridge/intel/calpella/chip.h
new file mode 100644
index 0000000..16df91b
--- /dev/null
+++ b/src/northbridge/intel/calpella/chip.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Digital Port Hotplug Enable:
+ *  0x04 = Enabled, 2ms short pulse
+ *  0x05 = Enabled, 4.5ms short pulse
+ *  0x06 = Enabled, 6ms short pulse
+ *  0x07 = Enabled, 100ms short pulse
+ */
+struct northbridge_intel_sandybridge_config {
+	u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
+	u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
+	u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
+
+	u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
+	u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
+	u16 gpu_panel_power_up_delay;            /* T1+T2 time sequence */
+	u16 gpu_panel_power_down_delay;          /* T3 time sequence */
+	u16 gpu_panel_power_backlight_on_delay;  /* T5 time sequence */
+	u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
+
+	u32 gpu_cpu_backlight;	/* CPU Backlight PWM value */
+	u32 gpu_pch_backlight;	/* PCH Backlight PWM value */
+};
+
diff --git a/src/northbridge/intel/calpella/early_init.c b/src/northbridge/intel/calpella/early_init.c
new file mode 100644
index 0000000..716318a
--- /dev/null
+++ b/src/northbridge/intel/calpella/early_init.c
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <elog.h>
+#include "calpella.h"
+#include "pcie_config.c"
+
+static void calpella_setup_bars(void)
+{
+	/* Setting up Southbridge. In the northbridge code. */
+	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+
+	printk(BIOS_DEBUG, " done.\n");
+
+	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
+	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
+	printk(BIOS_DEBUG, " done.\n");
+
+	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
+	/* Set up all hardcoded northbridge BARs */
+	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
+	pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32);
+	pci_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1);
+
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+
+	/* Set C0000-FFFFF to access RAM on both reads and writes */
+	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
+	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33);
+	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33);
+	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33);
+	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33);
+	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
+	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
+
+#if CONFIG_ELOG_BOOT_COUNT
+	/* Increment Boot Counter for non-S3 resume */
+	if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
+	    ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
+		boot_count_increment();
+#endif
+
+	printk(BIOS_DEBUG, " done.\n");
+
+#if CONFIG_ELOG_BOOT_COUNT
+	/* Increment Boot Counter except when resuming from S3 */
+	if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
+	    ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
+		return;
+	boot_count_increment();
+#endif
+}
+
+static void calpella_setup_graphics(void)
+{
+	u32 reg32;
+	u16 reg16;
+	u8 reg8;
+
+	reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID);
+	switch (reg16) {
+	case 0x0102: /* GT1 Desktop */
+	case 0x0106: /* GT1 Mobile */
+	case 0x010a: /* GT1 Server */
+	case 0x0112: /* GT2 Desktop */
+	case 0x0116: /* GT2 Mobile */
+	case 0x0122: /* GT2 Desktop >=1.3GHz */
+	case 0x0126: /* GT2 Mobile >=1.3GHz */
+	case 0x0156: /* IvyBridge */
+	case 0x0166: /* IvyBridge */
+		break;
+	default:
+		printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n");
+		return;
+	}
+
+	return;
+
+	printk(BIOS_DEBUG, "Initializing Graphics...\n");
+
+	/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+	reg16 = pci_read_config16(PCI_DEV(0,0,0), D0F0_GGC);
+	reg16 &= ~0x00f8;
+	reg16 |= 1 << 3;
+	/* Program GTT memory by setting GGC[9:8] = 2MB */
+	reg16 &= ~0x0300;
+	reg16 |= 2 << 8;
+	/* Enable VGA decode */
+	reg16 &= ~0x0002;
+	pci_write_config16(PCI_DEV(0,0,0), D0F0_GGC, reg16);
+
+	/* Enable 256MB aperture */
+	reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC);
+	reg8 &= ~0x06;
+	reg8 |= 0x02;
+	pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8);
+
+	/* Erratum workarounds */
+	reg32 = MCHBAR32(0x5f00);
+	reg32 |= (1 << 9)|(1 << 10);
+	MCHBAR32(0x5f00) = reg32;
+
+	/* Enable SA Clock Gating */
+	reg32 = MCHBAR32(0x5f00);
+	MCHBAR32(0x5f00) = reg32 | 1;
+
+	/* GPU RC6 workaround for sighting 366252 */
+	reg32 = MCHBAR32(0x5d14);
+	reg32 |= (1 << 31);
+	MCHBAR32(0x5d14) = reg32;
+
+	/* VLW */
+	reg32 = MCHBAR32(0x6120);
+	reg32 &= ~(1 << 0);
+	MCHBAR32(0x6120) = reg32;
+
+	reg32 = MCHBAR32(0x5418);
+	reg32 |= (1 << 4) | (1 << 5);
+	MCHBAR32(0x5418) = reg32;
+}
+
+void calpella_early_initialization(int chipset_type)
+{
+	u32 capid0_a;
+	u8 reg8;
+
+	/* Device ID Override Enable should be done very early */
+	capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
+	if (capid0_a & (1 << 10)) {
+		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
+		reg8 &= ~7; /* Clear 2:0 */
+
+		if (chipset_type == CALPELLA_MOBILE)
+			reg8 |= 1; /* Set bit 0 */
+
+		pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
+	}
+
+	/* Setup all BARs required for early PCIe and raminit */
+	calpella_setup_bars();
+
+	/* Device Enable */
+	pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, 9);
+
+	calpella_setup_graphics();
+}
diff --git a/src/northbridge/intel/calpella/fake_vbios.c b/src/northbridge/intel/calpella/fake_vbios.c
new file mode 100644
index 0000000..3fccb1f
--- /dev/null
+++ b/src/northbridge/intel/calpella/fake_vbios.c
@@ -0,0 +1,1797 @@
+ my_outb(0x03c2, 0x23);// Device I/O <--
+ my_outb(0x03da, 0x02);// Device I/O <--
+ my_inb(0x03c2);// Device I/O --> 10
+ my_outb(0x03da, 0x01);// Device I/O <--
+ my_inb(0x03c2);// Device I/O --> 10
+ my_outl(0x1040, 0x00070080);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00070180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00071180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00041000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00002900
+ my_outl(0x1044, 0x8000298e);// Device I/O 
+ my_outl(0x1040, 0x0007019c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0007119c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00000000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> ffffffff
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00000000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> ffffffff
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00000000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> ffffffff
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00000000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> ffffffff
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00000000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> ffffffff
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x000fc008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outl(0x1040, 0x000fc020);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outl(0x1040, 0x000fc038);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outl(0x1040, 0x000fc050);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outl(0x1040, 0x000fc408);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outl(0x1040, 0x000fc420);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outl(0x1040, 0x000fc438);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outl(0x1040, 0x000fc450);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 2c010757
+ my_outl(0x1044, 0x2c010000);// Device I/O 
+ my_outw(0x03ce, 0x0018);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x01000001);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f048);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x03030000);// Device I/O 
+ my_outl(0x1040, 0x0004f050);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000001);// Device I/O 
+ my_outl(0x1040, 0x0004f058);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1044, 0x03030000);// Device I/O 
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1044, 0x03030000);// Device I/O 
+ my_outl(0x1040, 0x00042004);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x02000000);// Device I/O 
+ my_outl(0x1040, 0x000fd034);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 39cfffe0
+ my_outl(0x1044, 0x8421ffe0);// Device I/O 
+int i;
+for (i = 0; i < 0x1fff; i++)
+  {
+    my_outl(0x1040, 0x00000001 | (i << 2));// Device I/O 
+    my_outl(0x1044, 0xc2000001 | (i << 12));// Device I/O 
+  } 
+ my_outw(0x03c4, 0x0302);// Device I/O 
+ my_outw(0x03c4, 0x0003);// Device I/O 
+ my_outw(0x03c4, 0x0204);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outw(0x03c4, 0x0300);// Device I/O 
+ my_outb(0x03c2, 0x67);// Device I/O <--
+ my_outb(0x03d4, 0x11);// Device I/O <--
+ my_inw(0x03d4);// Device I/O --> 0x0011
+ my_outw(0x03d4, 0x0011);// Device I/O 
+ my_outw(0x03d4, 0x5f00);// Device I/O 
+ my_outw(0x03d4, 0x4f01);// Device I/O 
+ my_outw(0x03d4, 0x5002);// Device I/O 
+ my_outw(0x03d4, 0x8203);// Device I/O 
+ my_outw(0x03d4, 0x5504);// Device I/O 
+ my_outw(0x03d4, 0x8105);// Device I/O 
+ my_outw(0x03d4, 0xbf06);// Device I/O 
+ my_outw(0x03d4, 0x1f07);// Device I/O 
+ my_outw(0x03d4, 0x0008);// Device I/O 
+ my_outw(0x03d4, 0x4f09);// Device I/O 
+ my_outw(0x03d4, 0x0d0a);// Device I/O 
+ my_outw(0x03d4, 0x0e0b);// Device I/O 
+ my_outw(0x03d4, 0x000c);// Device I/O 
+ my_outw(0x03d4, 0x000d);// Device I/O 
+ my_outw(0x03d4, 0x000e);// Device I/O 
+ my_outw(0x03d4, 0x000f);// Device I/O 
+ my_outw(0x03d4, 0x9c10);// Device I/O 
+ my_outw(0x03d4, 0x8e11);// Device I/O 
+ my_outw(0x03d4, 0x8f12);// Device I/O 
+ my_outw(0x03d4, 0x2813);// Device I/O 
+ my_outw(0x03d4, 0x1f14);// Device I/O 
+ my_outw(0x03d4, 0x9615);// Device I/O 
+ my_outw(0x03d4, 0xb916);// Device I/O 
+ my_outw(0x03d4, 0xa317);// Device I/O 
+ my_outw(0x03d4, 0xff18);// Device I/O 
+ my_inb(0x03da);// Device I/O --> 31
+ my_inb(0x03ba);// Device I/O --> ff
+ my_inb(0x03da);// Device I/O --> 21
+ my_inb(0x03ba);// Device I/O --> ff
+ my_inb(0x03da);// Device I/O --> 01
+ my_inb(0x03ba);// Device I/O --> ff
+ my_outw(0x03ce, 0x0000);// Device I/O 
+ my_outw(0x03ce, 0x0001);// Device I/O 
+ my_outw(0x03ce, 0x0002);// Device I/O 
+ my_outw(0x03ce, 0x0003);// Device I/O 
+ my_outw(0x03ce, 0x0004);// Device I/O 
+ my_outw(0x03ce, 0x1005);// Device I/O 
+ my_outw(0x03ce, 0x0e06);// Device I/O 
+ my_outw(0x03ce, 0x0007);// Device I/O 
+ my_outw(0x03ce, 0xff08);// Device I/O 
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00010000);// Device I/O 
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00010000
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00010000
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x000e1100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000001
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000001
+ my_outl(0x1044, 0x00000001);// Device I/O 
+ my_outl(0x1040, 0x000e4200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000001c
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00050000
+ my_outl(0x1044, 0x8004003e);// Device I/O 
+ my_outl(0x1040, 0x000e4214);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x80060002);// Device I/O 
+ my_outl(0x1040, 0x000e4218);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x01000000);// Device I/O 
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1044, 0x5344003e);// Device I/O 
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0144003e
+ my_outl(0x1044, 0x8074003e);// Device I/O 
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1044, 0x5344003e);// Device I/O 
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0144003e
+ my_outl(0x1044, 0x8074003e);// Device I/O 
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1044, 0x5344003e);// Device I/O 
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0144003e
+ my_outl(0x1044, 0x8074003e);// Device I/O 
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1040, 0x000e4210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 5144003e
+ my_outl(0x1044, 0x5344003e);// Device I/O 
+ my_outl(0x1040, 0x000e4f00);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0100038e
+ my_outl(0x1044, 0x0100030c);// Device I/O 
+ my_outl(0x1040, 0x000e4f04);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00b8338e
+ my_outl(0x1044, 0x00b8230c);// Device I/O 
+ my_outl(0x1040, 0x000e4f08);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0178838e
+ my_outl(0x1044, 0x06f8930c);// Device I/O 
+ my_outl(0x1040, 0x000e4f0c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 09f8e38e
+ my_outl(0x1044, 0x09f8e38e);// Device I/O 
+ my_outl(0x1040, 0x000e4f10);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00b8038e
+ my_outl(0x1044, 0x00b8030c);// Device I/O 
+ my_outl(0x1040, 0x000e4f14);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0978838e
+ my_outl(0x1044, 0x0b78830c);// Device I/O 
+ my_outl(0x1040, 0x000e4f18);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 09f8b38e
+ my_outl(0x1044, 0x0ff8d3cf);// Device I/O 
+ my_outl(0x1040, 0x000e4f1c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0178038e
+ my_outl(0x1044, 0x01e8030c);// Device I/O 
+ my_outl(0x1040, 0x000e4f20);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 09f8638e
+ my_outl(0x1044, 0x0ff863cf);// Device I/O 
+ my_outl(0x1040, 0x000e4f24);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 09f8038e
+ my_outl(0x1044, 0x0ff803cf);// Device I/O 
+ my_outl(0x1040, 0x000c4030);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00001000);// Device I/O 
+ my_outl(0x1040, 0x000c4000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000c4030);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00001000
+ my_outl(0x1044, 0x00001000);// Device I/O 
+ my_outl(0x1040, 0x000e1150);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000001c
+ my_outl(0x1040, 0x000e1150);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000001c
+ my_outl(0x1044, 0x0000089c);// Device I/O 
+ my_outl(0x1040, 0x000fcc00);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01773f30
+ my_outl(0x1044, 0x01986f00);// Device I/O 
+ my_outl(0x1040, 0x000fcc0c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01773f30
+ my_outl(0x1044, 0x01986f00);// Device I/O 
+ my_outl(0x1040, 0x000fcc18);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01773f30
+ my_outl(0x1044, 0x01986f00);// Device I/O 
+ my_outl(0x1040, 0x000fcc24);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01773f30
+ my_outl(0x1044, 0x01986f00);// Device I/O 
+ my_outl(0x1040, 0x000c4000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 40000002
+ my_inb(0x03d4);// Device I/O --> 18
+ my_inb(0x03d6);// Device I/O --> ff
+ my_inb(0x03d0);// Device I/O --> ff
+ my_inb(0x03ce);// Device I/O --> 08
+ my_inb(0x03d2);// Device I/O --> ff
+ my_inb(0x03c4);// Device I/O --> 00
+ my_inb(0x03c7);// Device I/O --> 00
+ my_inb(0x03c8);// Device I/O --> 00
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outw(0x03c4, 0x2001);// Device I/O 
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000800
+ my_outl(0x1040, 0x000c5100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000003);// Device I/O 
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008800
+ my_outl(0x1040, 0x000c5120);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x000c5104);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x460000a0);// Device I/O 
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000ca00
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000ca00
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000ca00
+ my_outl(0x1040, 0x000c5120);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x000c5104);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 060000a0
+ my_outl(0x1044, 0x4a8000a1);// Device I/O 
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a08
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a08
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> ffffff00
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a0c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a0c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00ffffff
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a10
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a10
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 4011ae30
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a14
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a14
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a18
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a18
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03011300
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a1c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a1c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 78101a80
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a20
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a20
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 9795baea
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a24
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a24
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 278c5559
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a28
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a28
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00545021
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a2c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a2c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01010000
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a30
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a30
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01010101
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a34
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a34
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01010101
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a38
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a38
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01010101
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a3c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a3c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 1b120101
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a40
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a40
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 20508000
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a44
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a44
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 20183014
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a48
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a48
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> a3050044
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a4c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a4c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 1f000010
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a50
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a50
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 80001693
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a54
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a54
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 30142050
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a58
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a58
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00442018
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a5c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a5c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0010a305
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a60
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a60
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00001f00
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a64
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a64
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 81000f00
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a68
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a68
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0a813c0a
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a6c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a6c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00091632
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a70
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a70
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01f0e430
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a74
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a74
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> fe000000
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a78
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a78
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 31504c00
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a7c
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008a7c
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 58573132
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008800
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008800
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 4c542d33
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008800
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008800
+ my_outl(0x1040, 0x000c510c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> ac003143
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008000
+ my_outl(0x1040, 0x000c5104);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 028000a1
+ my_outl(0x1044, 0x480000a0);// Device I/O 
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008000
+ my_outl(0x1040, 0x000c5100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000003
+ my_outl(0x1044, 0x48000000);// Device I/O 
+ my_outl(0x1040, 0x000c5108);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008000
+ my_outl(0x1044, 0x00008000);// Device I/O 
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outw(0x03c4, 0x0001);// Device I/O 
+ my_outb(0x03d4, 0x18);// Device I/O <--
+ my_outb(0x03d6, 0xff);// Device I/O <--
+ my_outb(0x03d0, 0xff);// Device I/O <--
+ my_outb(0x03ce, 0x08);// Device I/O <--
+ my_outb(0x03d2, 0xff);// Device I/O <--
+ my_outb(0x03c4, 0x00);// Device I/O <--
+ my_outb(0x03c8, 0x00);// Device I/O <--
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 40000002
+ my_outl(0x1044, 0x00000300);// Device I/O 
+ my_outl(0x1040, 0x000c7208);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00fa09c4);// Device I/O 
+ my_outl(0x1040, 0x000c720c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00fa09c4);// Device I/O 
+ my_outl(0x1040, 0x000c7210);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00186904
+ my_outl(0x1044, 0x00186903);// Device I/O 
+ my_outl(0x1040, 0x00048250);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x80000000);// Device I/O 
+ my_outl(0x1040, 0x00048254);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x061a061a);// Device I/O 
+ my_outl(0x1040, 0x000c8254);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x061a061a);// Device I/O 
+ my_outl(0x1040, 0x000c8250);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x000c8250);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x80000000);// Device I/O 
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000c4000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000001
+ my_outl(0x1044, 0x0000020d);// Device I/O 
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000020d
+ my_outl(0x1040, 0x0004f050);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f050);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000020d
+ my_outl(0x1044, 0x0000020d);// Device I/O 
+ my_outl(0x1040, 0x0004f050);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0xc0000000);// Device I/O 
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000020d
+ my_outl(0x1040, 0x0004f054);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 0000020d
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000400);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000400
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000400
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c6, 0xff);// Device I/O <--
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1044, 0x03300000);// Device I/O 
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03300000
+ my_outl(0x1044, 0x30300000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 30300000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 30300000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 30300000
+ my_outl(0x1040, 0x0004f048);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 30300000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 30300000
+ my_outl(0x1044, 0x30030000);// Device I/O 
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 30030000
+ my_outl(0x1044, 0x03030000);// Device I/O 
+
+vga_textmode_init ();
+
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000001
+ my_outl(0x1044, 0x01000008);// Device I/O 
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1044, 0x03030000);// Device I/O 
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1044, 0x03030000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00070080);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000700c0);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x0001
+ my_outw(0x03c4, 0x2001);// Device I/O 
+ my_outl(0x1040, 0x00041000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 8000298e
+ my_outl(0x1040, 0x00041000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 8000298e
+ my_outl(0x1044, 0x8000298e);// Device I/O 
+ my_outl(0x1040, 0x00070180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00071180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00068070);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00068080);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00068074);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000400);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000400
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000400
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00041000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 8000298e
+ my_outl(0x1044, 0x8020298e);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outw(0x03ce, 0x0010);// Device I/O 
+ my_outw(0x03ce, 0x0011);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outw(0x03c4, 0x0100);// Device I/O 
+ my_outw(0x03c4, 0x2001);// Device I/O 
+ my_outw(0x03c4, 0x0302);// Device I/O 
+ my_outw(0x03c4, 0x0003);// Device I/O 
+ my_outw(0x03c4, 0x0204);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outw(0x03c4, 0x0300);// Device I/O 
+ my_outb(0x03c2, 0x67);// Device I/O <--
+ my_outb(0x03d4, 0x11);// Device I/O <--
+ my_inw(0x03d4);// Device I/O --> 0x8e11
+ my_outw(0x03d4, 0x0e11);// Device I/O 
+ my_outw(0x03d4, 0x5f00);// Device I/O 
+ my_outw(0x03d4, 0x4f01);// Device I/O 
+ my_outw(0x03d4, 0x5002);// Device I/O 
+ my_outw(0x03d4, 0x8203);// Device I/O 
+ my_outw(0x03d4, 0x5504);// Device I/O 
+ my_outw(0x03d4, 0x8105);// Device I/O 
+ my_outw(0x03d4, 0xbf06);// Device I/O 
+ my_outw(0x03d4, 0x1f07);// Device I/O 
+ my_outw(0x03d4, 0x0008);// Device I/O 
+ my_outw(0x03d4, 0x4f09);// Device I/O 
+ my_outw(0x03d4, 0x0d0a);// Device I/O 
+ my_outw(0x03d4, 0x0e0b);// Device I/O 
+ my_outw(0x03d4, 0x000c);// Device I/O 
+ my_outw(0x03d4, 0x000d);// Device I/O 
+ my_outw(0x03d4, 0x000e);// Device I/O 
+ my_outw(0x03d4, 0x000f);// Device I/O 
+ my_outw(0x03d4, 0x9c10);// Device I/O 
+ my_outw(0x03d4, 0x8e11);// Device I/O 
+ my_outw(0x03d4, 0x8f12);// Device I/O 
+ my_outw(0x03d4, 0x2813);// Device I/O 
+ my_outw(0x03d4, 0x1f14);// Device I/O 
+ my_outw(0x03d4, 0x9615);// Device I/O 
+ my_outw(0x03d4, 0xb916);// Device I/O 
+ my_outw(0x03d4, 0xa317);// Device I/O 
+ my_outw(0x03d4, 0xff18);// Device I/O 
+ my_inb(0x03da);// Device I/O --> 01
+ my_inb(0x03ba);// Device I/O --> ff
+ my_inb(0x03da);// Device I/O --> 21
+ my_inb(0x03ba);// Device I/O --> ff
+ my_inb(0x03da);// Device I/O --> 01
+ my_inb(0x03ba);// Device I/O --> ff
+ my_outw(0x03ce, 0x0000);// Device I/O 
+ my_outw(0x03ce, 0x0001);// Device I/O 
+ my_outw(0x03ce, 0x0002);// Device I/O 
+ my_outw(0x03ce, 0x0003);// Device I/O 
+ my_outw(0x03ce, 0x0004);// Device I/O 
+ my_outw(0x03ce, 0x1005);// Device I/O 
+ my_outw(0x03ce, 0x0e06);// Device I/O 
+ my_outw(0x03ce, 0x0007);// Device I/O 
+ my_outw(0x03ce, 0xff08);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c6, 0xff);// Device I/O <--
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ vga_textmode_init ();
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f050);// Device I/O 
+ my_inl(0x1044);// Device I/O --> c0000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03ce, 0x06);// Device I/O <--
+ my_inw(0x03ce);// Device I/O --> 0x0e06
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00041000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 8020298e
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000302
+ my_outl(0x1044, 0x00008302);// Device I/O 
+ my_outl(0x1040, 0x00048250);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 80000000
+ my_outl(0x1044, 0x80000000);// Device I/O 
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008302
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008302
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008302
+ my_outl(0x1040, 0x000c6200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00001000);// Device I/O 
+ my_outl(0x1040, 0x000c6200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00001000
+ my_outl(0x1044, 0x00001002);// Device I/O 
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0xabcd0000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f00c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000c6040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00030d07
+ my_outl(0x1044, 0x00021005);// Device I/O 
+ my_outl(0x1040, 0x000c6014);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 04800080
+ my_outl(0x1044, 0x88046004);// Device I/O 
+ my_outl(0x1040, 0x000c6014);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 88046004
+ my_outl(0x1044, 0x88046004);// Device I/O 
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> abcd0000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008302
+ my_outl(0x1044, 0x00008302);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x057f04ff);// Device I/O 
+ my_outl(0x1040, 0x00060004);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x057f04ff);// Device I/O 
+ my_outl(0x1040, 0x00060008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x05370517);// Device I/O 
+ my_outl(0x1040, 0x0006000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x0333031f);// Device I/O 
+ my_outl(0x1040, 0x00060010);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x0333031f);// Device I/O 
+ my_outl(0x1040, 0x00060014);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x03270323);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outl(0x1040, 0x0006001c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x02cf018f);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00070008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f050);// Device I/O 
+ my_inl(0x1044);// Device I/O --> c0000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03ce, 0x06);// Device I/O <--
+ my_inw(0x03ce);// Device I/O --> 0x0e06
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outb(0x03c4, 0x01);// Device I/O <--
+ my_inw(0x03c4);// Device I/O --> 0x2001
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0006001c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 02cf018f
+ my_outl(0x1044, 0x027f018f);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00068080);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x80800000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00068070);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00068074);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x05000320);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00070008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00070008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060030);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x7e127ae1);// Device I/O 
+ my_outl(0x1040, 0x00060034);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00800000);// Device I/O 
+ my_outl(0x1040, 0x00060040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00020da7);// Device I/O 
+ my_outl(0x1040, 0x00060044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00080000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000040
+ my_outl(0x1044, 0x00002040);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00002040
+ my_outl(0x1044, 0x00002050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00044000
+ my_outl(0x1044, 0x00044000);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00070008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000040);// Device I/O 
+ my_outl(0x1040, 0x000f0008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000040);// Device I/O 
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00002050
+ my_outl(0x1044, 0x00022050);// Device I/O 
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00070008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000040
+ my_outl(0x1044, 0x00000050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00070008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000050
+ my_outl(0x1044, 0x80000050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x00041000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 8020298e
+ my_outl(0x1044, 0x0020298e);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000080);// Device I/O 
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f0018);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 000007ff
+ my_outl(0x1044, 0x000000ff);// Device I/O 
+ my_outl(0x1040, 0x000f1018);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 000007ff
+ my_outl(0x1044, 0x000000ff);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00022050
+ my_outl(0x1044, 0x001a2050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00044000
+ my_outl(0x1044, 0x001c4000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 001c4000
+ my_outl(0x1044, 0x801c4000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 001a2050
+ my_outl(0x1044, 0x801a2050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 801c4000
+ my_outl(0x1044, 0x801c4000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 801a2050
+ my_outl(0x1044, 0x801a2050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f0014);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000100
+ my_outl(0x1040, 0x000f0014);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000100
+ my_outl(0x1044, 0x00000100);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 801c4000
+ my_outl(0x1044, 0x901c4000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 801a2050
+ my_outl(0x1044, 0x901a2050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f0014);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000600
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000e0000);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x057f04ff);// Device I/O 
+ my_outl(0x1040, 0x000e0004);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x057f04ff);// Device I/O 
+ my_outl(0x1040, 0x000e0008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x05370517);// Device I/O 
+ my_outl(0x1040, 0x000e000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x0333031f);// Device I/O 
+ my_outl(0x1040, 0x000e0010);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x0333031f);// Device I/O 
+ my_outl(0x1040, 0x000e0014);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x03270323);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00060100);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 901c4000
+ my_outl(0x1044, 0xb01c4000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f000c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 901a2050
+ my_outl(0x1044, 0xb01a2050);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000f0008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000040
+ my_outl(0x1044, 0x80000040);// Device I/O 
+ my_outl(0x1040, 0x000e1180);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00008302
+ my_outl(0x1044, 0x80008302);// Device I/O 
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0xabcd0000);// Device I/O 
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> abcd0000
+ my_outl(0x1044, 0xabcd0002);// Device I/O 
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> abcd0002
+ my_outl(0x1044, 0xabcd0003);// Device I/O 
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d000000a
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> d0000009
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> c0000008
+ my_outl(0x1040, 0x000c7200);// Device I/O 
+ my_inl(0x1044);// Device I/O --> c0000008
+ my_outl(0x1040, 0x000c7204);// Device I/O 
+ my_inl(0x1044);// Device I/O --> abcd0003
+ my_outl(0x1044, 0x00000003);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f040);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 01000008
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000400);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000400
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000400
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x0004f044);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x0004f04c);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 03030000
+ my_outl(0x1040, 0x000c4030);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00001000
+ my_outl(0x1040, 0x000c4030);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00001000
+ my_outl(0x1044, 0x00001000);// Device I/O 
+ my_outl(0x1040, 0x000c4008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x000c4008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x000c4008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1040, 0x00044008);// Device I/O 
+ my_inl(0x1044);// Device I/O --> 00000000
+ my_outl(0x1044, 0x00000000);// Device I/O 
diff --git a/src/northbridge/intel/calpella/finalize.c b/src/northbridge/intel/calpella/finalize.c
new file mode 100644
index 0000000..3b51b1e
--- /dev/null
+++ b/src/northbridge/intel/calpella/finalize.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <stdlib.h>
+#include "pcie_config.c"
+#include "calpella.h"
+
+#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
+
+void intel_sandybridge_finalize_smm(void)
+{
+	pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0);	/* GGC */
+	pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0);	/* DPR */
+	pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10);	/* ME */
+	pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0);	/* REMAPBASE */
+	pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0);	/* REMAPLIMIT */
+	pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0);	/* TOM */
+	pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0);	/* TOUUD */
+	pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0);	/* BDSM */
+	pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0);	/* BGSM */
+	pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0);	/* TSEGMB */
+	pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0);	/* TOLUD */
+
+	MCHBAR32_OR(0x5500, 1 << 0);	/* PAVP */
+	MCHBAR32_OR(0x5f00, 1 << 31);	/* SA PM */
+	MCHBAR32_OR(0x6020, 1 << 0);	/* UMA GFX */
+	MCHBAR32_OR(0x63fc, 1 << 0);	/* VTDTRK */
+	MCHBAR32_OR(0x6800, 1 << 31);
+	MCHBAR32_OR(0x7000, 1 << 31);
+	MCHBAR32_OR(0x77fc, 1 << 0);
+
+	/* Memory Controller Lockdown */
+	MCHBAR8(0x50fc) = 0x8f;
+
+	/* Read+write the following */
+	MCHBAR32(0x6030) = MCHBAR32(0x6030);
+	MCHBAR32(0x6034) = MCHBAR32(0x6034);
+	MCHBAR32(0x6008) = MCHBAR32(0x6008);
+}
diff --git a/src/northbridge/intel/calpella/gma.c b/src/northbridge/intel/calpella/gma.c
new file mode 100644
index 0000000..b07f40f
--- /dev/null
+++ b/src/northbridge/intel/calpella/gma.c
@@ -0,0 +1,1049 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+#include "chip.h"
+#include "calpella.h"
+
+struct gt_powermeter {
+	u16 reg;
+	u32 value;
+};
+
+static const struct gt_powermeter snb_pm_gt1[] = {
+	{ 0xa200, 0xcc000000 },
+	{ 0xa204, 0x07000040 },
+	{ 0xa208, 0x0000fe00 },
+	{ 0xa20c, 0x00000000 },
+	{ 0xa210, 0x17000000 },
+	{ 0xa214, 0x00000021 },
+	{ 0xa218, 0x0817fe19 },
+	{ 0xa21c, 0x00000000 },
+	{ 0xa220, 0x00000000 },
+	{ 0xa224, 0xcc000000 },
+	{ 0xa228, 0x07000040 },
+	{ 0xa22c, 0x0000fe00 },
+	{ 0xa230, 0x00000000 },
+	{ 0xa234, 0x17000000 },
+	{ 0xa238, 0x00000021 },
+	{ 0xa23c, 0x0817fe19 },
+	{ 0xa240, 0x00000000 },
+	{ 0xa244, 0x00000000 },
+	{ 0xa248, 0x8000421e },
+	{ 0 }
+};
+
+static const struct gt_powermeter snb_pm_gt2[] = {
+	{ 0xa200, 0x330000a6 },
+	{ 0xa204, 0x402d0031 },
+	{ 0xa208, 0x00165f83 },
+	{ 0xa20c, 0xf1000000 },
+	{ 0xa210, 0x00000000 },
+	{ 0xa214, 0x00160016 },
+	{ 0xa218, 0x002a002b },
+	{ 0xa21c, 0x00000000 },
+	{ 0xa220, 0x00000000 },
+	{ 0xa224, 0x330000a6 },
+	{ 0xa228, 0x402d0031 },
+	{ 0xa22c, 0x00165f83 },
+	{ 0xa230, 0xf1000000 },
+	{ 0xa234, 0x00000000 },
+	{ 0xa238, 0x00160016 },
+	{ 0xa23c, 0x002a002b },
+	{ 0xa240, 0x00000000 },
+	{ 0xa244, 0x00000000 },
+	{ 0xa248, 0x8000421e },
+	{ 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt1[] = {
+	{ 0xa800, 0x00000000 },
+	{ 0xa804, 0x00021c00 },
+	{ 0xa808, 0x00000403 },
+	{ 0xa80c, 0x02001700 },
+	{ 0xa810, 0x05000200 },
+	{ 0xa814, 0x00000000 },
+	{ 0xa818, 0x00690500 },
+	{ 0xa81c, 0x0000007f },
+	{ 0xa820, 0x01002501 },
+	{ 0xa824, 0x00000300 },
+	{ 0xa828, 0x01000331 },
+	{ 0xa82c, 0x0000000c },
+	{ 0xa830, 0x00010016 },
+	{ 0xa834, 0x01100101 },
+	{ 0xa838, 0x00010103 },
+	{ 0xa83c, 0x00041300 },
+	{ 0xa840, 0x00000b30 },
+	{ 0xa844, 0x00000000 },
+	{ 0xa848, 0x7f000000 },
+	{ 0xa84c, 0x05000008 },
+	{ 0xa850, 0x00000001 },
+	{ 0xa854, 0x00000004 },
+	{ 0xa858, 0x00000007 },
+	{ 0xa85c, 0x00000000 },
+	{ 0xa860, 0x00010000 },
+	{ 0xa248, 0x0000221e },
+	{ 0xa900, 0x00000000 },
+	{ 0xa904, 0x00001c00 },
+	{ 0xa908, 0x00000000 },
+	{ 0xa90c, 0x06000000 },
+	{ 0xa910, 0x09000200 },
+	{ 0xa914, 0x00000000 },
+	{ 0xa918, 0x00590000 },
+	{ 0xa91c, 0x00000000 },
+	{ 0xa920, 0x04002501 },
+	{ 0xa924, 0x00000100 },
+	{ 0xa928, 0x03000410 },
+	{ 0xa92c, 0x00000000 },
+	{ 0xa930, 0x00020000 },
+	{ 0xa934, 0x02070106 },
+	{ 0xa938, 0x00010100 },
+	{ 0xa93c, 0x00401c00 },
+	{ 0xa940, 0x00000000 },
+	{ 0xa944, 0x00000000 },
+	{ 0xa948, 0x10000e00 },
+	{ 0xa94c, 0x02000004 },
+	{ 0xa950, 0x00000001 },
+	{ 0xa954, 0x00000004 },
+	{ 0xa960, 0x00060000 },
+	{ 0xaa3c, 0x00001c00 },
+	{ 0xaa54, 0x00000004 },
+	{ 0xaa60, 0x00060000 },
+	{ 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2[] = {
+	{ 0xa800, 0x10000000 },
+	{ 0xa804, 0x00033800 },
+	{ 0xa808, 0x00000902 },
+	{ 0xa80c, 0x0c002f00 },
+	{ 0xa810, 0x12000400 },
+	{ 0xa814, 0x00000000 },
+	{ 0xa818, 0x00d20800 },
+	{ 0xa81c, 0x00000002 },
+	{ 0xa820, 0x03004b02 },
+	{ 0xa824, 0x00000600 },
+	{ 0xa828, 0x07000773 },
+	{ 0xa82c, 0x00000000 },
+	{ 0xa830, 0x00010032 },
+	{ 0xa834, 0x1520040d },
+	{ 0xa838, 0x00020105 },
+	{ 0xa83c, 0x00083700 },
+	{ 0xa840, 0x0000151d },
+	{ 0xa844, 0x00000000 },
+	{ 0xa848, 0x20001b00 },
+	{ 0xa84c, 0x0a000010 },
+	{ 0xa850, 0x00000000 },
+	{ 0xa854, 0x00000008 },
+	{ 0xa858, 0x00000008 },
+	{ 0xa85c, 0x00000000 },
+	{ 0xa860, 0x00020000 },
+	{ 0xa248, 0x0000221e },
+	{ 0xa900, 0x00000000 },
+	{ 0xa904, 0x00003500 },
+	{ 0xa908, 0x00000000 },
+	{ 0xa90c, 0x0c000000 },
+	{ 0xa910, 0x12000500 },
+	{ 0xa914, 0x00000000 },
+	{ 0xa918, 0x00b20000 },
+	{ 0xa91c, 0x00000000 },
+	{ 0xa920, 0x08004b02 },
+	{ 0xa924, 0x00000200 },
+	{ 0xa928, 0x07000820 },
+	{ 0xa92c, 0x00000000 },
+	{ 0xa930, 0x00030000 },
+	{ 0xa934, 0x050f020d },
+	{ 0xa938, 0x00020300 },
+	{ 0xa93c, 0x00903900 },
+	{ 0xa940, 0x00000000 },
+	{ 0xa944, 0x00000000 },
+	{ 0xa948, 0x20001b00 },
+	{ 0xa94c, 0x0a000010 },
+	{ 0xa950, 0x00000000 },
+	{ 0xa954, 0x00000008 },
+	{ 0xa960, 0x00110000 },
+	{ 0xaa3c, 0x00003900 },
+	{ 0xaa54, 0x00000008 },
+	{ 0xaa60, 0x00110000 },
+	{ 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_17w[] = {
+	{ 0xa800, 0x20000000 },
+	{ 0xa804, 0x000e3800 },
+	{ 0xa808, 0x00000806 },
+	{ 0xa80c, 0x0c002f00 },
+	{ 0xa810, 0x0c000800 },
+	{ 0xa814, 0x00000000 },
+	{ 0xa818, 0x00d20d00 },
+	{ 0xa81c, 0x000000ff },
+	{ 0xa820, 0x03004b02 },
+	{ 0xa824, 0x00000600 },
+	{ 0xa828, 0x07000773 },
+	{ 0xa82c, 0x00000000 },
+	{ 0xa830, 0x00020032 },
+	{ 0xa834, 0x1520040d },
+	{ 0xa838, 0x00020105 },
+	{ 0xa83c, 0x00083700 },
+	{ 0xa840, 0x000016ff },
+	{ 0xa844, 0x00000000 },
+	{ 0xa848, 0xff000000 },
+	{ 0xa84c, 0x0a000010 },
+	{ 0xa850, 0x00000002 },
+	{ 0xa854, 0x00000008 },
+	{ 0xa858, 0x0000000f },
+	{ 0xa85c, 0x00000000 },
+	{ 0xa860, 0x00020000 },
+	{ 0xa248, 0x0000221e },
+	{ 0xa900, 0x00000000 },
+	{ 0xa904, 0x00003800 },
+	{ 0xa908, 0x00000000 },
+	{ 0xa90c, 0x0c000000 },
+	{ 0xa910, 0x12000800 },
+	{ 0xa914, 0x00000000 },
+	{ 0xa918, 0x00b20000 },
+	{ 0xa91c, 0x00000000 },
+	{ 0xa920, 0x08004b02 },
+	{ 0xa924, 0x00000300 },
+	{ 0xa928, 0x01000820 },
+	{ 0xa92c, 0x00000000 },
+	{ 0xa930, 0x00030000 },
+	{ 0xa934, 0x15150406 },
+	{ 0xa938, 0x00020300 },
+	{ 0xa93c, 0x00903900 },
+	{ 0xa940, 0x00000000 },
+	{ 0xa944, 0x00000000 },
+	{ 0xa948, 0x20001b00 },
+	{ 0xa94c, 0x0a000010 },
+	{ 0xa950, 0x00000000 },
+	{ 0xa954, 0x00000008 },
+	{ 0xa960, 0x00110000 },
+	{ 0xaa3c, 0x00003900 },
+	{ 0xaa54, 0x00000008 },
+	{ 0xaa60, 0x00110000 },
+	{ 0 }
+};
+
+static const struct gt_powermeter ivb_pm_gt2_35w[] = {
+	{ 0xa800, 0x00000000 },
+	{ 0xa804, 0x00030400 },
+	{ 0xa808, 0x00000806 },
+	{ 0xa80c, 0x0c002f00 },
+	{ 0xa810, 0x0c000300 },
+	{ 0xa814, 0x00000000 },
+	{ 0xa818, 0x00d20d00 },
+	{ 0xa81c, 0x000000ff },
+	{ 0xa820, 0x03004b02 },
+	{ 0xa824, 0x00000600 },
+	{ 0xa828, 0x07000773 },
+	{ 0xa82c, 0x00000000 },
+	{ 0xa830, 0x00020032 },
+	{ 0xa834, 0x1520040d },
+	{ 0xa838, 0x00020105 },
+	{ 0xa83c, 0x00083700 },
+	{ 0xa840, 0x000016ff },
+	{ 0xa844, 0x00000000 },
+	{ 0xa848, 0xff000000 },
+	{ 0xa84c, 0x0a000010 },
+	{ 0xa850, 0x00000001 },
+	{ 0xa854, 0x00000008 },
+	{ 0xa858, 0x00000008 },
+	{ 0xa85c, 0x00000000 },
+	{ 0xa860, 0x00020000 },
+	{ 0xa248, 0x0000221e },
+	{ 0xa900, 0x00000000 },
+	{ 0xa904, 0x00003800 },
+	{ 0xa908, 0x00000000 },
+	{ 0xa90c, 0x0c000000 },
+	{ 0xa910, 0x12000800 },
+	{ 0xa914, 0x00000000 },
+	{ 0xa918, 0x00b20000 },
+	{ 0xa91c, 0x00000000 },
+	{ 0xa920, 0x08004b02 },
+	{ 0xa924, 0x00000300 },
+	{ 0xa928, 0x01000820 },
+	{ 0xa92c, 0x00000000 },
+	{ 0xa930, 0x00030000 },
+	{ 0xa934, 0x15150406 },
+	{ 0xa938, 0x00020300 },
+	{ 0xa93c, 0x00903900 },
+	{ 0xa940, 0x00000000 },
+	{ 0xa944, 0x00000000 },
+	{ 0xa948, 0x20001b00 },
+	{ 0xa94c, 0x0a000010 },
+	{ 0xa950, 0x00000000 },
+	{ 0xa954, 0x00000008 },
+	{ 0xa960, 0x00110000 },
+	{ 0xaa3c, 0x00003900 },
+	{ 0xaa54, 0x00000008 },
+	{ 0xaa60, 0x00110000 },
+	{ 0 }
+};
+
+/* some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselfes
+ */
+
+u32 map_oprom_vendev(u32 vendev)
+{
+	u32 new_vendev=vendev;
+
+	switch (vendev) {
+	case 0x80860102:		/* GT1 Desktop */
+	case 0x8086010a:		/* GT1 Server */
+	case 0x80860112:		/* GT2 Desktop */
+	case 0x80860116:		/* GT2 Mobile */
+	case 0x80860122:		/* GT2 Desktop >=1.3GHz */
+	case 0x80860126:		/* GT2 Mobile >=1.3GHz */
+	case 0x80860156:                /* IVB */
+	case 0x80860166:                /* IVB */
+		new_vendev=0x80860106;	/* GT1 Mobile */
+		break;
+	}
+
+	return new_vendev;
+}
+
+static struct resource *gtt_res = NULL;
+
+static inline u32 gtt_read(u32 reg)
+{
+	return read32(gtt_res->base + reg);
+}
+
+static inline void gtt_write(u32 reg, u32 data)
+{
+	write32(gtt_res->base + reg, data);
+}
+
+static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
+{
+	for (; pm && pm->reg; pm++)
+		gtt_write(pm->reg, pm->value);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(u32 reg, u32 mask, u32 value)
+{
+	unsigned try = GTT_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = gtt_read(reg);
+		if ((data & mask) == value)
+			return 1;
+		udelay(10);
+	}
+
+	printk(BIOS_ERR, "GT init timeout\n");
+	return 0;
+}
+
+static void gma_pm_init_pre_vbios(struct device *dev)
+{
+	u32 reg32;
+
+	printk(BIOS_DEBUG, "GT Power Management Init\n");
+
+	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!gtt_res || !gtt_res->base)
+		return;
+
+	if (bridge_silicon_revision() < IVB_STEP_C0) {
+		/* 1: Enable force wake */
+		gtt_write(0xa18c, 0x00000001);
+		gtt_poll(0x130090, (1 << 0), (1 << 0));
+	} else {
+		gtt_write(0xa180, 1 << 5);
+		gtt_write(0xa188, 0xffff0001);
+		gtt_poll(0x130040, (1 << 0), (1 << 0));
+	}
+
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+		reg32 = gtt_read(0x42004);
+		reg32 |= (1 << 14) | (1 << 15);
+		gtt_write(0x42004, reg32);
+	}
+
+	if (bridge_silicon_revision() >= IVB_STEP_A0) {
+		/* Display Reset Acknowledge Settings */
+		reg32 = gtt_read(0x45010);
+		reg32 |= (1 << 1) | (1 << 0);
+		gtt_write(0x45010, reg32);
+	}
+
+	/* 2: Get GT SKU from GTT+0x911c[13] */
+	reg32 = gtt_read(0x911c);
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		if (reg32 & (1 << 13)) {
+			printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n");
+			gtt_write_powermeter(snb_pm_gt1);
+		} else {
+			printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n");
+			gtt_write_powermeter(snb_pm_gt2);
+		}
+	} else {
+		u32 unit = MCHBAR32(0x5938) & 0xf;
+
+		if (reg32 & (1 << 13)) {
+			/* GT1 SKU */
+			printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n");
+			gtt_write_powermeter(ivb_pm_gt1);
+		} else {
+			/* GT2 SKU */
+			u32 tdp = MCHBAR32(0x5930) & 0x7fff;
+			tdp /= (1 << unit);
+
+			if (tdp <= 17) {
+				/* <=17W ULV */
+				printk(BIOS_DEBUG, "IVB GT2 17W "
+				       "Power Meter Weights\n");
+				gtt_write_powermeter(ivb_pm_gt2_17w);
+			} else if ((tdp >= 25) && (tdp <= 35)) {
+				/* 25W-35W */
+				printk(BIOS_DEBUG, "IVB GT2 25W-35W "
+				       "Power Meter Weights\n");
+				gtt_write_powermeter(ivb_pm_gt2_35w);
+			} else {
+				/* All others */
+				printk(BIOS_DEBUG, "IVB GT2 35W "
+				       "Power Meter Weights\n");
+				gtt_write_powermeter(ivb_pm_gt2_35w);
+			}
+		}
+	}
+
+	/* 3: Gear ratio map */
+	gtt_write(0xa004, 0x00000010);
+
+	/* 4: GFXPAUSE */
+	gtt_write(0xa000, 0x00070020);
+
+	/* 5: Dynamic EU trip control */
+	gtt_write(0xa080, 0x00000004);
+
+	/* 6: ECO bits */
+	reg32 = gtt_read(0xa180);
+	reg32 |= (1 << 26) | (1 << 31);
+	/* (bit 20=1 for SNB step D1+ / IVB A0+) */
+	if (bridge_silicon_revision() >= SNB_STEP_D1)
+		reg32 |= (1 << 20);
+	gtt_write(0xa180, reg32);
+
+	/* 6a: for SnB step D2+ only */
+	if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
+		(bridge_silicon_revision() >= SNB_STEP_D2)) {
+		reg32 = gtt_read(0x9400);
+		reg32 |= (1 << 7);
+		gtt_write(0x9400, reg32);
+
+		reg32 = gtt_read(0x941c);
+		reg32 &= 0xf;
+		reg32 |= (1 << 1);
+		gtt_write(0x941c, reg32);
+		gtt_poll(0x941c, (1 << 1), (0 << 1));
+	}
+
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+		reg32 = gtt_read(0x907c);
+		reg32 |= (1 << 16);
+		gtt_write(0x907c, reg32);
+
+		/* 6b: Clocking reset controls */
+		gtt_write(0x9424, 0x00000001);
+	} else {
+		/* 6b: Clocking reset controls */
+		gtt_write(0x9424, 0x00000000);
+	}
+
+	/* 7 */
+	if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
+		gtt_write(0x138128, 0x00000029); /* Mailbox Data */
+		gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
+		if (gtt_poll(0x138124, (1 << 31), (0 << 31)))
+			gtt_write(0x138124, 0x8000000a);
+		gtt_poll(0x138124, (1 << 31), (0 << 31));
+	}
+
+	/* 8 */
+	gtt_write(0xa090, 0x00000000); /* RC Control */
+	gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+	gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+	gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+	gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+	gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+	/* 9 */
+	gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */
+	gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */
+	gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */
+
+	/* 10 */
+	gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+	gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */
+	gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */
+	gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */
+	gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+	/* 11 */
+	gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */
+	gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */
+	gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */
+	gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */
+	gtt_write(0xa068, 0x000186a0); /* RP Up EI */
+	gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
+	gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+	/* 11a: Enable Render Standby (RC6) */
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+		/*
+		 * IvyBridge should also support DeepRenderStandby.
+		 *
+		 * Unfortunately it does not work reliably on all SKUs so
+		 * disable it here and it can be enabled by the kernel.
+		 */
+		gtt_write(0xa090, 0x88040000); /* HW RC Control */
+	} else {
+		gtt_write(0xa090, 0x88040000); /* HW RC Control */
+	}
+
+	/* 12: Normal Frequency Request */
+	/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+	reg32 = MCHBAR32(0x5998);
+	reg32 >>= 16;
+	reg32 &= 0xef;
+	reg32 <<= 25;
+	gtt_write(0xa008, reg32);
+
+	/* 13: RP Control */
+	gtt_write(0xa024, 0x00000592);
+
+	/* 14: Enable PM Interrupts */
+	gtt_write(0x4402c, 0x03000076);
+
+	/* Clear 0x6c024 [8:6] */
+	reg32 = gtt_read(0x6c024);
+	reg32 &= ~0x000001c0;
+	gtt_write(0x6c024, reg32);
+}
+
+#if 1
+
+static u8 my_inb(u16 addr)
+{
+	u8 val;
+
+	val = inb(addr);
+
+	return val;
+}
+
+static u16 my_inw(u16 addr)
+{
+	u16 val;
+
+	val = inw(addr);
+
+	return val;
+}
+
+static u32 my_inl(u16 addr)
+{
+	u32 val;
+
+	val = inl(addr);
+
+	return val;
+}
+
+static void my_outb(u16 addr, u8 val)
+{
+	outb(val, addr);
+}
+
+static void my_outw(u16 addr, u16 val)
+{
+	outw(val, addr);
+}
+
+static void my_outl(u16 addr, u32 val)
+{
+	outl(val, addr);
+}
+#endif
+
+#include <pc80/vga.h>
+#include <pc80/vga_io.h>
+
+static void
+fake_vbios (void)
+{
+#include "fake_vbios.c"
+}
+
+static unsigned char fake_vbt[] =
+{
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+};
+
+
+static void gma_pm_init_post_vbios(struct device *dev)
+{
+	struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
+	u32 reg32;
+
+	/* Linux relies on VBT for panel info.  */
+	if (read16 (0xc0000) != 0xaa55)
+	  {
+	    optionrom_header_t *oh = (void *) 0xc0000;
+	    optionrom_pcir_t *pcir;
+	    int sz;
+
+	    memset (oh->reserved, 0, 8192);
+
+	    sz = (0x80 + sizeof (fake_vbt) + 511) / 512;
+	    oh->signature = 0xaa55;
+	    oh->size = sz;
+	    oh->pcir_offset = 0x40;
+	    oh->vbt_offset = 0x80;
+
+	    pcir = (void *) 0xc0040;
+	    pcir->signature = 0x52494350; // PCIR
+	    pcir->vendor = dev->vendor;
+	    pcir->device = dev->device;
+	    pcir->length = sizeof (*pcir);
+	    pcir->revision = dev->class;
+	    pcir->classcode[0] = dev->class >> 8; 
+	    pcir->classcode[1] = dev->class >> 16; 
+	    pcir->classcode[2] = dev->class >> 24; 
+	    pcir->imagelength = sz;
+	    pcir->indicator = 0x80;
+	    
+	    memcpy ((void *) 0xc0080, fake_vbt, sizeof (fake_vbt));
+	  }
+
+	if (1)
+	  fake_vbios ();
+
+	printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
+
+	/* 15: Deassert Force Wake */
+	if (bridge_silicon_revision() < IVB_STEP_C0) {
+		gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
+		gtt_poll(0x130090, (1 << 0), (0 << 0));
+	} else {
+		gtt_write(0xa188, 0x1fffe);
+		if (gtt_poll(0x130040, (1 << 0), (0 << 0)))
+			gtt_write(0xa188, gtt_read(0xa188) | 1);
+	}
+
+	/* 16: SW RC Control */
+	gtt_write(0xa094, 0x00060000);
+
+	/* Setup Digital Port Hotplug */
+	reg32 = gtt_read(0xc4030);
+	if (!reg32) {
+		reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
+		reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
+		reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
+		gtt_write(0xc4030, reg32);
+	}
+
+	/* Setup Panel Power On Delays */
+	reg32 = gtt_read(0xc7208);
+	if (!reg32) {
+		reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
+		reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
+		reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
+		gtt_write(0xc7208, reg32);
+	}
+
+	/* Setup Panel Power Off Delays */
+	reg32 = gtt_read(0xc720c);
+	if (!reg32) {
+		reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
+		reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
+		gtt_write(0xc720c, reg32);
+	}
+
+	/* Setup Panel Power Cycle Delay */
+	if (conf->gpu_panel_power_cycle_delay) {
+		reg32 = gtt_read(0xc7210);
+		reg32 &= ~0xff;
+		reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
+		gtt_write(0xc7210, reg32);
+	}
+
+	/* Enable Backlight if needed */
+	if (conf->gpu_cpu_backlight) {
+		gtt_write(0x48250, (1 << 31));
+		gtt_write(0x48254, conf->gpu_cpu_backlight);
+	}
+	if (conf->gpu_pch_backlight) {
+		gtt_write(0xc8250, (1 << 31));
+		gtt_write(0xc8254, conf->gpu_pch_backlight);
+	}
+}
+
+static void gma_func0_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* IGD needs to be Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Init graphics power management */
+	gma_pm_init_pre_vbios(dev);
+
+#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+	/* PCI Init, will run VBIOS */
+	pci_dev_init(dev);
+#endif
+
+	/* Post VBIOS init */
+	gma_pm_init_post_vbios(dev);
+
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+	/* This should probably run before post VBIOS init. */
+	printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
+	u32 iobase, mmiobase, physbase, graphics_base;
+	iobase = dev->resource_list[2].base;
+	mmiobase = dev->resource_list[0].base;
+	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+	graphics_base = dev->resource_list[1].base;
+
+	int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
+	i915lightup(physbase, iobase, mmiobase, graphics_base);
+#endif
+}
+
+static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static void gma_read_resources(struct device *dev)
+{
+	pci_dev_read_resources(dev);
+
+#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
+	struct resource *res;
+
+	/* Set the graphics memory to write combining. */
+	res = find_resource(dev, PCI_BASE_ADDRESS_2);
+	if (res == NULL) {
+		printk(BIOS_DEBUG, "gma: memory resource not found.\n");
+		return;
+	}
+	res->flags |= IORESOURCE_WRCOMB;
+#endif
+}
+
+static struct pci_operations gma_pci_ops = {
+	.set_subsystem    = gma_set_subsystem,
+};
+
+static struct device_operations gma_func0_ops = {
+	.read_resources		= gma_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= gma_func0_init,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= &gma_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x0046, 0x0102, 0x0106, 0x010a, 0x0112,
+						 0x0116, 0x0122, 0x0126, 0x0156,
+						 0x0166,
+						 0 };
+
+static const struct pci_driver gma __pci_driver = {
+	.ops	 = &gma_func0_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
diff --git a/src/northbridge/intel/calpella/gma.h b/src/northbridge/intel/calpella/gma.h
new file mode 100644
index 0000000..bfa43ef
--- /dev/null
+++ b/src/northbridge/intel/calpella/gma.h
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mailbox 0: header */
+typedef struct {
+	u8	signature[16];
+	u32	size;
+	u32	version;
+	u8	sbios_version[32];
+	u8	vbios_version[16];
+	u8	driver_version[16];
+	u32	mailboxes;
+	u8	reserved[164];
+} __attribute__((packed)) opregion_header_t;
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION  2
+
+#define IGD_MBOX1	(1 << 0)
+#define IGD_MBOX2	(1 << 1)
+#define IGD_MBOX3	(1 << 2)
+#define IGD_MBOX4	(1 << 3)
+#define IGD_MBOX5	(1 << 4)
+
+#define MAILBOXES_MOBILE  (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+			   IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+typedef struct {
+	u32	drdy;
+	u32	csts;
+	u32	cevt;
+	u8	reserved1[20];
+	u32	didl[8];
+	u32	cpdl[8];
+	u32	cadl[8];
+	u32	nadl[8];
+	u32	aslp;
+	u32	tidx;
+	u32	chpd;
+	u32	clid;
+	u32	cdck;
+	u32	sxsw;
+	u32	evts;
+	u32	cnot;
+	u32	nrdy;
+	u8	reserved2[60];
+} __attribute__((packed)) opregion_mailbox1_t;
+
+/* mailbox 2: software sci interface */
+typedef struct {
+	u32	scic;
+	u32	parm;
+	u32	dslp;
+	u8	reserved[244];
+} __attribute__((packed)) opregion_mailbox2_t;
+
+/* mailbox 3: power conservation */
+typedef struct {
+	u32	ardy;
+	u32	aslc;
+	u32	tche;
+	u32	alsi;
+	u32	bclp;
+	u32	pfit;
+	u32	cblv;
+	u16	bclm[20];
+	u32	cpfm;
+	u32	epfm;
+	u8	plut[74];
+	u32	pfmb;
+	u32	ccdv;
+	u32	pcft;
+	u8	reserved[94];
+} __attribute__((packed)) opregion_mailbox3_t;
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID	(1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+typedef struct {
+	u8 gvd1[7168];
+} __attribute__((packed)) opregion_vbt_t;
+
+/* IGD OpRegion */
+typedef struct {
+	opregion_header_t header;
+	opregion_mailbox1_t mailbox1;
+	opregion_mailbox2_t mailbox2;
+	opregion_mailbox3_t mailbox3;
+	opregion_vbt_t vbt;
+} __attribute__((packed)) igd_opregion_t;
+
+/* Intel Video BIOS (Option ROM) */
+typedef struct {
+	u16	signature;
+	u8	size;
+	u8	reserved[21];
+	u16	pcir_offset;
+	u16	vbt_offset;
+} __attribute__((packed)) optionrom_header_t;
+
+#define OPROM_SIGNATURE 0xaa55
+
+typedef struct {
+	u32 signature;
+	u16 vendor;
+	u16 device;
+	u16 reserved1;
+	u16 length;
+	u8  revision;
+	u8  classcode[3];
+	u16 imagelength;
+	u16 coderevision;
+	u8  codetype;
+	u8  indicator;
+	u16 reserved2;
+} __attribute__((packed)) optionrom_pcir_t;
+
+typedef struct {
+	u8  hdr_signature[20];
+	u16 hdr_version;
+	u16 hdr_size;
+	u16 hdr_vbt_size;
+	u8  hdr_vbt_checksum;
+	u8  hdr_reserved;
+	u32 hdr_vbt_datablock;
+	u32 hdr_aim[4];
+	u8  datahdr_signature[16];
+	u16 datahdr_version;
+	u16 datahdr_size;
+	u16 datahdr_datablocksize;
+	u8  coreblock_id;
+	u16 coreblock_size;
+	u16 coreblock_biossize;
+	u8  coreblock_biostype;
+	u8  coreblock_releasestatus;
+	u8  coreblock_hwsupported;
+	u8  coreblock_integratedhw;
+	u8  coreblock_biosbuild[4];
+	u8  coreblock_biossignon[155];
+} __attribute__((packed)) optionrom_vbt_t;
+
+#define VBT_SIGNATURE 0x54425624
+
diff --git a/src/northbridge/intel/calpella/northbridge.c b/src/northbridge/intel/calpella/northbridge.c
new file mode 100644
index 0000000..881b857
--- /dev/null
+++ b/src/northbridge/intel/calpella/northbridge.c
@@ -0,0 +1,446 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <delay.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cbmem.h>
+#include "chip.h"
+#include "calpella.h"
+
+static int bridge_revision_id = -1;
+
+int bridge_silicon_revision(void)
+{
+	if (bridge_revision_id < 0) {
+		uint8_t stepping = cpuid_eax(1) & 0xf;
+		uint8_t bridge_id = pci_read_config16(
+			dev_find_slot(0, PCI_DEVFN(0, 0)),
+			PCI_DEVICE_ID) & 0xf0;
+		bridge_revision_id = bridge_id | stepping;
+	}
+	return bridge_revision_id;
+}
+
+/* Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 384;
+
+static int get_pcie_bar(u32 *base, u32 *len)
+{
+	device_t dev;
+	u32 pciexbar_reg;
+
+	*base = 0;
+	*len = 0;
+
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (!dev)
+		return 0;
+
+	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+	if (!(pciexbar_reg & (1 << 0)))
+		return 0;
+
+	switch ((pciexbar_reg >> 1) & 3) {
+	case 0: // 256MB
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		*len = 256 * 1024 * 1024;
+		return 1;
+	case 1: // 128M
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		*len = 128 * 1024 * 1024;
+		return 1;
+	case 2: // 64M
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		*len = 64 * 1024 * 1024;
+		return 1;
+	}
+
+	return 0;
+}
+
+static void add_fixed_resources(struct device *dev, int index)
+{
+	struct resource *resource;
+	u32 pcie_config_base, pcie_config_size;
+
+	if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
+		       "size=0x%x\n", pcie_config_base, pcie_config_size);
+		resource = new_resource(dev, index++);
+		resource->base = (resource_t) pcie_config_base;
+		resource->size = (resource_t) pcie_config_size;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	mmio_resource(dev, index++, legacy_hole_base_k,
+			(0xc0000 >> 10) - legacy_hole_base_k);
+	reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+			(0x100000 - 0xc0000) >> 10);
+
+#if CONFIG_CHROMEOS_RAMOOPS
+	reserved_ram_resource(dev, index++,
+			CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
+			CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
+#endif
+	bad_ram_resource(dev, index++, 0x1fc000000ULL >> 10, 
+			 0x004000000 >> 10);
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+	uint32_t tseg_base;
+	uint64_t TOUUD;
+	uint16_t reg16;
+
+	tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)),
+				      TSEG);
+	TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
+				  D0F0_TOUUD);
+
+	printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
+	printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned) TOUUD);
+ 
+ 	/* Report the memory regions */
+ 	ram_resource(dev, 3, 0, 640);
+	ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768));
+
+
+
+	/* Using uma_resource() here would fail as base & size cannot
+	 * be used as-is for a single MTRR. This would cause excessive
+	 * use of MTRRs.
+	 *
+	 * Use of mmio_resource() instead does not create UC holes by using
+	 * MTRRs, but making these regions uncacheable is taken care of by
+	 * making sure they do not overlap with any ram_resource().
+	 *
+	 * The resources can be changed to use separate mmio_resource()
+	 * calls after MTRR code is able to merge them wisely.
+	 */
+	mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10);
+
+	reg16 = pci_read_config16 (dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);
+	const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
+	/* Igd memory */
+	const int uma_sizes_igd[16] = 
+	  {
+	    0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 
+	  };
+	u32 igd_base, gtt_base;
+	int uma_size_igd, uma_size_gtt;
+
+	uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF];
+	uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF];
+
+	igd_base = pci_read_config32 (dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE);
+	gtt_base = pci_read_config32 (dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE);
+	mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10);
+	mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10);
+ 
+	if (TOUUD > 4096 + 256)
+		ram_resource(dev, 8, (4096 << 10),
+			     ((TOUUD - 4096) << 10));
+
+	add_fixed_resources(dev, 9);
+ 
+ 	assign_resources(dev->link_list);
+ 
+ 	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tseg_base - HIGH_MEMORY_SIZE;
+ 	high_tables_size = HIGH_MEMORY_SIZE;
+}
+
+	/* TODO We could determine how many PCIe busses we need in
+	 * the bar. For now that number is hardcoded to a max of 64.
+	 * See e7525/northbridge.c for an example.
+	 */
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void mc_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	pci_dev_read_resources(dev);
+
+	/* So, this is one of the big mysteries in the coreboot resource
+	 * allocator. This resource should make sure that the address space
+	 * of the PCIe memory mapped config space bar. But it does not.
+	 */
+
+	/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
+	resource = new_resource(dev, 0xcf);
+	resource->base = DEFAULT_PCIEXBAR;
+	resource->size = 256 * 1024 * 1024;	/* 64MB hard coded PCIe config space */
+	resource->flags =
+	    IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+	    IORESOURCE_ASSIGNED;
+	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+		     (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
+}
+
+static void mc_set_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Report the PCIe BAR */
+	resource = find_resource(dev, 0xcf);
+	if (resource) {
+		report_resource_stored(dev, resource, "<mmconfig>");
+	}
+
+	/* And call the normal set_resources */
+	pci_dev_set_resources(dev);
+}
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static void northbridge_dmi_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Clear error status bits */
+	DMIBAR32(0x1c4) = 0xffffffff;
+	DMIBAR32(0x1d0) = 0xffffffff;
+
+	/* Steps prior to DMI ASPM */
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		reg32 = DMIBAR32(0x250);
+		reg32 &= ~((1 << 22)|(1 << 20));
+		reg32 |= (1 << 21);
+		DMIBAR32(0x250) = reg32;
+	}
+
+	reg32 = DMIBAR32(0x238);
+	reg32 |= (1 << 29);
+	DMIBAR32(0x238) = reg32;
+
+	if (bridge_silicon_revision() >= SNB_STEP_D0) {
+		reg32 = DMIBAR32(0x1f8);
+		reg32 |= (1 << 16);
+		DMIBAR32(0x1f8) = reg32;
+	} else if (bridge_silicon_revision() >= SNB_STEP_D1) {
+		reg32 = DMIBAR32(0x1f8);
+		reg32 &= ~(1 << 26);
+		reg32 |= (1 << 16);
+		DMIBAR32(0x1f8) = reg32;
+
+		reg32 = DMIBAR32(0x1fc);
+		reg32 |= (1 << 12) | (1 << 23);
+		DMIBAR32(0x1fc) = reg32;
+	}
+
+	/* Enable ASPM on SNB link, should happen before PCH link */
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+		reg32 = DMIBAR32(0xd04);
+		reg32 |= (1 << 4);
+		DMIBAR32(0xd04) = reg32;
+	}
+
+	reg32 = DMIBAR32(0x88);
+	reg32 |= (1 << 1) | (1 << 0);
+	DMIBAR32(0x88) = reg32;
+}
+
+static void northbridge_init(struct device *dev)
+{
+	u8 bios_reset_cpl;
+	u32 bridge_type;
+
+	northbridge_dmi_init(dev);
+
+	bridge_type = MCHBAR32(0x5f10);
+	bridge_type &= ~0xff;
+
+	if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+		/* Enable Power Aware Interrupt Routing */
+		u8 pair = MCHBAR8(0x5418);
+		pair &= ~0xf;	/* Clear 3:0 */
+		pair |= 0x4;	/* Fixed Priority */
+		MCHBAR8(0x5418) = pair;
+
+		/* 30h for IvyBridge */
+		bridge_type |= 0x30;
+	} else {
+		/* 20h for Sandybridge */
+		bridge_type |= 0x20;
+	}
+	MCHBAR32(0x5f10) = bridge_type;
+
+	/*
+	 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
+	 * that BIOS has initialized memory and power management
+	 */
+	bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
+	bios_reset_cpl |= 1;
+	MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
+	printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
+
+	/* Configure turbo power limits 1ms after reset complete bit */
+	mdelay(1);
+#ifdef DISABLED
+		set_power_limits(28);
+
+	/*
+	 * CPUs with configurable TDP also need power limits set
+	 * in MCHBAR.  Use same values from MSR_PKG_POWER_LIMIT.
+	 */
+	if (cpu_config_tdp_levels()) {
+		msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT);
+		MCHBAR32(0x59A0) = msr.lo;
+		MCHBAR32(0x59A4) = msr.hi;
+	}
+#endif
+	/* Set here before graphics PM init */
+	MCHBAR32(0x5500) = 0x00100001;
+}
+
+static void northbridge_enable(device_t dev)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+	switch (pci_read_config32(dev, SKPAD)) {
+	case 0xcafebabe:
+		printk(BIOS_DEBUG, "Normal boot.\n");
+		acpi_slp_type=0;
+		break;
+	case 0xcafed00d:
+		printk(BIOS_DEBUG, "S3 Resume.\n");
+		acpi_slp_type=3;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
+		acpi_slp_type=0;
+		break;
+	}
+#endif
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = mc_read_resources,
+	.set_resources    = mc_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = northbridge_init,
+	.enable           = northbridge_enable,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+
+static const struct pci_driver mc_driver_44 __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x0044, /* Sandy bridge */
+};
+
+static const struct pci_driver mc_driver_0100 __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x0100,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x0104, /* Sandy bridge */
+};
+
+static const struct pci_driver mc_driver_1 __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x0154, /* Ivy bridge */
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+	/* Enable ROM caching if option was selected. */
+	x86_mtrr_enable_rom_caching();
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_sandybridge_ops = {
+	CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/calpella/pcie_config.c b/src/northbridge/intel/calpella/pcie_config.c
new file mode 100644
index 0000000..27f3640
--- /dev/null
+++ b/src/northbridge/intel/calpella/pcie_config.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "calpella.h"
+
+static inline __attribute__ ((always_inline))
+u8 pcie_read_config8(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read8(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u16 pcie_read_config16(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read16(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u32 pcie_read_config32(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read32(addr);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config8(device_t dev, unsigned int where, u8 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write8(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config16(device_t dev, unsigned int where, u16 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write16(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config32(device_t dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write32(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
+{
+	u8 value = pcie_read_config8(dev, where);
+	pcie_write_config8(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
+{
+	u16 value = pcie_read_config16(dev, where);
+	pcie_write_config16(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
+{
+	u32 value = pcie_read_config32(dev, where);
+	pcie_write_config32(dev, where, value | ormask);
+}
diff --git a/src/northbridge/intel/calpella/raminit.c b/src/northbridge/intel/calpella/raminit.c
new file mode 100644
index 0000000..e4ecd1d
--- /dev/null
+++ b/src/northbridge/intel/calpella/raminit.c
@@ -0,0 +1,5502 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef REAL
+#define REAL 1
+#endif
+
+#if REAL
+#include <console/console.h>
+#include <string.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cbmem.h>
+#include <arch/cbfs.h>
+#include <cbfs.h>
+#include <ip_checksum.h>
+#include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
+#include <arch/cpu.h>
+#include <spd.h>
+#include "raminit.h"
+#include <timestamp.h>
+#include <cpu/x86/mtrr.h>
+#endif
+
+#if !REAL
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+typedef u32 device_t;
+#endif
+
+#include "calpella.h"
+
+#include "southbridge/intel/bd82x6x/me.h"
+
+#if REAL
+#include <delay.h>
+#endif
+
+
+#define NORTHBRIDGE 0, 0, 0
+#define SOUTHBRIDGE 0, 0x1f, 0
+#define HECIDEV 0, 0x16, 0
+#define HECIBAR 0x10
+
+#define FOR_ALL_RANKS					   \
+  for (channel = 0; channel < NUM_CHANNELS; channel++)	   \
+    for (slot = 0; slot < NUM_SLOTS; slot++)		   \
+      for (rank = 0; rank < NUM_RANKS; rank++)
+
+#define FOR_POPULATED_RANKS				   \
+  for (channel = 0; channel < NUM_CHANNELS; channel++)	   \
+    for (slot = 0; slot < NUM_SLOTS; slot++)		   \
+      for (rank = 0; rank < NUM_RANKS; rank++)		   \
+	if (info->populated_ranks[channel][slot][rank])
+
+#define FOR_POPULATED_RANKS_BACKWARDS				\
+  for (channel = NUM_CHANNELS - 1; channel >= 0; channel--)	\
+    for (slot = 0; slot < NUM_SLOTS; slot++)			\
+      for (rank = 0; rank < NUM_RANKS; rank++)			\
+	if (info->populated_ranks[channel][slot][rank])
+
+/* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */
+typedef struct
+{
+  u8 smallest;
+  u8 largest;
+} timing_bounds_t[2][2][2][9];
+
+struct ram_training
+{
+  /* [TM][CHANNEL][SLOT][RANK][LANE] */
+  u16 lane_timings[4][2][2][2][9]; 
+  u16 reg_178;
+  u16 reg_10b;
+
+  u8 reg178_center;
+  u8 reg178_smallest;
+  u8 reg178_largest;
+  timing_bounds_t timing_bounds[2];
+  u16 timing_offset[2][2][2][9];
+  u16 timing2_offset[2][2][2][9];
+  u16 timing2_bounds[2][2][2][9][2];
+};
+
+#if !REAL
+#include "raminit_fake.c"
+#else
+
+#include <lib.h> /* Prototypes */
+
+static void
+my_write_msr (u32 addr, u64 val)
+{
+  msr_t msr = { .lo = val, .hi = val >> 32 };
+
+  wrmsr (addr, msr);
+}
+
+static inline void
+write_acpi32 (u32 addr, u32 val)
+{
+  outl (val, DEFAULT_PMBASE | addr);
+}
+
+static inline void
+write_acpi16 (u32 addr, u16 val)
+{
+  outw (val, DEFAULT_PMBASE | addr);
+}
+
+static inline u32
+read_acpi32 (u32 addr)
+{
+  return inl (DEFAULT_PMBASE | addr);
+}
+
+static inline u16
+read_acpi16 (u32 addr)
+{
+  return inw (DEFAULT_PMBASE | addr);
+}
+
+static inline u16
+read_tco16 (u32 addr)
+{
+  return inw (DEFAULT_PMBASE | (0x60 + addr));
+}
+
+static inline u8
+read_tco8 (u32 addr)
+{
+  return inb (DEFAULT_PMBASE | (0x60 + addr));
+}
+
+static inline void
+write_tco16 (u32 addr, u16 val)
+{
+  outw (val, DEFAULT_PMBASE | (0x60 + addr));
+}
+
+static inline void
+write_tco8 (u32 addr, u8 val)
+{
+  outb (val, DEFAULT_PMBASE | (0x60 + addr));
+}
+
+static inline void
+write_mchbar32 (u32 addr, u32 val)
+{
+  MCHBAR32(addr) = val;
+  //  udelay (1000);
+}
+
+static inline void
+write_mchbar16 (u32 addr, u16 val)
+{
+  MCHBAR16(addr) = val;
+  //udelay (1000);
+}
+
+static inline void
+write_mchbar8 (u32 addr, u8 val)
+{
+  MCHBAR8(addr) = val;
+  //udelay (1000);
+}
+
+static u32 mchgav (u32 addr, u32 val)
+{
+  //printk (BIOS_DEBUG, "MCH: [%x] => %x\n", addr, val);
+  return val;
+}
+
+static inline u32
+read_mchbar32 (u32 addr)
+{
+  return mchgav (addr, MCHBAR32(addr));
+}
+
+static inline u32
+read_mchbar32_bypass (u32 addr)
+{
+  return MCHBAR32(addr);
+}
+
+static inline u16
+read_mchbar16 (u32 addr)
+{
+  return mchgav (addr, MCHBAR16(addr));
+}
+
+static inline u8
+read_mchbar8 (u32 addr)
+{
+  return mchgav (addr, MCHBAR8(addr));
+}
+
+static inline u8
+read_mchbar8_bypass (u32 addr)
+{
+  return MCHBAR8(addr);
+}
+
+static u32
+pci_read32 (int bus, int dev, int func, u32 addr)
+{
+  return pci_read_config32(PCI_DEV(bus, dev, func), addr);
+}
+
+static u8
+pci_read8 (int bus, int dev, int func, u32 addr)
+{
+  return pci_read_config8(PCI_DEV(bus, dev, func), addr);
+}
+
+static void
+pci_write32 (int bus, int dev, int func, u32 addr, u32 val)
+{
+  return pci_write_config32(PCI_DEV(bus, dev, func), addr, val);
+}
+
+static void
+pci_write16 (int bus, int dev, int func, u32 addr, u16 val)
+{
+  return pci_write_config16(PCI_DEV(bus, dev, func), addr, val);
+}
+
+static void
+pci_write8 (int bus, int dev, int func, u32 addr, u8 val)
+{
+  return pci_write_config8(PCI_DEV(bus, dev, func), addr, val);
+}
+
+static u16
+pci_read16 (int bus, int dev, int func, u32 addr)
+{
+  return pci_read_config16(PCI_DEV(bus, dev, func), addr);
+}
+
+static void
+pci_mm_write8 (int bus, int dev, int func, u32 addr, u8 val)
+{
+  write8 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr, val);
+}
+static void
+pci_mm_write16 (int bus, int dev, int func, u32 addr, u16 val)
+{
+  write16 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr, val);
+}
+
+static void
+pci_mm_write32 (int bus, int dev, int func, u32 addr, u32 val)
+{
+  write32 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr, val);
+}
+
+static u32
+pci_mm_read32 (int bus, int dev, int func, u32 addr)
+{
+  return read32 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr);
+}
+
+static u16
+pci_mm_read16 (int bus, int dev, int func, u32 addr)
+{
+  return read16 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr);
+}
+
+static u8
+pci_mm_read8 (int bus, int dev, int func, u32 addr)
+{
+  return read8 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr);
+}
+
+static void clflush(u32 addr)
+{
+  asm volatile ("clflush (%0)" : : "r" (addr));
+}
+
+typedef struct _u128
+{
+  u64 lo;
+  u64 hi;
+} u128;
+
+static void
+read128 (u32 addr, u64 *out)
+{
+  u128 ret;
+  u128 stor;
+  asm volatile ("movdqu %%xmm0, %0\n"
+                "movdqa (%2), %%xmm0\n"
+		"movdqu %%xmm0, %1\n"
+		"movdqu %0, %%xmm0":"+m"(stor),"=m"(ret):"r"(addr));
+  out[0] = ret.lo;
+  out[1] = ret.hi;
+}
+
+static u64
+my_read_msr (u32 addr)
+{
+  msr_t m = rdmsr (addr);
+  return (((u64)m.hi) << 32) | m.lo;
+}
+
+#endif
+
+/* OK */
+static void
+write_1d0 (u32 val, u16 addr, int bits, int flag)
+{
+  write_mchbar32 (0x1d0, 0);
+  while (read_mchbar32_bypass (0x1d0) & 0x800000);
+  write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits));
+  write_mchbar32 (0x1d0, 0x40000000 | addr);
+  while (read_mchbar32_bypass (0x1d0) & 0x800000);
+}
+
+/* OK */
+static u16
+read_1d0 (u16 addr, int split)
+{
+  u32 val;
+  write_mchbar32 (0x1d0, 0);
+  while (read_mchbar32_bypass (0x1d0) & 0x800000);
+  write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8_bypass (0x246) >> 2) & 3) + 0x361 - addr));
+  while (read_mchbar32_bypass (0x1d0) & 0x800000);
+  val = read_mchbar32_bypass (0x1d8);
+  write_1d0 (0, 0x33d, 0, 0);
+  write_1d0 (0, 0x33d, 0, 0);
+  val &= ((1 << split) - 1);
+  //  printk (BIOS_ERR, "R1D0C [%x] => %x\n", addr, val);
+  return val;
+}
+
+static void
+sfence (void)
+{
+#if REAL
+  asm volatile ("sfence");
+#endif
+}
+
+
+static inline u16
+get_lane_offset (int slot, int rank, int lane)
+{
+  return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8);
+}
+
+static inline u16
+get_timing_register_addr (int lane, int tm, int slot, int rank)
+{
+  const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
+  return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4];
+}
+
+
+#if REAL
+static u32 gav_real (int line, u32 in)
+{
+  //  printk (BIOS_DEBUG, "%d: GAV: %x\n", line, in);
+  return in;
+}
+
+#define gav(x) gav_real (__LINE__, (x))
+#endif
+struct raminfo
+{
+  u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */
+  u16 fsb_frequency; /* in 1.(1)/2 MHz.  */
+  u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */
+  u8 density[2][2]; /* [CHANNEL][SLOT] */
+  u8 populated_ranks[2][2][2]; /* [CHANNEL][SLOT][RANK] */
+  int rank_start[2][2][2];
+  u8 cas_latency;
+  u8 board_lane_delay[9];
+  u8 use_ecc;
+  u8 revision;
+  u8 max_supported_clock_speed_index;
+  u8 uma_enabled;
+  u8 spd[2][2][151]; /* [CHANNEL][SLOT][BYTE]  */
+  u8 silicon_revision;
+  u8 populated_ranks_mask[2];
+  u8 max_slots_used_in_channel;
+  u8 mode4030[2];
+  u16 avg4044[2];
+  u16 max4048[2];
+  unsigned total_memory_mb;
+  unsigned interleaved_part_mb;
+  unsigned non_interleaved_part_mb;
+
+  u32 heci_bar;
+  u64 heci_uma_addr;
+  unsigned memory_reserved_for_heci_mb;
+
+  struct ram_training training;
+  u32 last_500_command[2];
+
+  u8 reg2ca9_bit0;
+  u8 reg274265[2][3]; /* [CHANNEL][REGISTER]*/
+  u32 delay46_ps[2];
+  u32 delay54_ps[2];
+  u8 revision_flag_1;
+  u8 some_delay_1_cycle_floor;
+  u8 some_delay_2_halfcycles_ceil;
+  u8 some_delay_3_ps_rounded;
+
+  const struct ram_training *cached_training;
+};
+
+static void
+write_500 (struct raminfo *info, int channel, u32 val, u16 addr, int bits, int flag);
+
+/* OK */
+static u16
+read_500_bypass (struct raminfo *info, int channel, u16 addr, int split)
+{
+  u32 val;
+  info->last_500_command[channel] = 0x80000000;
+  write_mchbar32 (0x500 + (channel << 10), 0);
+  while (read_mchbar32_bypass (0x500 + (channel << 10)) & 0x800000);
+  write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8_bypass (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr));
+  while (read_mchbar32_bypass (0x500 + (channel << 10)) & 0x800000);
+  val = read_mchbar32_bypass (0x508 + (channel << 10));
+  return val & ((1 << split) - 1);
+}
+
+static u16
+read_500 (struct raminfo *info, int channel, u16 addr, int split)
+{
+  u16 ret;
+  ret = read_500_bypass (info, channel, addr, split);
+  //  printk (BIOS_ERR, "R500 [%d/%x] => %x\n", channel, addr, ret);
+  return ret;
+}
+
+/* OK */
+static void
+write_500 (struct raminfo *info, int channel, u32 val, u16 addr, int bits, int flag)
+{
+  if (info->last_500_command[channel] == 0x80000000)
+    {
+      info->last_500_command[channel] = 0x40000000;
+      write_500 (info, channel, 0, 0xb61, 0, 0);
+    }
+  write_mchbar32 (0x500 + (channel << 10), 0); 
+  while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
+  write_mchbar32 (0x504 + (channel << 10), (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits));
+  write_mchbar32 (0x500 + (channel << 10), 0x40000000 | addr);
+  while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
+}
+
+static int
+rw_test (int rank)
+{
+  const u32 mask = 0xf00fc33c;
+  int ok = 0xff;
+  int i;
+  for (i = 0; i < 64; i++)
+    write32 ((rank << 28) | (i << 2), 0);
+  sfence ();
+  for (i = 0; i < 64; i++)
+    gav (read32 ((rank << 28) | (i << 2)));
+  sfence ();
+  for (i = 0; i < 32; i++)
+    {
+      u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0);
+      write32 ((rank << 28) | (i << 3), pat);
+      write32 ((rank << 28) | (i << 3) | 4, pat);
+    }
+  sfence ();
+  for (i = 0; i < 32; i++)
+    {
+      u8 pat = (((mask >> i) & 1) ? 0xff : 0);
+      int j;
+      u32 val;
+      gav (val = read32 ((rank << 28) | (i << 3)));
+      for (j = 0; j < 4; j++)
+	if (((val >> (j * 8)) & 0xff) != pat)
+	  ok &= ~(1 << j);
+      gav (val = read32 ((rank << 28) | (i << 3) | 4));
+      for (j = 0; j < 4; j++)
+	if (((val >> (j * 8)) & 0xff) != pat)
+	  ok &= ~(16 << j);
+    }
+  sfence ();
+  for (i = 0; i < 64; i++)
+    write32 ((rank << 28) | (i << 2), 0);
+  sfence ();
+  for (i = 0; i < 64; i++)
+    gav (read32 ((rank << 28) | (i << 2)));
+
+  return ok;
+}
+
+static void
+program_timings (struct raminfo *info, u16 base,
+		 int channel, int slot, int rank)
+{
+  int lane;
+  for (lane = 0; lane < 8; lane++)
+    {
+      write_500 (info, channel, base + info->training.lane_timings[2][channel][slot][rank][lane],
+		 get_timing_register_addr (lane, 2, slot, rank), 9, 0);
+      write_500 (info, channel, base + info->training.lane_timings[3][channel][slot][rank][lane],
+		 get_timing_register_addr (lane, 3, slot, rank), 9, 0);
+    }
+}
+
+static void
+write_26c (int channel, u16 si)
+{
+  write_mchbar32 (0x26c + (channel << 10), 0x03243f35);
+  write_mchbar32 (0x268 + (channel << 10), 0xcfc00000 | (si << 9));
+  write_mchbar16 (0x2b9 + (channel << 10), si);
+}
+
+static u32
+get_580 (int channel, u8 addr)
+{
+  u32 ret;
+  gav (read_1d0 (0x142, 3));
+  write_mchbar8 (0x5ff, 0x0); /* OK */
+  write_mchbar8 (0x5ff, 0x80); /* OK */
+  write_mchbar32 (0x580 + (channel << 10), 0x8493c012 | addr);
+  write_mchbar8 (0x580 + (channel << 10), read_mchbar8 (0x580 + (channel << 10)) | 1);
+  while (!((ret = read_mchbar32 (0x580 + (channel << 10))) & 0x10000));
+  write_mchbar8 (0x580 + (channel << 10), read_mchbar8 (0x580 + (channel << 10)) & ~1);
+  return ret;
+}
+
+const int cached_config = 0;
+
+#define NUM_CHANNELS 2
+#define NUM_SLOTS 2
+#define NUM_RANKS 2
+#define RANK_SHIFT 28
+#define CHANNEL_SHIFT 10
+
+#include "raminit_tables.c"
+
+static void
+seq9 (struct raminfo *info, int channel, int slot, int rank)
+{
+  int i, lane;
+
+  for (i = 0; i < 2; i++)
+    for (lane = 0; lane < 8; lane++)
+      write_500 (info, channel, info->training.lane_timings[i + 1][channel][slot][rank][lane],
+		 get_timing_register_addr (lane, i + 1, slot, rank), 9, 0);
+
+  write_1d0 (1, 0x103, 6, 1);
+  for (lane = 0; lane < 8; lane++)
+    write_500 (info, channel, info->training.lane_timings[0][channel][slot][rank][lane], get_timing_register_addr (lane, 0, slot, rank), 9, 0);
+
+  for (i = 0; i < 2; i++)
+    {
+      for (lane = 0; lane < 8; lane++)
+	write_500 (info, channel, info->training.lane_timings[i + 1][channel][slot][rank][lane], get_timing_register_addr (lane, i + 1, slot, rank), 9, 0);
+      gav (get_580 (channel, ((i + 1) << 2) | (rank << 5)));
+    }
+
+  gav (read_1d0 (0x142, 3)); // = 0x10408118
+  write_mchbar8 (0x5ff, 0x0); /* OK */
+  write_mchbar8 (0x5ff, 0x80); /* OK */
+  write_1d0 (0x2, 0x142, 3, 1);
+  for (lane = 0; lane < 8; lane++)
+    {
+      //      printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]);
+      info->training.lane_timings[2][channel][slot][rank][lane] = read_500 (info, channel, get_timing_register_addr (lane, 2, slot, rank), 9);
+      //printk (BIOS_ERR, "after: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]);
+      info->training.lane_timings[3][channel][slot][rank][lane] = info->training.lane_timings[2][channel][slot][rank][lane] + 0x20;
+    }
+}
+
+static int
+count_ranks_in_channel (struct raminfo *info, int channel)
+{
+  int slot, rank;
+  int res = 0;
+  for (slot = 0; slot < NUM_SLOTS; slot++)
+    for (rank = 0; rank < NUM_SLOTS; rank++)
+      res += info->populated_ranks[channel][slot][rank];
+  return res;
+}
+
+static void
+config_rank (struct raminfo *info, int s3resume, int channel, int slot, int rank)
+{
+  int add;
+
+  write_1d0 (0, 0x178, 7, 1);
+  seq9 (info, channel, slot, rank);
+  program_timings (info, 0x80, channel, slot, rank);
+
+  if (channel == 0)
+    add = count_ranks_in_channel (info, 1);
+  else
+    add = 0;
+  if (!s3resume)
+    gav (rw_test (rank + add));
+  program_timings (info, 0x00, channel, slot, rank);
+  if (!s3resume)
+    gav (rw_test (rank + add));
+  if (!s3resume)
+    gav (rw_test (rank + add));
+  write_1d0 (0, 0x142, 3, 1);
+  write_1d0 (0, 0x103, 6, 1);
+	
+  gav (get_580 (channel, 0xc | (rank << 5)));
+  gav (read_1d0 (0x142, 3));
+	
+  write_mchbar8 (0x5ff, 0x0); /* OK */
+  write_mchbar8 (0x5ff, 0x80); /* OK */
+}
+
+static void
+set_4cf (struct raminfo *info, int channel, u8 val)
+{
+  gav (read_500 (info, channel, 0x4cf, 4)); // = 0xc2300cf9
+  write_500 (info, channel, val, 0x4cf, 4, 1);
+  gav (read_500 (info, channel, 0x659, 4)); // = 0x80300839
+  write_500 (info, channel, val, 0x659, 4, 1);
+  gav (read_500 (info, channel, 0x697, 4)); // = 0x80300839
+  write_500 (info, channel, val, 0x697, 4, 1);
+}
+
+static void
+set_334 (int zero)
+{
+  int j, k, channel;
+  const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b };
+  u32 vd8[2][16];
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  u32 a = (j == 1) ? 0x29292929 : 0x31313131;
+	  u32 lmask = (j == 3) ? 0xffff : 0xffffffff;
+	  u16 c;
+	  if ((j == 0 || j == 3) && zero)
+	    c = 0;
+	  else if (j == 3)
+	    c  = 0x5f;
+	  else
+	    c = 0x5f5f;
+
+	  for (k = 0; k < 2; k++)
+	    {
+	      write_mchbar32 (0x138 + 8 * k, (channel << 26) | (j << 24));
+	      gav (vd8[1][(channel << 3) | (j << 1) | k] = read_mchbar32 (0x138 + 8 * k));
+	      gav (vd8[0][(channel << 3) | (j << 1) | k] = read_mchbar32 (0x13c + 8 * k));
+	    }
+
+	  write_mchbar32 (0x334 + (channel << 10) + (j * 0x44), zero ? 0 : val3[j]);
+	  write_mchbar32 (0x32c + (channel << 10) + (j * 0x44), zero ? 0 : (0x18191819 & lmask));
+	  write_mchbar16 (0x34a + (channel << 10) + (j * 0x44), c);
+	  write_mchbar32 (0x33c + (channel << 10) + (j * 0x44), zero ? 0 : (a & lmask));
+	  write_mchbar32 (0x344 + (channel << 10) + (j * 0x44), zero ? 0 : (a & lmask));
+	}
+    }
+
+  write_mchbar32 (0x130, read_mchbar32 (0x130) | 1); /* OK */
+  while (read_mchbar8 (0x130) & 1); /* OK */
+}
+
+static void
+rmw_1d0 (u16 addr, u32 and, u32 or, int split, int flag)
+{
+  u32 v;
+  v = read_1d0 (addr, split); 
+  write_1d0 ((v & and) | or, addr, split, flag);
+}
+
+static int 
+find_highest_bit_set (u16 val)
+{
+  int i;
+  for (i = 15; i >= 0; i--)
+    if (val & (1 << i))
+      return i;
+  return -1;
+}
+
+static int 
+find_lowest_bit_set32 (u32 val)
+{
+  int i;
+  for (i = 0; i < 32; i++)
+    if (val & (1 << i))
+      return i;
+  return -1;
+}
+
+#define max(a,b) (((a) > (b)) ? (a) : (b))
+#define min(a,b) (((a) < (b)) ? (a) : (b))
+
+enum
+  {
+    DEVICE_TYPE = 2,
+    MODULE_TYPE = 3,
+    DENSITY = 4,
+    RANKS_AND_DQ = 7,
+    MEMORY_BUS_WIDTH = 8,
+    TIMEBASE_DIVIDEND = 10,
+    TIMEBASE_DIVISOR = 11,
+    CYCLETIME = 12,
+
+    CAS_LATENCIES_LSB = 14,
+    CAS_LATENCIES_MSB = 15,
+    CAS_LATENCY_TIME = 16,
+    THERMAL_AND_REFRESH = 31,
+    REFERENCE_RAW_CARD_USED = 62,
+    RANK1_ADDRESS_MAPPING = 63
+  };
+
+static void
+calculate_timings (struct raminfo *info)
+{
+  unsigned cycletime;
+  unsigned cas_latency_time;
+  unsigned supported_cas_latencies;
+  unsigned channel, slot;
+  unsigned clock_speed_index;
+  unsigned min_cas_latency;
+  unsigned cas_latency;
+  unsigned max_clock_index;
+
+  /* Find common CAS latency  */
+  supported_cas_latencies = 0x3fe;
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    for (slot = 0; slot < NUM_SLOTS; slot++)
+      if (info->populated_ranks[channel][slot][0])
+	supported_cas_latencies &= 2 * (info->spd[channel][slot][CAS_LATENCIES_LSB] | (info->spd[channel][slot][CAS_LATENCIES_MSB] << 8));
+
+  max_clock_index = min (3, info->max_supported_clock_speed_index);
+
+  cycletime = min_cycletime[max_clock_index];
+  cas_latency_time = min_cas_latency_time[max_clock_index];
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    for (slot = 0; slot < NUM_SLOTS; slot++)
+      if (info->populated_ranks[channel][slot][0])
+	{
+	  unsigned timebase;
+	  timebase = 1000 * info->spd[channel][slot][TIMEBASE_DIVIDEND] / info->spd[channel][slot][TIMEBASE_DIVISOR];
+	  cycletime = max (cycletime, timebase * info->spd[channel][slot][CYCLETIME]);
+	  cas_latency_time = max (cas_latency_time, timebase * info->spd[channel][slot][CAS_LATENCY_TIME]);
+	}
+  for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++)
+    {
+      if (cycletime == min_cycletime[clock_speed_index])
+	break;
+      if (cycletime > min_cycletime[clock_speed_index])
+	{
+	  clock_speed_index--;
+	  cycletime = min_cycletime[clock_speed_index];
+	  break;
+	}
+    }
+  min_cas_latency = (cas_latency_time + cycletime - 1) / cycletime;
+  cas_latency = 0;
+  while (supported_cas_latencies)
+    {
+      cas_latency = find_highest_bit_set(supported_cas_latencies) + 3;
+      if (cas_latency <= min_cas_latency)
+        break;
+      supported_cas_latencies &= ~(1 << find_highest_bit_set(supported_cas_latencies));
+    }
+
+  if (cas_latency != min_cas_latency && clock_speed_index)
+    clock_speed_index--;
+
+  if (cas_latency * min_cycletime[clock_speed_index] > 20000)
+    die ("Couldn't configure DRAM");
+  info->clock_speed_index = clock_speed_index;
+  info->cas_latency = cas_latency;
+}
+
+static void
+program_base_timings (struct raminfo *info)
+{
+  unsigned channel;
+  unsigned slot, rank, lane;
+  unsigned extended_silicon_revision;
+  int i;
+
+  extended_silicon_revision = info->silicon_revision;
+  if (info->silicon_revision == 0)
+    for (channel = 0; channel < NUM_CHANNELS; channel++)
+      for (slot = 0; slot < NUM_SLOTS; slot++)
+	if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3)
+	  extended_silicon_revision = 4;
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      for (slot = 0; slot < NUM_SLOTS; slot++)
+	for (rank = 0; rank < NUM_SLOTS; rank++)
+	  {
+	    int card_timing_2;
+	    if (!info->populated_ranks[channel][slot][rank])
+	      continue;
+
+	    for (lane = 0; lane < 9; lane++)
+	      {
+		int tm_reg;
+		int card_timing;
+
+		card_timing = 0;
+		if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3)
+		  {
+		    int reference_card;
+		    reference_card = info->spd[channel][slot][REFERENCE_RAW_CARD_USED] & 0x1f;
+		    if (reference_card == 3)
+		      card_timing = u16_ffd1188[0][lane][info->clock_speed_index];
+		    if (reference_card == 5)
+		      card_timing = u16_ffd1188[1][lane][info->clock_speed_index];
+		  }
+
+		info->training.lane_timings[0][channel][slot][rank][lane] = u8_FFFD1218[info->clock_speed_index];
+		info->training.lane_timings[1][channel][slot][rank][lane] = 256;
+
+		for (tm_reg = 2; tm_reg < 4; tm_reg++)
+		  info->training.lane_timings[tm_reg][channel][slot][rank][lane] = u8_FFFD1240[channel][extended_silicon_revision][lane][2 * slot + rank][info->clock_speed_index]
+		    + info->max4048[channel]
+		    + u8_FFFD0C78[channel][extended_silicon_revision][info->mode4030[channel]][slot][rank][info->clock_speed_index]
+		    + card_timing;
+		for (tm_reg = 0; tm_reg < 4; tm_reg++)
+		    write_500 (info, channel, info->training.lane_timings[tm_reg][channel][slot][rank][lane],
+			       get_timing_register_addr (lane, tm_reg, slot, rank),
+			       9, 0);
+	      }
+
+	    card_timing_2 = 0;
+	    if (!(extended_silicon_revision != 4
+		  || (info->populated_ranks_mask[channel] & 5) == 5))
+	      {
+		if ((info->spd[channel][slot][REFERENCE_RAW_CARD_USED] & 0x1F) == 3)
+		  card_timing_2 = u16_FFFE0EB8[0][info->clock_speed_index];
+		if ((info->spd[channel][slot][REFERENCE_RAW_CARD_USED] & 0x1F) == 5)
+		  card_timing_2 = u16_FFFE0EB8[1][info->clock_speed_index];
+	      }
+
+	    for (i = 0; i < 3; i++)
+	      write_500 (info, channel, (card_timing_2 + info->max4048[channel]
+				   + u8_FFFD0EF8[channel][extended_silicon_revision][info->mode4030[channel]][info->clock_speed_index]),
+			 u16_fffd0c50[i][slot][rank], 8, 1);
+	    write_500 (info, channel, (info->max4048[channel] + u8_FFFD0C78[channel][extended_silicon_revision][info->mode4030[channel]][slot][rank][info->clock_speed_index]),
+		       u16_fffd0c70[slot][rank], 7, 1);
+	  }
+      if (!info->populated_ranks_mask[channel])
+	continue;
+      for (i = 0; i < 3; i++)
+	write_500 (info, channel, (info->max4048[channel] + info->avg4044[channel]
+			     + u8_FFFD17E0[channel][extended_silicon_revision][info->mode4030[channel]][info->clock_speed_index]),
+		   u16_fffd0c68[i], 8, 1);
+    }
+}
+
+static unsigned int
+fsbcycle_ps (struct raminfo *info)
+{
+  return 900000 / info->fsb_frequency;
+}
+
+/* The time of DDR transfer in ps.  */
+static unsigned int
+halfcycle_ps (struct raminfo *info)
+{
+  return 3750 / (info->clock_speed_index + 3);
+}
+
+/* The time of clock cycle in ps.  */
+static unsigned int
+cycle_ps (struct raminfo *info)
+{
+  return 2 * halfcycle_ps (info);
+}
+
+/* Frequency in 1.(1)=10/9 MHz units. */
+static unsigned
+frequency_11 (struct raminfo *info)
+{
+  return (info->clock_speed_index + 3) * 120;
+}
+
+/* Frequency in 0.1 MHz units. */
+static unsigned
+frequency_01 (struct raminfo *info)
+{
+  return 100 * frequency_11 (info) / 9;
+}
+
+static unsigned
+ps_to_halfcycles (struct raminfo *info, unsigned int ps)
+{
+  return (frequency_11 (info) * 2) * ps / 900000;
+}
+
+static unsigned
+ns_to_cycles (struct raminfo *info, unsigned int ns)
+{
+  return (frequency_11 (info)) * ns / 900;
+}
+
+static void
+compute_derived_timings(struct raminfo *info)
+{
+  unsigned channel, slot, rank;
+  int extended_silicon_revision;
+  int some_delay_1_ps;
+  int some_delay_2_ps;
+  int some_delay_2_halfcycles_ceil;
+  int some_delay_2_halfcycles_floor;
+  int some_delay_3_ps;
+  int some_delay_3_halfcycles;
+  int some_delay_3_ps_rounded;
+  int some_delay_1_cycle_ceil;
+  int some_delay_1_cycle_floor;
+
+  some_delay_3_halfcycles = 0;
+  some_delay_3_ps_rounded = 0;
+  extended_silicon_revision = info->silicon_revision;
+  if (!info->silicon_revision)
+    for (channel = 0; channel < NUM_CHANNELS; channel++)
+      for (slot = 0; slot < NUM_SLOTS; slot++)
+	if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3)
+	  extended_silicon_revision = 4;
+  if (info->board_lane_delay[7] < 5)
+    info->board_lane_delay[7] = 5;
+  info->revision_flag_1 = 2;
+  if ( info->silicon_revision == 2 || info->silicon_revision == 3 )
+    info->revision_flag_1 = 0;
+  if (info->revision < 16)
+    info->revision_flag_1 = 0;
+
+  if (info->revision < 8)
+    info->revision_flag_1 = 0;
+  if (info->revision >= 8 && (info->silicon_revision == 0
+			      || info->silicon_revision == 1))
+    some_delay_2_ps = 735;
+  else
+    some_delay_2_ps = 750;
+
+  if (info->revision >= 0x10 && (info->silicon_revision == 0
+			      || info->silicon_revision == 1))
+    some_delay_1_ps = 3929;
+  else
+    some_delay_1_ps = 3490;
+
+  some_delay_1_cycle_floor = some_delay_1_ps / cycle_ps (info);
+  some_delay_1_cycle_ceil = some_delay_1_ps / cycle_ps (info);
+  if (some_delay_1_ps % cycle_ps (info))
+    some_delay_1_cycle_ceil++;
+  else
+    some_delay_1_cycle_floor--;
+  info->some_delay_1_cycle_floor = some_delay_1_cycle_floor;
+  if (info->revision_flag_1)
+    some_delay_2_ps = halfcycle_ps (info) >> 6;
+  some_delay_2_ps += max (some_delay_1_ps - 30, 2 * halfcycle_ps (info) * (some_delay_1_cycle_ceil - 1) + 1000) + 375;
+  some_delay_3_ps = halfcycle_ps (info) - some_delay_2_ps % halfcycle_ps (info);
+  if (info->revision_flag_1)
+    {
+      if (some_delay_3_ps < 150)
+	some_delay_3_halfcycles = 0;
+      else
+	some_delay_3_halfcycles = (some_delay_3_ps << 6) / halfcycle_ps (info);
+      some_delay_3_ps_rounded = halfcycle_ps (info) * some_delay_3_halfcycles >> 6;
+    }
+  some_delay_2_halfcycles_ceil = (some_delay_2_ps + halfcycle_ps (info) - 1) / halfcycle_ps (info) - 2 * (some_delay_1_cycle_ceil - 1);
+  if (info->revision_flag_1 && some_delay_3_ps < 150)
+    some_delay_2_halfcycles_ceil++;
+  some_delay_2_halfcycles_floor = some_delay_2_halfcycles_ceil;
+  if (info->revision < 0x10)
+    some_delay_2_halfcycles_floor = some_delay_2_halfcycles_ceil - 1;
+  if (!info->revision_flag_1)
+    some_delay_2_halfcycles_floor++;
+  info->some_delay_2_halfcycles_ceil = some_delay_2_halfcycles_ceil;
+  info->some_delay_3_ps_rounded = some_delay_3_ps_rounded;
+  if ((info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0])
+       || (info->populated_ranks[1][0][0] && info->populated_ranks[1][1][0]))
+    info->max_slots_used_in_channel = 2;
+  else
+    info->max_slots_used_in_channel = 1;
+  for (channel = 0; channel < 2; channel++)
+    write_mchbar32 (0x244 + (channel << 10), ((info->revision < 8) ? 1 : 0x200)
+		    | ((2 - info->max_slots_used_in_channel) << 17) | (channel << 21) | (info->some_delay_1_cycle_floor << 18) | 0x9510);
+  if (info->max_slots_used_in_channel == 1)
+    {
+      info->mode4030[0] = (count_ranks_in_channel (info, 0) == 2); 
+      info->mode4030[1] = (count_ranks_in_channel (info, 1) == 2);
+    }
+  else
+    {
+      info->mode4030[0] = ((count_ranks_in_channel (info, 0) == 1) || (count_ranks_in_channel (info, 0) == 2)) ? 2 : 3; /* 2 if 1 or 2 ranks */
+      info->mode4030[1] = ((count_ranks_in_channel (info, 1) == 1) || (count_ranks_in_channel (info, 1) == 2)) ? 2 : 3;
+    }
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      int max_of_unk;
+      int min_of_unk_2;
+
+      int i, count;
+      int sum;
+
+      if (!info->populated_ranks_mask[channel])
+	continue;
+
+      max_of_unk = 0;
+      min_of_unk_2 = 32767;
+
+      sum = 0;
+      count = 0;
+      for (i = 0; i < 3; i++)
+	{
+	  int unk1;
+	  if (info->revision < 8)
+	    unk1 = u8_FFFD1891[0][channel][info->clock_speed_index][i];
+	  else if (!(info->revision >= 0x10 || info->revision_flag_1))
+	    unk1 = u8_FFFD1891[1][channel][info->clock_speed_index][i];
+	  else
+	    unk1 = 0;
+	  for (slot = 0; slot < NUM_SLOTS; slot++)
+	    for (rank = 0; rank < NUM_RANKS; rank++)
+	      {
+		int a = 0;
+		int b = 0;
+
+		if (!info->populated_ranks[channel][slot][rank])
+		  continue;
+		if (extended_silicon_revision == 4 && (info->populated_ranks_mask[channel] & 5) != 5)
+		  {
+		    if ( (info->spd[channel][slot][REFERENCE_RAW_CARD_USED] & 0x1F) == 3 )
+		      {
+			a = u16_ffd1178[0][info->clock_speed_index];
+			b = u16_fe0eb8[0][info->clock_speed_index];
+		      }
+		    else if ( (info->spd[channel][slot][REFERENCE_RAW_CARD_USED] & 0x1F) == 5 )
+		      {
+			a = u16_ffd1178[1][info->clock_speed_index];
+			b = u16_fe0eb8[1][info->clock_speed_index];
+		      }
+		  }
+		min_of_unk_2 = min (min_of_unk_2, a);
+		min_of_unk_2 = min (min_of_unk_2, b);
+		if (rank == 0)
+		  {
+		    sum += a;
+		    count++;
+		  }
+		{
+		  int t;
+		  t = b + u8_FFFD0EF8[channel][extended_silicon_revision][info->mode4030[channel]][info->clock_speed_index];
+		  if (unk1 >= t)
+		    max_of_unk = max (max_of_unk, unk1 - t);
+		}
+	      }
+	  {
+	    int t = u8_FFFD17E0[channel][extended_silicon_revision][info->mode4030[channel]][info->clock_speed_index] + min_of_unk_2;
+	    if (unk1 >= t)
+	      max_of_unk = max (max_of_unk, unk1 - t);
+	  }
+	}
+
+      info->avg4044[channel] = sum / count;
+      info->max4048[channel] = max_of_unk;
+    }
+}
+
+static void jedec_read(struct raminfo *info, 
+		       int channel, int slot, int rank,
+		       int total_rank, u8 addr3, unsigned int value)
+{
+  /* Handle mirrored mapping.  */
+  if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
+    addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | ((addr3 >> 1) & 0x10);
+  write_mchbar8 (0x271, addr3 | (read_mchbar8 (0x271) & 0xC1));
+  write_mchbar8 (0x671, addr3 | (read_mchbar8 (0x671) & 0xC1));
+
+  /* Handle mirrored mapping.  */
+  if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
+    value = (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8) << 1);
+
+  read32 ((value << 3) | (total_rank << 28));
+
+  write_mchbar8 (0x271, (read_mchbar8 (0x271) & 0xC3) | 2);
+  write_mchbar8 (0x671, (read_mchbar8 (0x671) & 0xC3) | 2);
+
+  read32 (total_rank << 28);
+}
+
+enum
+  {
+    MR1_RZQ12 = 512,
+    MR1_RZQ2 = 64,
+    MR1_RZQ4 = 4,
+    MR1_ODS34OHM  = 2
+  };
+
+enum
+  {
+    MR0_BT_INTERLEAVED = 8,
+    MR0_DLL_RESET_ON = 256
+  };
+
+enum
+  {
+    MR2_RTT_WR_DISABLED = 0,
+    MR2_RZQ2 = 1 << 10
+  };
+
+static void 
+jedec_init (struct raminfo *info)
+{
+  int write_recovery;
+  int channel, slot, rank;
+  int total_rank;
+  int dll_on;
+  int self_refresh_temperature;
+  int auto_self_refresh;
+
+  auto_self_refresh = 1;
+  self_refresh_temperature = 1;
+  if (info->board_lane_delay[3] <= 10)
+    {
+      if (info->board_lane_delay[3] <= 8)
+	write_recovery = info->board_lane_delay[3] - 4;
+      else
+	write_recovery = 5;
+    }
+  else
+    {
+      write_recovery = 6;
+    }
+  FOR_POPULATED_RANKS
+    {
+      auto_self_refresh &= (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1;
+      self_refresh_temperature &= info->spd[channel][slot][THERMAL_AND_REFRESH] & 1;
+    }
+  if (auto_self_refresh == 1)
+    self_refresh_temperature = 0;
+
+  dll_on = ((info->silicon_revision != 2 && info->silicon_revision != 3)
+		 || (info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0])
+		 || (info->populated_ranks[1][0][0] && info->populated_ranks[1][1][0]));
+
+  total_rank = 0;
+
+  for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) 
+    {
+      int rtt, rtt_wr = MR2_RTT_WR_DISABLED;
+      int rzq_reg58e;
+
+      if (info->silicon_revision == 2 || info->silicon_revision == 3)
+	{
+	  rzq_reg58e = 64;
+	  rtt = MR1_RZQ2;
+	  if (info->clock_speed_index != 0)
+	    {
+	      rzq_reg58e = 4;
+	      if (info->populated_ranks_mask[channel] == 3)
+		rtt = MR1_RZQ4;
+	    }
+	}
+      else
+	{
+	  if ((info->populated_ranks_mask[channel] & 5) == 5)
+	    {
+	      rtt = MR1_RZQ12;
+	      rzq_reg58e = 64;
+	      rtt_wr = MR2_RZQ2;
+	    }
+	  else
+	    {
+	      rzq_reg58e = 4;
+	      rtt = MR1_RZQ4;
+	    }
+	}
+
+      write_mchbar16 (0x588 + (channel << 10), 0x0);
+      write_mchbar16 (0x58a + (channel << 10), 0x4);
+      write_mchbar16 (0x58c + (channel << 10), rtt | MR1_ODS34OHM);
+      write_mchbar16 (0x58e + (channel << 10), rzq_reg58e | 0x82);
+      write_mchbar16 (0x590 + (channel << 10), 0x1282);
+
+      for (slot = 0; slot < NUM_SLOTS; slot++)
+	for (rank = 0; rank < NUM_RANKS; rank++)
+	  if (info->populated_ranks[channel][slot][rank])
+	    {
+	      jedec_read (info, channel, slot, rank,
+			 total_rank, 0x28,
+			  rtt_wr | (info->clock_speed_index << 3)
+			  | (auto_self_refresh << 6) | (self_refresh_temperature << 7));
+	      jedec_read (info, channel, slot, rank, total_rank, 0x38, 0);
+	      jedec_read (info, channel, slot, rank,
+			  total_rank, 0x18, rtt | MR1_ODS34OHM);
+	      jedec_read (info, channel, slot, rank,
+			  total_rank, 6,
+			  (dll_on << 12) | (write_recovery << 9)
+			  | ((info->cas_latency - 4) << 4) | MR0_BT_INTERLEAVED | MR0_DLL_RESET_ON);
+	      total_rank++;
+	    }
+    }
+}
+
+static void pm_wait (u16 us)
+{
+  u32 base = read_acpi32 (8);
+  u32 ticks = (us * 358) / 100;
+  while (((read_acpi32 (8) - base) & 0xffffff) < ticks);
+}
+
+static void program_modules_memory_map (struct raminfo *info, int pre_jedec)
+{
+  unsigned channel, slot, rank;
+  unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */
+  unsigned int channel_0_non_interleaved;
+
+  FOR_ALL_RANKS
+    {
+      if (info->populated_ranks[channel][slot][rank])
+	{
+	  total_mb[channel] += pre_jedec ? 256 : (256 << info->density[channel][slot] >> info->is_x16_module[channel][slot]);
+	  write_mchbar8 (0x208 + rank +  2 * slot + (channel << 10), 
+			 (pre_jedec ? (1 | ((1 + 1) << 1))  : (info->is_x16_module[channel][slot] | ((info->density[channel][slot] + 1) << 1))) | 0x80);
+	}
+      write_mchbar16 (0x200 + (channel << 10) + 4 * slot + 2 * rank, total_mb[channel] >> 6);
+    }
+
+  info->total_memory_mb = total_mb[0] + total_mb[1];
+
+  info->interleaved_part_mb = pre_jedec ? 0 : 2 * min (total_mb[0], total_mb[1]);
+  info->non_interleaved_part_mb = total_mb[0] + total_mb[1] - info->interleaved_part_mb;
+  channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2;
+  write_mchbar32 (0x100, channel_0_non_interleaved | (info->non_interleaved_part_mb << 16));
+  if (!pre_jedec)
+    write_mchbar16 (0x104, info->interleaved_part_mb);
+}
+
+static void program_board_delay(struct raminfo *info)
+{
+  int cas_latency_shift;
+  int some_delay_ns;
+  int some_delay_3_half_cycles;
+
+  unsigned channel, i;
+  int high_multiplier;
+  int lane_3_delay;
+  int cas_latency_derived;
+
+  high_multiplier = 0;
+  some_delay_ns = 200;
+  some_delay_3_half_cycles = 4;
+  cas_latency_shift = info->silicon_revision == 0 || info->silicon_revision == 1 ? 1 : 0;
+  if (info->revision < 8)
+    {
+      some_delay_ns = 600;
+      cas_latency_shift = 0;
+    }
+  {
+    int speed_bit;
+    speed_bit = ((info->clock_speed_index > 1 || (info->silicon_revision != 2 && info->silicon_revision != 3))) ^ (info->revision >= 0x10);
+    write_500 (info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e, 3, 1);
+    write_500 (info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e, 3, 1);
+    if (info->revision >= 0x10 && info->clock_speed_index <= 1 && (info->silicon_revision == 2 || info->silicon_revision == 3))
+      rmw_1d0 (0x116, 5, 2, 4, 1);
+  }
+  write_mchbar32 (0x120, (1 << (info->max_slots_used_in_channel + 28)) | 0x188e7f9f);
+
+  write_mchbar8 (0x124, info->board_lane_delay[4] + ((frequency_01 (info) + 999) / 1000)); 
+  write_mchbar16 (0x125, 0x1360);
+  write_mchbar8 (0x127, 0x40);
+  if (info->fsb_frequency < frequency_11 (info) / 2)
+    {
+      unsigned some_delay_2_half_cycles;
+      high_multiplier = 1;
+      some_delay_2_half_cycles = ps_to_halfcycles (info, 
+						   ((3 * fsbcycle_ps (info)) >> 1) + (halfcycle_ps (info) * reg178_min[info->clock_speed_index] >> 6)
+						   + 4 * halfcycle_ps (info)
+						   + 2230);
+      some_delay_3_half_cycles = min ((some_delay_2_half_cycles + (frequency_11 (info) * 2) * (28 - some_delay_2_half_cycles) /
+				       (frequency_11 (info) * 2 - 4 * (info->fsb_frequency))) >> 3, 7);
+    }
+  if (read_mchbar8 (0x2ca9) & 1)
+    some_delay_3_half_cycles = 3;
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_mchbar32 (0x220 + (channel << 10), read_mchbar32 (0x220 + (channel << 10)) | 0x18001117);
+      write_mchbar32 (0x224 + (channel << 10), (info->max_slots_used_in_channel - 1)
+		      | ((info->cas_latency
+			  - 5 - info->clock_speed_index) << 21)
+		      | ((info->max_slots_used_in_channel + info->cas_latency - cas_latency_shift - 4) << 16)
+		      | ((info->cas_latency - cas_latency_shift - 4) << 26)
+		      | ((info->cas_latency - info->clock_speed_index + info->max_slots_used_in_channel - 6) << 8));
+      write_mchbar32 (0x228 + (channel << 10), info->max_slots_used_in_channel);
+      write_mchbar8 (0x239 + (channel << 10), 32);
+      write_mchbar32 (0x248 + (channel << 10), (high_multiplier << 24) | (some_delay_3_half_cycles << 25) | 0x840000);
+      write_mchbar32 (0x278 + (channel << 10), 0xc362042);
+      write_mchbar32 (0x27c + (channel << 10), 0x8b000062);
+      write_mchbar32 (0x24c + (channel << 10), ((!!info->clock_speed_index) << 17) | (((2 + info->clock_speed_index - (!!info->clock_speed_index))) << 12) | 0x10200);
+
+      write_mchbar8 (0x267 + (channel << 10), 0x4);
+      write_mchbar16 (0x272 + (channel << 10), 0x155);
+      write_mchbar32 (0x2bc + (channel << 10),
+		      (read_mchbar32 (0x2bc + (channel << 10)) & 0xFF000000)
+		      | 0x707070);
+
+      write_500 (info, channel,
+		 ((!info->populated_ranks[channel][1][1])
+		  | (!info->populated_ranks[channel][1][0] << 1)
+		  | (!info->populated_ranks[channel][0][1] << 2)
+		  | (!info->populated_ranks[channel][0][0] << 3)),
+		 0x4c9, 4, 1);
+    }
+
+  write_mchbar8 (0x2c4, ((1 + (info->clock_speed_index != 0)) << 6) | 0xC);
+  {
+    u8 freq_divisor = 2; 
+    if (info->fsb_frequency == frequency_11 (info))
+      freq_divisor = 3;
+    else if (2 * info->fsb_frequency < 3 * (frequency_11 (info) / 2) )
+      freq_divisor = 1;
+    else
+      freq_divisor = 2;
+    write_mchbar32 (0x2c0, (freq_divisor << 11) | 0x6009c400);
+  }
+
+  if ( info->board_lane_delay[3] <= 10 )
+    {
+      if ( info->board_lane_delay[3] <= 8 )
+	lane_3_delay = info->board_lane_delay[3];
+      else
+	lane_3_delay = 10;
+    }
+  else
+    {
+      lane_3_delay = 12;
+    }
+  cas_latency_derived = info->cas_latency - info->clock_speed_index + 2;
+  if (info->clock_speed_index > 1)
+    cas_latency_derived++;
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_mchbar32 (0x240 + (channel << 10), ((info->clock_speed_index == 0) * 0x11000) | 0x1002100 | ((2 + info->clock_speed_index) << 4) | (info->cas_latency - 3));
+      write_500 (info, channel, (info->clock_speed_index << 1) | 1, 0x609, 6, 1);
+      write_500 (info, channel, info->clock_speed_index + 2 * info->cas_latency - 7, 0x601, 6, 1);
+		
+      write_mchbar32 (0x250 + (channel << 10), ((lane_3_delay + info->clock_speed_index + 9) << 6)
+		      | (info->board_lane_delay[7] << 2) | (info->board_lane_delay[4] << 16) | (info->board_lane_delay[1] << 25) | (info->board_lane_delay[1] << 29) | 1);
+      write_mchbar32 (0x254 + (channel << 10), (info->board_lane_delay[1] >> 3) | ((info->board_lane_delay[8] + 4 * info->use_ecc) << 6) | 0x80 |
+		      (info->board_lane_delay[6] << 1) | (info->board_lane_delay[2] << 28) | (cas_latency_derived << 16) | 0x4700000);
+      write_mchbar32 (0x258 + (channel << 10), ((info->board_lane_delay[5] + info->clock_speed_index + 9) << 12) | ((info->clock_speed_index - info->cas_latency + 12) << 8)
+		      | (info->board_lane_delay[2] << 17) | (info->board_lane_delay[4] << 24) | 0x47);
+      write_mchbar32 (0x25c + (channel << 10), (info->board_lane_delay[1] << 1) | (info->board_lane_delay[0] << 8) | 0x1da50000);
+      write_mchbar8 (0x264 + (channel << 10), 0xff);
+      write_mchbar8 (0x5f8 + (channel << 10), (cas_latency_shift << 3) | info->use_ecc);
+    }
+
+  program_modules_memory_map (info, 1);
+
+  write_mchbar16 (0x610, (min (ns_to_cycles (info, some_delay_ns) / 2, 127) << 9)
+		  | (read_mchbar16(0x610) & 0x1C3) | 0x3C);
+  write_mchbar16 (0x612, read_mchbar16(0x612) | 0x100);
+  write_mchbar16 (0x214, read_mchbar16 (0x214) | 0x3E00);
+  for (i = 0; i < 8; i++)
+    {
+      pci_mm_write32 (QUICKPATH_BUS, 0, 1, 0x80 + 4 * i, (info->total_memory_mb - 64) | !i | 2);
+      pci_mm_write32 (QUICKPATH_BUS, 0, 1, 0xc0 + 4 * i, 0);
+    }
+}
+
+#define BETTER_MEMORY_MAP 0
+
+static void
+program_total_memory_map (struct raminfo *info)
+{
+  unsigned int TOM, TOLUD, TOUUD;
+  unsigned int quickpath_reserved;
+  unsigned int REMAPbase;
+  unsigned int uma_base_igd;
+  unsigned int uma_base_gtt;
+  int memory_remap;
+  unsigned int memory_map[8];
+  int i;
+  unsigned int current_limit;
+  unsigned int tseg_base;
+  int uma_size_igd = 0, uma_size_gtt = 0;
+
+  memset (memory_map, 0, sizeof (memory_map));
+
+#if REAL
+  if (info->uma_enabled)
+    {
+      u16 t = pci_mm_read16 (NORTHBRIDGE, D0F0_GGC);
+      gav (t);
+      const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
+      /* Igd memory */
+      const int uma_sizes_igd[16] = 
+	{
+	  0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 
+	};
+
+      uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];
+      uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
+    }
+#endif
+
+  TOM = info->total_memory_mb;
+  if (TOM == 4096)
+    TOM = 4032;
+  TOUUD = ALIGN_DOWN (TOM - info->memory_reserved_for_heci_mb, 64);
+  TOLUD = ALIGN_DOWN (min (3072
+			   + ALIGN_UP(uma_size_igd + uma_size_gtt, 64)
+			   , TOUUD), 64);
+  memory_remap = 0;
+  if (TOUUD - TOLUD > 64)
+    {
+      memory_remap = 1;
+      REMAPbase = max (4096, TOUUD);
+      TOUUD = TOUUD - TOLUD + 4096;
+    }
+  if (TOUUD > 4096)
+    memory_map[2] = TOUUD | 1;
+  quickpath_reserved = 0;
+
+  {
+    u32 t;
+
+    gav (t = pci_mm_read32 (QUICKPATH_BUS, 0, 1, 0x68));
+    if (t & 0x800)
+      quickpath_reserved = (1 << find_lowest_bit_set32 (t >> 20));
+  }
+  if (memory_remap)
+    TOUUD -= quickpath_reserved;
+
+#if !REAL
+  if (info->uma_enabled)
+    {
+      u16 t = pci_mm_read16 (NORTHBRIDGE, D0F0_GGC);
+      gav (t);
+      const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
+      /* Igd memory */
+      const int uma_sizes_igd[16] = 
+	{
+	  0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 
+	};
+
+      uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];
+      uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
+    }
+#endif
+
+  uma_base_igd = TOLUD - uma_size_igd;
+  uma_base_gtt = uma_base_igd - uma_size_gtt;
+  tseg_base = ALIGN_DOWN (uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20);
+  if (!memory_remap)
+    tseg_base -= quickpath_reserved;
+  tseg_base = ALIGN_DOWN (tseg_base, 8);
+
+  pci_mm_write16 (NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4);
+  pci_mm_write16 (NORTHBRIDGE, D0F0_TOM, TOM >> 6);
+  if (memory_remap)
+    {
+      pci_mm_write16 (NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6);
+      pci_mm_write16 (NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6);
+    }
+  pci_mm_write16 (NORTHBRIDGE, D0F0_TOUUD, TOUUD);
+
+  if (info->uma_enabled)
+    {
+      pci_mm_write32 (NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20);
+      pci_mm_write32 (NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20);
+    }
+  pci_mm_write32 (NORTHBRIDGE, TSEG, tseg_base << 20);
+
+  current_limit = 0;
+  memory_map[0] = ALIGN_DOWN (uma_base_gtt, 64) | 1;
+  memory_map[1] = 4096;
+  for (i = 0; i < ARRAY_SIZE (memory_map); i++)
+    {
+      current_limit = max (current_limit, memory_map[i] & ~1);
+      pci_mm_write32 (QUICKPATH_BUS, 0, 1, 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN (current_limit - 1, 64) | 2);
+      pci_mm_write32 (QUICKPATH_BUS, 0, 1, 4 * i + 0xc0, 0);
+    }
+}
+
+static void
+collect_system_info (struct raminfo *info)
+{
+  u32 capid0[3];
+  int i;
+  unsigned channel;
+
+  /* Wait for some bit, maybe TXT clear. */
+  while (!(read8(0xfed40000) & (1 << 7))) ;
+
+  if (!info->heci_bar)
+    gav (info->heci_bar = pci_mm_read32 (HECIDEV, HECIBAR) & 0xFFFFFFF8);
+  if (!info->memory_reserved_for_heci_mb)
+    {
+      /* Wait for ME to be ready */
+      intel_early_me_init ();
+      info->memory_reserved_for_heci_mb = intel_early_me_uma_size ();
+    }
+
+  for (i = 0; i < 3; i++)
+    gav (capid0[i] = pci_mm_read32 (NORTHBRIDGE, D0F0_CAPID0 | (i << 2)));
+  gav (info->revision = pci_mm_read8 (NORTHBRIDGE, PCI_REVISION_ID));
+  info->max_supported_clock_speed_index = (~capid0[1] & 7);
+
+  if ((capid0[1] >> 11) & 1)
+    info->uma_enabled = 0;
+  else
+    gav (info->uma_enabled = pci_mm_read8 (NORTHBRIDGE, D0F0_DEVEN) & 8);
+  /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff*/
+  info->silicon_revision = 0;
+
+  if (capid0[2] & 2)
+    {
+      info->silicon_revision = 0;
+      info->max_supported_clock_speed_index = 2;
+      for (channel = 0; channel < NUM_CHANNELS; channel++)
+	if (info->populated_ranks[channel][0][0] && (info->spd[channel][0][MODULE_TYPE] & 0xf) == 3)
+	  {
+	    info->silicon_revision = 2;
+	    info->max_supported_clock_speed_index = 1;
+	  }
+    }
+  else
+    {
+      switch (((capid0[2] >> 18) & 1) + 2 * ((capid0[1] >> 3) & 1) )
+	{
+	case 1:
+	case 2:
+	  info->silicon_revision = 3;
+	  break;
+	case 3:
+	  info->silicon_revision = 0;
+	  break;
+	case 0:
+	  info->silicon_revision = 2;
+	  break;
+	}
+      switch (pci_mm_read16 (NORTHBRIDGE, PCI_DEVICE_ID))
+	{
+	case 0x40:
+	  info->silicon_revision = 0;
+	  break;
+	case 0x48:
+	  info->silicon_revision = 1;
+	  break;
+	}
+    }
+}
+
+static void
+write_training_data (struct raminfo *info)
+{
+  int tm, channel, slot,rank, lane;
+  if (info->revision < 8)
+    return;
+
+  for (tm = 0; tm < 4; tm++)
+    for (channel = 0; channel < NUM_CHANNELS; channel++)
+      for (slot = 0; slot < NUM_SLOTS; slot++)
+      for (rank = 0; rank < NUM_RANKS; rank++)
+	for (lane = 0; lane < 9; lane++)
+	  write_500 (info, channel, info->cached_training->lane_timings[tm][channel][slot][rank][lane],
+		     get_timing_register_addr (lane, tm, slot, rank), 9, 0);
+  write_1d0 (info->cached_training->reg_178, 0x178, 7, 1);
+  write_1d0 (info->cached_training->reg_10b, 0x10b, 6, 1);
+}
+
+static void 
+enable_hpet (void)
+{
+#if REAL
+  u32 reg32;
+
+  /* Move HPET to default address 0xfed00000 and enable it */
+  reg32 = RCBA32(HPTC);
+  reg32 |= (1 << 7); // HPET Address Enable
+  reg32 &= ~(3 << 0);
+  RCBA32(HPTC) = reg32;
+#else
+  write32 (DEFAULT_RCBA | HPTC, 0x80);
+#endif
+}
+
+static void
+dump_timings (struct raminfo *info)
+{
+#if REAL
+  int channel, slot, rank, lane, i;
+  printk (BIOS_DEBUG, "Timings:\n");
+  FOR_POPULATED_RANKS
+    {
+      printk (BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank);
+      for (lane = 0; lane < 9; lane++)
+	{
+	  printk (BIOS_DEBUG, "lane %d: ", lane);
+	  for (i = 0; i < 4; i++)
+	    {
+	      printk (BIOS_DEBUG, "%x (%x) ", read_500_bypass (info, channel,
+							       get_timing_register_addr (lane, i, slot, rank), 9),
+		      info->training.lane_timings[i][channel][slot][rank][lane]);
+	    }
+	  printk (BIOS_DEBUG, "\n");
+	}
+    }
+  printk (BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0 (0x178, 7), info->training.reg_178);
+  printk (BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0 (0x10b, 6), info->training.reg_10b);
+#endif
+}
+
+static void
+save_timings (struct raminfo *info)
+{
+#if CONFIG_EARLY_CBMEM_INIT
+        struct ram_training train;
+	struct mrc_data_container *mrcdata;
+	int output_len = ALIGN(sizeof (train), 16);
+	int channel, slot, rank, lane, i;
+
+	train = info->training;
+	FOR_POPULATED_RANKS
+	  for (lane = 0; lane < 9; lane++)
+	    for (i = 0; i < 4; i++)
+	      train.lane_timings[i][channel][slot][rank][lane] = read_500 (info, channel,
+									   get_timing_register_addr (lane, i, slot, rank), 9);
+	train.reg_178 = read_1d0 (0x178, 7);
+	train.reg_10b = read_1d0 (0x10b, 6);
+
+	/* Save the MRC S3 restore data to cbmem */
+	cbmem_initialize();
+	mrcdata = cbmem_add
+		(CBMEM_ID_MRCDATA,
+		 output_len + sizeof(struct mrc_data_container));
+
+	printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
+	       &train, mrcdata, output_len);
+
+	mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
+	mrcdata->mrc_data_size = output_len;
+	mrcdata->reserved = 0;
+	memcpy(mrcdata->mrc_data, &train,
+	       sizeof (train));
+
+	/* Zero the unused space in aligned buffer. */
+	if (output_len > sizeof (train))
+		memset(mrcdata->mrc_data+sizeof (train), 0,
+		       output_len - sizeof (train));
+
+	mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
+						    mrcdata->mrc_data_size);
+#endif
+}
+
+#if REAL
+static const struct ram_training *
+get_cached_training (void)
+{
+  struct mrc_data_container *cont;
+  cont = find_current_mrc_cache();
+  if (!cont)
+    return 0;
+  return (void *) cont->mrc_data;
+}
+#endif
+
+/* FIXME: add timeout.  */
+static void
+wait_heci_ready (void)
+{
+  while (!(read32 (DEFAULT_HECIBAR | 0xc) & 8)); // = 0x8000000c
+  write32 ((DEFAULT_HECIBAR | 0x4), (read32 (DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc);
+}
+
+/* FIXME: add timeout.  */
+static void
+wait_heci_cb_avail (int len)
+{
+  union
+  {
+    struct mei_csr csr;
+    u32 raw;
+  } csr;
+
+  while (!(read32 (DEFAULT_HECIBAR | 0xc) & 8));
+
+  do
+    csr.raw = read32 (DEFAULT_HECIBAR | 0x4);
+  while (len > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr));
+}
+
+static void
+send_heci_packet (struct mei_header *head, u32 *payload)
+{
+  int len = (head->length + 3) / 4;
+  int i;
+
+  wait_heci_cb_avail (len + 1);
+
+  /* FIXME: handle leftovers correctly.  */
+  write32 (DEFAULT_HECIBAR | 0, *(u32 *)head);
+  for (i = 0; i < len - 1; i++)
+    write32 (DEFAULT_HECIBAR | 0, payload[i]);
+
+  write32 (DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1));
+  write32 (DEFAULT_HECIBAR | 0x4, read32 (DEFAULT_HECIBAR | 0x4) | 0x4);
+}
+
+static void
+send_heci_message (u8 *msg, int len, u8 hostaddress, u8 clientaddress)
+{
+  struct mei_header head;
+  int maxlen;
+
+  wait_heci_ready ();
+  maxlen = (read32 (DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4;
+
+  while (len)
+    {
+      int cur = len;
+      if (cur > maxlen)
+	{
+	  cur = maxlen;
+	  head.is_complete = 0;
+	}
+      else
+	head.is_complete = 1;
+      head.length = cur;
+      head.reserved = 0;
+      head.client_address = clientaddress;
+      head.host_address = hostaddress;
+      send_heci_packet (&head, (u32 *) msg);
+      len -= cur;
+      msg += cur;
+    }
+}
+
+/* FIXME: Add timeout.  */
+static int
+recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet, u32 *packet_size)
+{
+  union
+  {
+    struct mei_csr csr;
+    u32 raw;
+  } csr;
+  int i = 0;
+
+  write32 (DEFAULT_HECIBAR | 0x4, read32 (DEFAULT_HECIBAR | 0x4) | 2);
+  do
+    {
+      csr.raw = read32 (DEFAULT_HECIBAR | 0xc);
+#if !REAL
+      if (i++ > 346)
+	return -1;
+#endif
+    }
+  while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
+  *(u32 *)head = read32 (DEFAULT_HECIBAR | 0x8);
+  if (!head->length)
+    {
+      write32 (DEFAULT_HECIBAR | 0x4, read32 (DEFAULT_HECIBAR | 0x4) | 2);
+      *packet_size = 0;
+      return 0;
+    }
+  if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size)
+    {
+      *packet_size = 0;
+      return -1;
+    }
+
+  do
+    csr.raw = read32 (DEFAULT_HECIBAR | 0xc);
+  while ((head->length + 3) >> 2 > csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
+
+  for (i = 0; i < (head->length + 3) >> 2; i++)
+    packet[i++] = read32 (DEFAULT_HECIBAR | 0x8);
+  *packet_size = head->length;
+  if (!csr.csr.ready)
+    *packet_size = 0;
+  write32 (DEFAULT_HECIBAR | 0x4, read32 (DEFAULT_HECIBAR | 0x4) | 4);
+  return 0;
+}
+
+/* FIXME: Add timeout.  */
+static int
+recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size)
+{
+  struct mei_header head;
+  int current_position;
+
+  current_position = 0;
+  while (1)
+  {
+    u32 current_size;
+    current_size = *message_size - current_position;
+    if (recv_heci_packet(info, &head, message + (current_position >> 2), &current_size) == -1 )
+      break;
+    if (!current_size)
+      break;
+    current_position += current_size;
+    if (head.is_complete)
+      {
+	*message_size = current_position;
+	return 0;
+      }
+
+    if (current_position >= *message_size)
+      break;
+  }
+  *message_size = 0;
+  return -1;
+}
+
+static void
+send_heci_uma_message(struct raminfo *info)
+{
+  struct uma_reply
+  {
+    u8 group_id;
+    u8 command;
+    u8 reserved;
+    u8 result;
+    u8 field2;
+    u8 unk3[0x48 - 4 - 1];
+  }__attribute__ ((packed)) reply;
+  struct uma_message
+  {
+    u8 group_id;
+    u8 cmd;
+    u8 reserved;
+    u8 result;
+    u32 c2;
+    u64 heci_uma_addr;
+    u32 memory_reserved_for_heci_mb;
+    u16 c3;
+  } __attribute__ ((packed)) msg = {
+    0, MKHI_SET_UMA, 0, 0,
+    0x82,
+    info->heci_uma_addr,
+    info->memory_reserved_for_heci_mb,
+    0
+  };
+  u32 reply_size;
+
+  send_heci_message ((u8 *) &msg, sizeof (msg), 0, 7);
+
+  reply_size = sizeof (reply);
+  if (recv_heci_message (info, (u32 *) &reply, &reply_size) == -1)
+    return;
+
+  if (reply.command != (MKHI_SET_UMA | (1 << 7)))
+    die ("HECI init failed\n");
+}
+
+static void
+setup_heci_uma (struct raminfo *info)
+{
+  u32 reg44;
+
+  reg44 = pci_mm_read32 (HECIDEV, 0x44);  // = 0x80010020
+  info->memory_reserved_for_heci_mb = 0;
+  info->heci_uma_addr = 0;
+  if (!((reg44 & 0x10000) && !(pci_mm_read32 (HECIDEV, 0x40) & 0x20)))
+    return;
+
+  info->heci_bar =  pci_mm_read32 (HECIDEV, 0x10) & 0xFFFFFFF0;
+  info->memory_reserved_for_heci_mb = reg44 & 0x3f;
+  info->heci_uma_addr = ((u64)((((u64) pci_mm_read16 (NORTHBRIDGE, D0F0_TOM)) << 6) - info->memory_reserved_for_heci_mb)) << 20;
+
+  pci_mm_read32 (NORTHBRIDGE, DMIBAR);
+  if (info->memory_reserved_for_heci_mb)
+    {
+      write32 (DEFAULT_DMIBAR | 0x14, read32 (DEFAULT_DMIBAR | 0x14) & ~0x80);
+      write32 (DEFAULT_RCBA | 0x14, read32 (DEFAULT_RCBA | 0x14) & ~0x80);
+      write32 (DEFAULT_DMIBAR | 0x20, read32 (DEFAULT_DMIBAR | 0x20) & ~0x80);
+      write32 (DEFAULT_RCBA | 0x20, read32 (DEFAULT_RCBA | 0x20) & ~0x80);
+      write32 (DEFAULT_DMIBAR | 0x2c, read32 (DEFAULT_DMIBAR | 0x2c) & ~0x80);
+      write32 (DEFAULT_RCBA | 0x30, read32 (DEFAULT_RCBA | 0x30) & ~0x80);
+      write32 (DEFAULT_DMIBAR | 0x38, read32 (DEFAULT_DMIBAR | 0x38) & ~0x80);
+      write32 (DEFAULT_RCBA | 0x40, read32 (DEFAULT_RCBA | 0x40) & ~0x80);
+
+      write32 (DEFAULT_RCBA | 0x40, 0x87000080); // OK
+      write32 (DEFAULT_DMIBAR | 0x38, 0x87000080); // OK
+      while (read16 (DEFAULT_RCBA | 0x46) & 2 && read16 (DEFAULT_DMIBAR | 0x3e) & 2);
+    }
+
+  write_mchbar32 (0x24, 0x10000 + info->memory_reserved_for_heci_mb);
+
+  send_heci_uma_message(info);
+
+  pci_mm_write32 (HECIDEV, 0x10, 0x0);
+  pci_mm_write8 (HECIDEV, 0x4, 0x0);
+
+}
+
+static int
+have_match_ranks (struct raminfo *info, int channel, int ranks)
+{
+  int ranks_in_channel;
+  ranks_in_channel = info->populated_ranks[channel][0][0]
+    + info->populated_ranks[channel][0][1]
+    + info->populated_ranks[channel][1][0]
+    + info->populated_ranks[channel][1][1];
+
+  /* empty channel */
+  if (ranks_in_channel == 0)
+    return 1;
+
+  if (ranks_in_channel != ranks)
+    return 0;
+  /* single slot */
+  if (info->populated_ranks[channel][0][0] != info->populated_ranks[channel][1][0])
+    return 1;
+  if (info->populated_ranks[channel][0][1] != info->populated_ranks[channel][1][1])
+    return 1;
+  if (info->is_x16_module[channel][0] != info->is_x16_module[channel][1])
+    return 0;
+  if (info->density[channel][0] != info->density[channel][1])
+    return 0;
+  return 1;
+}
+
+#define WTF1 1
+
+static void
+read_4090 (struct raminfo *info)
+{
+  int i, channel, slot, rank, lane;
+  for (i = 0; i < 2; i++)
+    for (slot = 0; slot < NUM_SLOTS; slot++)
+      for (rank = 0; rank < NUM_RANKS; rank++)
+	for (lane = 0; lane < 9; lane++)
+	  info->training.lane_timings[0][i][slot][rank][lane] = 32;
+	
+  for (i = 1; i < 4; i++)
+    for (channel = 0; channel < NUM_CHANNELS; channel++)
+      for (slot = 0; slot < NUM_SLOTS; slot++)
+	for (rank = 0; rank < NUM_RANKS; rank++)
+	  for (lane = 0; lane < 9; lane++)
+	    {
+	      info->training.lane_timings[i][channel][slot][rank][lane] = read_500 (info, channel,
+								   get_timing_register_addr (lane, i, slot, rank), 9)
+		+ (i == 1) * 11; // !!!!
+	    }
+
+}
+
+static u32
+get_etalon2 (int flip, u32 addr)
+{
+  const u16 invmask[] = {
+    0xaaaa, 0x6db6, 0x4924, 0xeeee, 0xcccc, 0x8888, 0x7bde, 0x739c,
+    0x6318, 0x4210, 0xefbe, 0xcf3c, 0x8e38, 0x0c30, 0x0820
+  };
+  u32 ret;
+  u32 comp4 = addr / 480;
+  addr %= 480;
+  u32 comp1 = addr & 0xf;
+  u32 comp2 = (addr >> 4) & 1;
+  u32 comp3 = addr >> 5;
+
+  if (comp4)
+    ret = 0x1010101 << (comp4 - 1);
+  else
+    ret = 0;
+  if (flip ^ (((invmask[comp3] >> comp1) ^ comp2) & 1))
+    ret = ~ret;
+
+  return ret;
+}
+
+static void
+disable_cache (void)
+{
+  my_write_msr (MTRRphysBase_MSR (3), 0);
+  my_write_msr (MTRRphysMask_MSR (3), 0);
+}
+
+static void
+enable_cache(unsigned int base, unsigned int size)
+{
+  my_write_msr (MTRRphysBase_MSR (3), base | MTRR_TYPE_WRPROT);
+  my_write_msr (MTRRphysMask_MSR (3), 0x0000000f00000000LL
+		| ((~(ALIGN_DOWN (size + 4096, 4096) - 1) | MTRRdefTypeEn)
+		   & 0xffffffff));
+}
+
+static void
+flush_cache (u32 start, u32 size)
+{
+  u32 end;
+  u32 addr;
+
+  end = start + (ALIGN_DOWN (size + 4096, 4096));
+  for (addr = start; addr < end; addr += 64)
+    clflush (addr);
+}
+
+static void
+send_c0_signal (void)
+{
+  pci_mm_write8 (NORTHBRIDGE, 0xc0, 0x01);
+}
+
+static void
+write_testing (struct raminfo *info, int totalrank, int flip)
+{
+  int nwrites = 0;
+  /* in 8-byte units.  */
+  u32 offset;
+  u32 base;
+
+  base = totalrank << 28;
+  for (offset = 0; offset < 9 * 480; offset += 2)
+    {
+      write32 (base + offset * 8, get_etalon2 (flip, offset));
+      write32 (base + offset * 8 + 4, get_etalon2 (flip, offset));
+      write32 (base + offset * 8 + 8, get_etalon2 (flip, offset + 1));
+      write32 (base + offset * 8 + 12, get_etalon2 (flip, offset + 1));
+      nwrites += 4;
+      if (nwrites >= 320)
+	{
+	  send_c0_signal ();
+	  nwrites = 0;
+	}
+    }
+}
+
+static u8
+check_testing (struct raminfo *info, u8 total_rank, int flip)
+{
+  u8 failmask = 0;
+  int i;
+  int comp1, comp2, comp3;
+  u32 failxor[2] = { 0, 0 };
+
+  enable_cache ((total_rank << 28), 1728 * 5 * 4);
+
+  for (comp3 = 0; comp3 < 9 && failmask != 0xff; comp3++)
+    {
+      for (comp1 = 0; comp1 < 4; comp1++)
+	for (comp2 = 0; comp2 < 60; comp2++)
+	  {
+	    u32 re[4];
+	    u32 curroffset = comp3 * 8 * 60 + 2 * comp1 + 8 * comp2;
+	    read128 ((total_rank << 28) | (curroffset << 3),
+		     (u64 *) re);
+	    failxor[0] |= get_etalon2 (flip, curroffset) ^ re[0];
+	    failxor[1] |= get_etalon2 (flip, curroffset) ^ re[1];
+	    failxor[0] |= get_etalon2 (flip, curroffset | 1) ^ re[2];
+	    failxor[1] |= get_etalon2 (flip, curroffset | 1) ^ re[3];
+	  }
+      for (i = 0; i < 8; i++)
+	if ((0xff << (8 * (i % 4))) & failxor[i / 4])
+	  failmask |= 1 << i;
+    }
+  disable_cache ();
+  flush_cache ((total_rank << 28), 1728 * 5 * 4);
+  return failmask;
+}
+
+const u32 seed1[0x18] = {
+  0x3a9d5ab5, 0x576cb65b, 0x555773b6, 0x2ab772ee,
+  0x555556ee, 0x3a9d5ab5, 0x576cb65b, 0x555773b6,
+  0x2ab772ee, 0x555556ee, 0x5155a555, 0x5155a555,
+  0x5155a555, 0x5155a555, 0x3a9d5ab5, 0x576cb65b,
+  0x555773b6, 0x2ab772ee, 0x555556ee, 0x55d6b4a5,
+  0x366d6b3a, 0x2ae5ddbb, 0x3b9ddbb7, 0x55d6b4a5,
+};
+
+static u32
+get_seed2 (int a, int b)
+{
+  const u32 seed2[5] = {
+    0x55555555, 0x33333333, 0x2e555a55, 0x55555555,
+    0x5b6db6db,
+  };
+  u32 r;
+  r = seed2[(a + (a >= 10)) / 5];
+  return b ? ~r : r;
+}
+
+static int
+make_shift (int comp2, int comp5, int x)
+{
+  const u8 seed3[32] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+    0x00, 0x00, 0x38, 0x1c, 0x3c, 0x18, 0x38, 0x38, 
+    0x38, 0x38, 0x38, 0x38, 0x0f, 0x0f, 0x0f, 0x0f, 
+    0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
+  };
+
+  return (comp2 - ((seed3[comp5] >> (x & 7)) & 1)) & 0x1f;
+}
+
+static u32
+get_etalon (int flip, u32 addr)
+{
+  u32 mask_byte = 0;
+  int comp1 = (addr >> 1) & 1;
+  int comp2 = (addr >> 3) & 0x1f;
+  int comp3 = (addr >> 8) & 0xf;
+  int comp4 = (addr >> 12) & 0xf;
+  int comp5 = (addr >> 16) & 0x1f;
+  u32 mask_bit = ~(0x10001 << comp3);
+  u32 part1;
+  u32 part2;
+  int byte;
+
+  part2 = ((seed1[comp5] >> make_shift (comp2, comp5, (comp3 >> 3) | (comp1 << 2) | 2)) & 1) ^ flip;
+  part1 = ((seed1[comp5] >> make_shift (comp2, comp5, (comp3 >> 3) | (comp1 << 2) | 0)) & 1) ^ flip;
+
+  for (byte = 0; byte < 4; byte++)
+    if ((get_seed2 (comp5, comp4) >> make_shift (comp2, comp5, (byte | (comp1 << 2)))) & 1 )
+      mask_byte |= 0xff << (8 * byte);
+
+  return (mask_bit & mask_byte) | (part1 << comp3) | (part2 << (comp3 + 16));
+}
+
+static void
+write_testing_type2 (struct raminfo *info, u8 totalrank, u8 region, u8 block, char flip)
+{
+  int i;
+  for (i = 0; i < 2048; i++)
+    write32 ((totalrank << 28) | (region << 25) | (block << 16) | (i << 2),
+	     get_etalon (flip, (block << 16) | (i << 2)));
+}
+
+static u8
+check_testing_type2 (struct raminfo *info, u8 totalrank, u8 region, u8 block, char flip)
+{
+  u8 failmask = 0;
+  u32 failxor[2];
+  int i;
+  int comp1, comp2, comp3;
+
+  failxor[0] = 0;
+  failxor[1] = 0;
+
+  enable_cache (totalrank << 28, 134217728);
+  for (comp3 = 0; comp3 < 2 && failmask != 0xff; comp3++)
+  {
+    for (comp1 = 0; comp1 < 16; comp1++)
+      for (comp2 = 0; comp2 < 64; comp2++)
+	{
+	  u32 addr = (totalrank << 28) | (region << 25) | (block << 16) | (comp3 << 12) | (comp2 << 6) | (comp1 << 2);
+	  failxor[comp1 & 1] |= read32 (addr) ^ get_etalon (flip, addr);
+	}
+    for (i = 0; i < 8; i++)
+      if ((0xff << (8 * (i % 4))) & failxor[i / 4])
+	failmask |= 1 << i;
+  }
+  disable_cache ();
+  flush_cache ((totalrank << 28) | (region << 25) | (block << 16), 16384);
+  return failmask;
+}
+
+static int 
+check_bounded (unsigned short *vals, u16 bound)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    if (vals[i] < bound)
+      return 0;
+  return 1;
+}
+
+enum state {
+  BEFORE_USABLE = 0, AT_USABLE = 1, AT_MARGIN = 2, COMPLETE = 3 
+};
+
+static int
+validate_state (enum state *in)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    if (in[i] != COMPLETE)
+      return 0;
+  return 1;
+}
+
+static void
+do_fsm (enum state *state, u16 *counter,
+	u8 fail_mask, int margin, int uplimit,
+	u8 *res_low, u8 *res_high, u8 val)
+{
+  int lane;
+
+  for (lane = 0; lane < 8; lane++)
+    {
+      int is_fail = (fail_mask >> lane) & 1;
+      switch (state[lane])
+	{
+	case BEFORE_USABLE:
+	  if (!is_fail)
+	    {
+	      counter[lane] = 1;
+	      state[lane] = AT_USABLE;
+	      break;
+	    }
+	  counter[lane] = 0;
+	  state[lane] = BEFORE_USABLE;
+	  break;
+	case AT_USABLE:
+	  if (!is_fail)
+	    {
+	      ++counter[lane];
+	      if (counter[lane] >= margin)
+		{
+		  state[lane] = AT_MARGIN;
+		  res_low[lane] = val - margin + 1;
+		  break;
+		}
+	      state[lane] = 1;
+	      break;
+	    }
+	  counter[lane] = 0;
+	  state[lane] = BEFORE_USABLE;
+	  break;
+	case AT_MARGIN:
+	  if (is_fail)
+	    {
+	      state[lane] = COMPLETE;
+	      res_high[lane] = val - 1;
+	    }
+	  else
+	    {
+	      counter[lane]++;
+	      state[lane] = AT_MARGIN;
+	      if (val == uplimit)
+		{
+		  state[lane] = COMPLETE;
+		  res_high[lane] = uplimit;
+		}
+	    }
+	  break;
+	case COMPLETE:
+	  break;
+	}
+    }
+}
+
+static void
+train_ram_at_178 (struct raminfo *info, u8 channel, int slot, int rank, u8 total_rank,
+		  u8 reg_178, int first_run, int niter, timing_bounds_t *timings)
+{
+  int lane;
+  enum state state[8];
+  u16 count[8];
+  u8 lower_usable[8];
+  u8 upper_usable[8];
+  unsigned short num_sucessfully_checked[8];
+  u8 secondary_total_rank;
+  u8 reg1b3;
+
+  if (info->populated_ranks_mask[1])
+  {
+    if (channel == 1)
+      secondary_total_rank = info->populated_ranks[1][0][0] + info->populated_ranks[1][0][1]
+	+ info->populated_ranks[1][1][0] + info->populated_ranks[1][1][1];
+    else
+      secondary_total_rank = 0;
+  }
+  else
+    secondary_total_rank = total_rank;
+
+  {
+    int i;
+    for (i = 0; i < 8; i++)
+      state[i] = BEFORE_USABLE;
+  }
+
+  if (!first_run)
+  {
+    int is_all_ok = 1;
+    for (lane = 0; lane < 8; lane++)
+      if (timings[reg_178][channel][slot][rank][lane].smallest == timings[reg_178][channel][slot][rank][lane].largest)
+      {
+	timings[reg_178][channel][slot][rank][lane].smallest = 0;
+	timings[reg_178][channel][slot][rank][lane].largest = 0;
+	is_all_ok = 0;
+      }
+    if (is_all_ok)
+      {
+	int i;
+	for (i = 0; i < 8; i++)
+	  state[i] = COMPLETE;
+      }
+  }
+
+  for (reg1b3 = 0; reg1b3 < 0x30 && !validate_state (state); reg1b3++)
+    {
+      u8 failmask = 0;
+      write_1d0 (reg1b3 ^ 32, 0x1b3, 6, 1);
+      write_1d0 (reg1b3 ^ 32, 0x1a3, 6, 1);
+      failmask = check_testing (info, total_rank, 0);
+      write_mchbar32 (0xfb0, read_mchbar32 (0xfb0) | 0x00030000);
+      do_fsm (state, count, failmask, 5, 47, lower_usable, upper_usable, reg1b3);
+    }
+
+  if (reg1b3)
+    {
+      write_1d0 (0, 0x1b3, 6, 1);
+      write_1d0 (0, 0x1a3, 6, 1);
+      for (lane = 0; lane < 8; lane++)
+	{
+	  if (state[lane] == COMPLETE)
+	    {
+	      timings[reg_178][channel][slot][rank][lane].smallest = lower_usable[lane] + (info->training.lane_timings[0][channel][slot][rank][lane] & 0x3F) - 32;
+	      timings[reg_178][channel][slot][rank][lane].largest = upper_usable[lane] + (info->training.lane_timings[0][channel][slot][rank][lane] & 0x3F) - 32;
+	    }
+	}
+    }
+
+  if (!first_run)
+  {
+    for (lane = 0; lane < 8; lane++)
+      if (state[lane] == COMPLETE)
+	{
+	  write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].smallest,
+		     get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+	  write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].smallest
+		     + info->training.lane_timings[1][channel][slot][rank][lane]
+		     - info->training.lane_timings[0][channel][slot][rank][lane], get_timing_register_addr (lane, 1, slot, rank), 9, 1);
+	  num_sucessfully_checked[lane] = 0;
+	}
+      else
+	num_sucessfully_checked[lane] = -1;
+
+    do
+    {
+      u8 failmask = 0;
+      int i;
+      for (i = 0; i < niter; i++)
+        {
+          if (failmask == 0xFF)
+            break;
+          failmask |= check_testing_type2 (info, total_rank, 2, i, 0);
+          failmask |= check_testing_type2 (info, total_rank, 3, i, 1);
+        }
+      write_mchbar32 (0xfb0, read_mchbar32 (0xfb0) | 0x00030000);
+      for (lane = 0; lane < 8; lane++)
+        if (num_sucessfully_checked[lane] != 0xffff)
+	  {
+	    if ((1 << lane) & failmask)
+	      {	    
+		if (timings[reg_178][channel][slot][rank][lane].largest <= timings[reg_178][channel][slot][rank][lane].smallest)
+		  num_sucessfully_checked[lane] = -1;
+		else
+		  {
+		    num_sucessfully_checked[lane] = 0;
+		    timings[reg_178][channel][slot][rank][lane].smallest++;
+		    write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].smallest,
+			       get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+		    write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].smallest
+			       + info->training.lane_timings[1][channel][slot][rank][lane]
+			       - info->training.lane_timings[0][channel][slot][rank][lane],
+			       get_timing_register_addr (lane, 1, slot, rank), 9, 1);
+		  }
+	      }
+	    else
+	      num_sucessfully_checked[lane]++;
+	  }
+    }
+    while (!check_bounded (num_sucessfully_checked, 2));
+
+    for (lane = 0; lane < 8; lane++)
+      if (state[lane] == COMPLETE)
+      {
+	write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].largest,
+		   get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+	write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].largest
+		   + info->training.lane_timings[1][channel][slot][rank][lane]
+		   - info->training.lane_timings[0][channel][slot][rank][lane], get_timing_register_addr (lane, 1, slot, rank), 9, 1);
+        num_sucessfully_checked[lane] = 0;
+      }
+      else
+        num_sucessfully_checked[lane] = -1;
+
+    do
+    {
+      int failmask = 0;
+      int i;
+      for (i = 0; i < niter; i++)
+        {
+          if (failmask == 0xFF)
+            break;
+          failmask |= check_testing_type2 (info, total_rank, 2, i, 0);
+          failmask |= check_testing_type2 (info, total_rank, 3, i, 1);
+        }
+
+      write_mchbar32 (0xfb0, read_mchbar32 (0xfb0) | 0x00030000);
+      for (lane = 0; lane < 8; lane++)
+      {
+        if (num_sucessfully_checked[lane] != 0xffff)
+        {
+          if ((1 << lane) & failmask)
+          {
+            if ( timings[reg_178][channel][slot][rank][lane].largest <= timings[reg_178][channel][slot][rank][lane].smallest )
+            {
+              num_sucessfully_checked[lane] = -1;
+            }
+            else
+            {
+              num_sucessfully_checked[lane] = 0;
+              timings[reg_178][channel][slot][rank][lane].largest--;
+	      write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].largest,
+			 get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+	      write_500 (info, channel, timings[reg_178][channel][slot][rank][lane].largest
+			 + info->training.lane_timings[1][channel][slot][rank][lane]
+			 - info->training.lane_timings[0][channel][slot][rank][lane], get_timing_register_addr (lane, 1, slot, rank), 9, 1);
+            }
+          }
+          else
+            num_sucessfully_checked[lane]++;
+        }
+      }
+    }
+    while (!check_bounded (num_sucessfully_checked, 3));
+
+    for (lane = 0; lane < 8; lane++)
+    {
+      write_500 (info, channel, info->training.lane_timings[0][channel][slot][rank][lane],
+		 get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+      write_500 (info, channel, info->training.lane_timings[1][channel][slot][rank][lane],
+		 get_timing_register_addr (lane, 1, slot, rank), 9, 1);
+      if (timings[reg_178][channel][slot][rank][lane].largest <= timings[reg_178][channel][slot][rank][lane].smallest)
+        {
+	  timings[reg_178][channel][slot][rank][lane].largest = 0;
+	  timings[reg_178][channel][slot][rank][lane].smallest = 0;
+        }
+    }
+  }
+}
+
+static void
+set_10b (struct raminfo *info, u8 val)
+{
+  int channel;
+  int slot, rank;
+  int lane;
+
+  if (read_1d0 (0x10b, 6) == val)
+    return;
+
+  write_1d0 (val, 0x10b, 6, 1);
+
+  FOR_POPULATED_RANKS_BACKWARDS
+    for (lane = 0; lane < 9; lane++)
+      {
+	u16 reg_500;
+	reg_500 = read_500 (info, channel,
+		       get_timing_register_addr (lane, 0, slot, rank), 9);
+	if (val == 1)
+	  {
+	    if ( lut16[info->clock_speed_index] <= reg_500 )
+	      reg_500 -= lut16[info->clock_speed_index];
+	    else
+	      reg_500 = 0;
+	  }
+	else
+	  {
+	    reg_500 += lut16[info->clock_speed_index];
+	  }
+	write_500 (info, channel, reg_500, 
+		   get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+      }
+}
+
+static void
+set_ecc(int onoff)
+{
+  int channel;
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+  {
+    u8 t;
+    t = read_mchbar8 ((channel << 10) + 0x5f8);
+    if (onoff)
+      t |= 1;
+    else
+      t &= ~1;
+    write_mchbar8 ((channel << 10) + 0x5f8, t);
+  }
+}
+
+
+static void
+set_178 (u8 val)
+{
+  if (val >= 31)
+    val = val - 31;
+  else
+    val = 63 - val;
+
+  write_1d0 (2 * val, 0x178, 7, 1);
+}
+
+static void 
+write_500_timings_type (struct raminfo *info, int channel, int slot, int rank, int type)
+{
+  int lane;
+
+  for (lane = 0; lane < 8; lane++)
+    write_500 (info, channel, info->training.lane_timings[type][channel][slot][rank][lane],
+	       get_timing_register_addr (lane, type, slot, rank),
+	       9, 0);
+}
+
+static void
+try_timing_offsets (struct raminfo *info, int channel,
+		    int slot, int rank, int totalrank)
+{
+  u16 count[8];
+  enum state state[8];
+  u8 lower_usable[8], upper_usable[8];
+  int lane;
+  int i;
+  int flip = 1;
+  int timing_offset;
+
+  for (i = 0; i < 8; i++)
+    state[i] = BEFORE_USABLE;
+
+  memset (count, 0, sizeof (count));
+  
+  for (lane = 0; lane < 8; lane++)
+    write_500 (info, channel, info->training.lane_timings[2][channel][slot][rank][lane] + 32, get_timing_register_addr (lane, 3, slot, rank), 9, 1);
+
+  for (timing_offset = 0; !validate_state (state) && timing_offset < 64; timing_offset++)
+  {
+    u8 failmask;
+    write_1d0 (timing_offset ^ 32, 0x1bb, 6, 1);
+    failmask = 0;
+    for (i = 0; i < 2 && failmask != 0xff; i++)
+      {
+	flip = !flip;
+	write_testing (info, totalrank, flip);
+	failmask |= check_testing (info, totalrank, flip);
+      }
+    do_fsm (state, count, failmask, 10, 63, lower_usable,
+	    upper_usable, timing_offset);
+  }
+  write_1d0 (0, 0x1bb, 6, 1);
+  dump_timings (info);
+  if (!validate_state (state))
+    die ("Couldn't discover DRAM timings (1)\n");
+
+  for (lane = 0; lane < 8; lane++)
+    {
+      u8 bias = 0;
+
+      if (info->silicon_revision)
+	{
+	  int usable_length;
+
+	  usable_length = upper_usable[lane] - lower_usable[lane];
+	  if (usable_length >= 20)
+	    {
+	      bias = usable_length / 2 - 10;
+	      if (bias >= 2)
+	       bias = 2;
+	    }
+	}
+      write_500 (info, channel, info->training.lane_timings[2][channel][slot][rank][lane] + (upper_usable[lane] + lower_usable[lane]) / 2 - bias,
+		 get_timing_register_addr (lane, 3, slot, rank), 9, 1);
+      info->training.timing2_bounds[channel][slot][rank][lane][0] = info->training.lane_timings[2][channel][slot][rank][lane] + lower_usable[lane];
+      info->training.timing2_bounds[channel][slot][rank][lane][1] = info->training.lane_timings[2][channel][slot][rank][lane] + upper_usable[lane];
+      info->training.timing2_offset[channel][slot][rank][lane] = info->training.lane_timings[2][channel][slot][rank][lane];
+    }
+}
+
+static u8
+choose_training (struct raminfo *info, int channel, int slot, int rank,
+		 int lane, timing_bounds_t *timings, u8 center_178)
+{
+  u16 central_weight;
+  u16 side_weight;
+  unsigned int sum = 0, count = 0;
+  u8 span;
+  u8 lower_margin, upper_margin;
+  u8 reg_178;
+  u8 result;
+
+  span = 12;
+  central_weight = 20;
+  side_weight = 20;
+  if (info->silicon_revision == 1 && channel == 1)
+  {
+    central_weight = 5;
+    side_weight = 20;
+    if ( (info->populated_ranks_mask[1] ^ (info->populated_ranks_mask[1] >> 2)) & 1 )
+        span = 18;
+  }
+  if ((info->populated_ranks_mask[0] & 5) == 5)
+  {
+    central_weight = 20;
+    side_weight = 20;
+  }
+  if ( info->clock_speed_index >= 2 && (info->populated_ranks_mask[0] & 5) == 5 && slot == 1)
+  {
+    if (info->silicon_revision == 1)
+    {
+      switch (channel)
+	{
+	case 0:
+	  if (lane == 1)
+	    {
+	      central_weight = 10;
+	      side_weight = 20;
+	    }
+	  break;
+	case 1:
+	  if (lane == 6)
+	    {
+	      side_weight = 5;
+	      central_weight = 20;
+	    }
+	  break;
+	}
+    }
+    if (info->silicon_revision == 0 && channel == 0 && lane == 0)
+      {
+	side_weight = 5;
+	central_weight = 20;
+      }
+  }
+  for (reg_178 = center_178 - span; reg_178 <= center_178 + span; reg_178 += span)
+  {
+    u8 smallest;
+    u8 largest;
+    largest = timings[reg_178][channel][slot][rank][lane].largest;
+    smallest = timings[reg_178][channel][slot][rank][lane].smallest;
+    if (largest - smallest + 1 >= 5)
+    {
+      unsigned int weight;
+      if (reg_178 == center_178)
+        weight = central_weight;
+      else
+	weight = side_weight;
+      sum += weight * (largest + smallest);
+      count += weight;
+    }
+  }
+  dump_timings (info);
+  if (count == 0)
+    die ("Couldn't discover DRAM timings (2)\n");
+  result = sum / (2 * count);
+  lower_margin = result - timings[center_178][channel][slot][rank][lane].smallest;
+  upper_margin = timings[center_178][channel][slot][rank][lane].largest - result;
+  if (upper_margin < 10 && lower_margin > 10)
+    result -= min (lower_margin - 10, 10 - upper_margin);
+  if (upper_margin > 10 && lower_margin < 10)
+    result += min (upper_margin - 10, 10 - lower_margin);
+  return result;
+}
+
+#define STANDARD_MIN_MARGIN 5
+
+static u8
+choose_reg178 (struct raminfo *info, timing_bounds_t *timings)
+{
+  u16 margin[64];
+  int lane, rank, slot, channel;
+  u8 reg178;
+  int count = 0, sum = 0;
+
+  for (reg178 = reg178_min[info->clock_speed_index];
+       reg178 < reg178_max[info->clock_speed_index];
+       reg178 += reg178_step[info->clock_speed_index])
+    {
+      margin[reg178] = -1;
+      FOR_POPULATED_RANKS_BACKWARDS
+	for (lane = 0; lane < 8; lane++)
+	  {
+	    int curmargin = timings[reg178][channel][slot][rank][lane].largest - timings[reg178][channel][slot][rank][lane].smallest + 1;
+	    if (curmargin < margin[reg178])
+	      margin[reg178] = curmargin;
+	  }
+      if (margin[reg178] >= STANDARD_MIN_MARGIN)
+	{
+	  u16 weight;
+	  weight = margin[reg178] - STANDARD_MIN_MARGIN;
+	  sum += weight * reg178;
+	  count += weight;
+	}
+    }
+  dump_timings (info);
+  if (count == 0)
+    die ("Couldn't discover DRAM timings (3)\n");
+
+  u8 threshold;
+
+  for (threshold = 30; threshold >= 5; threshold--)
+    {
+      int usable_length = 0;
+      int smallest_fount = 0;
+      for (reg178 = reg178_min[info->clock_speed_index];
+	   reg178 < reg178_max[info->clock_speed_index];
+	   reg178 += reg178_step[info->clock_speed_index])
+	if (margin[reg178] >= threshold)
+	  {
+	    usable_length += reg178_step[info->clock_speed_index];
+	    info->training.reg178_largest = reg178 - 2 * reg178_step[info->clock_speed_index];
+
+	    if (!smallest_fount)
+	      {
+		smallest_fount = 1;
+		info->training.reg178_smallest = reg178 + reg178_step[info->clock_speed_index];
+	      }
+	  }
+      if (usable_length >= 0x21)
+	break;
+    }
+
+  return sum / count;
+}
+
+static int
+check_cached_sanity (struct raminfo *info)
+{
+  int lane;
+  int slot, rank;
+  int channel;
+
+  if (!info->cached_training)
+    return 0;
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    for (slot = 0; slot < NUM_SLOTS; slot++)
+      for (rank = 0; rank < NUM_RANKS; rank++)
+      for (lane = 0; lane < 8 + info->use_ecc; lane++)
+        {
+	  u16 cached_value, estimation_value;
+          cached_value = info->cached_training->lane_timings[1][channel][slot][rank][lane];
+          if (cached_value >= 0x18 && cached_value <= 0x1E7)
+	    {
+	      estimation_value = info->training.lane_timings[1][channel][slot][rank][lane];
+	      if (estimation_value < cached_value - 24)
+		return 0;
+	      if (estimation_value > cached_value + 24)
+		return 0;
+	    }
+        }
+  return 1;
+}
+
+
+static int
+try_cached_training (struct raminfo *info)
+{
+  u8 saved_243[2];
+  u8 tm;
+
+  int channel, slot, rank, lane;
+  int flip = 1;
+  int i, j;
+
+  if (!check_cached_sanity (info))
+    return 0;
+
+  info->training.reg178_center = info->cached_training->reg178_center;
+  info->training.reg178_smallest = info->cached_training->reg178_smallest;
+  info->training.reg178_largest = info->cached_training->reg178_largest;
+  memcpy (&info->training.timing_bounds,
+	  &info->cached_training->timing_bounds, sizeof (info->training.timing_bounds));
+  memcpy (&info->training.timing_offset,
+	  &info->cached_training->timing_offset, sizeof (info->training.timing_offset));
+
+  write_1d0 (2, 0x142, 3, 1);
+  saved_243[0] = read_mchbar8 (0x243);
+  saved_243[1] = read_mchbar8 (0x643);
+  write_mchbar8 (0x243, saved_243[0] | 2);
+  write_mchbar8 (0x643, saved_243[1] | 2);
+  set_ecc(0);
+  pci_mm_write16 (0, 0, 0, 0xc8, 3);
+  if ( read_1d0 (0x10b, 6) & 1 )
+    set_10b(info, 0);
+  for (tm = 0; tm < 2; tm++)
+    {
+      int totalrank;
+
+      set_178 (tm ? info->cached_training->reg178_largest : info->cached_training->reg178_smallest);
+      
+      totalrank = 0;
+      /* Check timing ranges. With i == 0 we check smallest one and with
+	 i == 1 the largest bound. With j == 0 we check that on the bound
+	 it still works whereas with j == 1 we check that just outside of
+	 bound we fail.
+       */
+      FOR_POPULATED_RANKS_BACKWARDS
+	{
+	  for (i = 0; i < 2; i++)
+	    {
+	      for (lane = 0; lane < 8; lane++)
+		{
+		  write_500 (info, channel, info->cached_training->timing2_bounds[channel][slot][rank][lane][i],
+			     get_timing_register_addr (lane, 3, slot, rank), 9, 1);
+
+		  if ( !i )
+		    write_500 (info, channel, info->cached_training->timing2_offset[channel][slot][rank][lane],
+			       get_timing_register_addr (lane, 2, slot, rank), 9, 1);
+		  write_500 (info, channel, i ? info->cached_training->timing_bounds[tm][channel][slot][rank][lane].largest
+			     : info->cached_training->timing_bounds[tm][channel][slot][rank][lane].smallest,
+			     get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+		  write_500 (info, channel,
+			     info->cached_training->timing_offset[channel][slot][rank][lane] +
+			     (i ? info->cached_training->timing_bounds[tm][channel][slot][rank][lane].largest
+			      : info->cached_training->timing_bounds[tm][channel][slot][rank][lane].smallest)  - 64,
+			     get_timing_register_addr (lane, 1, slot, rank),
+			     9, 1);
+		}
+	      for (j = 0; j < 2; j++)
+		{
+		  u8 failmask;
+		  u8 expected_failmask;
+		  char reg1b3;
+
+		  reg1b3 = (j == 1) + 4;
+		  reg1b3 = j == i ? reg1b3 : (-reg1b3) & 0x3f;
+		  write_1d0 (reg1b3, 0x1bb, 6, 1);
+		  write_1d0 (reg1b3, 0x1b3, 6, 1);
+		  write_1d0 (reg1b3, 0x1a3, 6, 1);
+
+		  flip = !flip;
+		  write_testing (info, totalrank, flip);
+		  failmask = check_testing (info, totalrank, flip);
+		  expected_failmask = j == 0 ? 0x00 : 0xff;
+		  if (failmask != expected_failmask)
+		    goto fail;
+		}
+	    }
+	  totalrank++;
+	}
+    }
+
+  set_178 (info->cached_training->reg178_center);
+  if (info->use_ecc)
+    set_ecc(1);
+  write_training_data (info);
+  write_1d0 (0, 322, 3, 1);
+  info->training = *info->cached_training;
+
+  write_1d0 (0, 0x1bb, 6, 1);
+  write_1d0 (0, 0x1b3, 6, 1);
+  write_1d0 (0, 0x1a3, 6, 1);
+  write_mchbar8 (0x243, saved_243[0]);
+  write_mchbar8 (0x643, saved_243[1]);
+
+  return 1;
+
+fail:
+  FOR_POPULATED_RANKS
+    {
+      write_500_timings_type (info, channel, slot, rank, 1);
+      write_500_timings_type (info, channel, slot, rank, 2);
+      write_500_timings_type (info, channel, slot, rank, 3);
+    }
+  
+  write_1d0 (0, 0x1bb, 6, 1);
+  write_1d0 (0, 0x1b3, 6, 1);
+  write_1d0 (0, 0x1a3, 6, 1);
+  write_mchbar8 (0x243, saved_243[0]);
+  write_mchbar8 (0x643, saved_243[1]);
+
+  return 0;
+}
+
+static void 
+do_ram_training (struct raminfo *info)
+{
+  u8 saved_243[2];
+  int totalrank = 0;
+  u8 reg_178;
+  int niter;
+
+  timing_bounds_t timings[64];
+  int lane, rank, slot, channel;
+  u8 reg178_center;
+
+  write_1d0 (2, 0x142, 3, 1);
+  saved_243[0] = read_mchbar8 (0x243);
+  saved_243[1] = read_mchbar8 (0x643);
+  write_mchbar8 (0x243, saved_243[0] | 2);
+  write_mchbar8 (0x643, saved_243[1] | 2);
+  switch (info->clock_speed_index)
+    {
+    case 0:
+      niter = 5;
+      break;
+    case 1:
+      niter = 10;
+      break;
+    default:
+      niter = 19;
+      break;
+    }
+  set_ecc (0);
+
+  FOR_POPULATED_RANKS_BACKWARDS
+    {
+      int i;
+
+      write_500_timings_type (info, channel, slot, rank, 0);
+
+      write_testing (info, totalrank, 0);
+      for (i = 0; i < niter; i++)
+	{
+	  write_testing_type2 (info, totalrank, 2, i, 0);
+	  write_testing_type2 (info, totalrank, 3, i, 1);
+	}
+      pci_mm_write8 (0, 0, 0, 0xc0, 0x01);
+      totalrank++;
+    }
+
+  if (reg178_min[info->clock_speed_index] < reg178_max[info->clock_speed_index])
+    memset (timings[reg178_min[info->clock_speed_index]], 0,
+	    sizeof (timings[0]) * (reg178_max[info->clock_speed_index] - reg178_min[info->clock_speed_index]));
+  for (reg_178 = reg178_min[info->clock_speed_index];
+       reg_178 < reg178_max[info->clock_speed_index];
+       reg_178 += reg178_step[info->clock_speed_index])
+    {
+      totalrank = 0;
+      set_178 (reg_178);
+      for (channel = NUM_CHANNELS - 1; channel >= 0; channel--)
+	for (slot = 0; slot < NUM_SLOTS; slot++)
+	  for (rank = 0; rank < NUM_RANKS; rank++)
+	    {
+	      memset (&timings[reg_178][channel][slot][rank][0].smallest, 0, 16);
+	      if (info->populated_ranks[channel][slot][rank])
+		{
+		  train_ram_at_178 (info, channel, slot, rank, totalrank,
+				    reg_178, 1, niter, timings);
+		  totalrank++;
+		}
+	    }
+    }
+
+  reg178_center = choose_reg178 (info, timings);
+
+  FOR_POPULATED_RANKS_BACKWARDS
+    for (lane = 0; lane < 8; lane++)
+      {
+	info->training.timing_bounds[0][channel][slot][rank][lane].smallest = timings[info->training.reg178_smallest][channel][slot][rank][lane].smallest;
+	info->training.timing_bounds[0][channel][slot][rank][lane].largest = timings[info->training.reg178_smallest][channel][slot][rank][lane].largest;
+	info->training.timing_bounds[1][channel][slot][rank][lane].smallest = timings[info->training.reg178_largest][channel][slot][rank][lane].smallest;
+	info->training.timing_bounds[1][channel][slot][rank][lane].largest = timings[info->training.reg178_largest][channel][slot][rank][lane].largest;
+	info->training.timing_offset[channel][slot][rank][lane] = info->training.lane_timings[1][channel][slot][rank][lane]
+	  - info->training.lane_timings[0][channel][slot][rank][lane] + 64;
+      }
+
+  if ( info->silicon_revision == 1 && (info->populated_ranks_mask[1] ^ (info->populated_ranks_mask[1] >> 2)) & 1 )
+    {
+      int ranks_after_channel1;
+
+      totalrank = 0;
+      for (reg_178 = reg178_center - 18; reg_178 <= reg178_center + 18; reg_178 += 18)
+	{
+	  totalrank = 0;
+	  set_178 (reg_178);
+	  for (slot = 0; slot < NUM_SLOTS; slot++)
+	    for (rank = 0; rank < NUM_RANKS; rank++)
+	      {
+		if (info->populated_ranks[1][slot][rank])
+		  {
+		    train_ram_at_178 (info, 1, slot, rank, totalrank, reg_178, 0, niter, timings);
+		    totalrank++;
+		  }
+	      }
+	}
+      ranks_after_channel1 = totalrank;
+      
+      for (reg_178 = reg178_center - 12; reg_178 <= reg178_center + 12; reg_178 += 12)
+	{
+	  totalrank = ranks_after_channel1;
+	  set_178 (reg_178);
+	  for (slot = 0; slot < NUM_SLOTS; slot++)
+	    for (rank = 0; rank < NUM_RANKS; rank++)
+	      if (info->populated_ranks[0][slot][rank])
+		{
+		  train_ram_at_178 (info, 0, slot, rank, totalrank,
+				    reg_178, 0, niter, timings);
+		  totalrank++;
+		}
+        
+	}
+    }
+  else
+    {
+      for (reg_178 = reg178_center - 12; reg_178 <= reg178_center + 12; reg_178 += 12)
+	{
+	  totalrank = 0;
+	  set_178 (reg_178);
+	  FOR_POPULATED_RANKS_BACKWARDS
+	    {
+	      train_ram_at_178 (info, channel, slot, rank, totalrank,
+				reg_178, 0, niter, timings);
+	      totalrank++;
+	    }
+	}
+    }
+
+  set_178 (reg178_center);
+  FOR_POPULATED_RANKS_BACKWARDS
+    for (lane = 0; lane < 8; lane++)
+      {
+	u16 tm0;
+
+	tm0 = choose_training (info, channel, slot, rank, lane, timings, reg178_center);
+	write_500 (info, channel, tm0, 
+		   get_timing_register_addr (lane, 0, slot, rank), 9, 1);
+	write_500 (info, channel, tm0 + info->training.lane_timings[1][channel][slot][rank][lane] - info->training.lane_timings[0][channel][slot][rank][lane],
+		   get_timing_register_addr (lane, 1, slot, rank), 9, 1);
+      }
+
+  totalrank = 0;
+  FOR_POPULATED_RANKS_BACKWARDS
+    {
+      try_timing_offsets (info, channel, slot, rank, totalrank);
+      totalrank++;
+    }
+  write_mchbar8 (0x243, saved_243[0]);
+  write_mchbar8 (0x643, saved_243[1]);
+  write_1d0 (0, 0x142, 3, 1);
+  info->training.reg178_center = reg178_center;
+}
+
+static void 
+ram_training (struct raminfo *info)
+{
+  u16 saved_fc4;
+
+  saved_fc4 = read_mchbar16 (0xfc4);
+  write_mchbar16 (0xfc4, 0xffff);
+
+  if (info->revision >= 8)
+    read_4090 (info);
+
+  if (!try_cached_training (info))
+    do_ram_training (info);
+  if ((info->silicon_revision == 2 || info->silicon_revision == 3) && info->clock_speed_index < 2)
+    set_10b (info, 1);
+  write_mchbar16 (0xfc4, saved_fc4);
+}
+
+static unsigned
+gcd (unsigned a, unsigned b)
+{
+  unsigned t;
+  if (a > b)
+    {
+      t = a;
+      a = b;
+      b = t;
+    }
+  /* invariant a < b.  */
+  while (a)
+    {
+      t = b % a;
+      b = a;
+      a = t;
+    }
+  return b;
+}
+
+static inline int
+div_roundup (int a, int b)
+{
+  return (a + b - 1) / b;
+}
+
+static unsigned
+lcm (unsigned a, unsigned b)
+{
+  return (a * b) / gcd (a, b);
+}
+
+struct stru1
+{
+  u8 freqs_reversed;
+  u8 freq_diff_reduced;
+  u8 freq_min_reduced;
+  u8 divisor_f4_to_fmax;
+  u8 divisor_f3_to_fmax;
+  u8 freq4_to_max_remainder;
+  u8 freq3_to_2_remainder;
+  u8 freq3_to_2_remaindera;
+  u8 freq4_to_2_remainder;
+  int divisor_f3_to_f1, divisor_f4_to_f2;
+  int common_time_unit_ps;
+  int freq_max_reduced;
+};
+
+static void
+compute_frequence_ratios (struct raminfo *info, u16 freq1, u16 freq2, int num_cycles_2, int num_cycles_1,
+	      int round_it, int add_freqs, struct stru1 *result)
+{
+  int g;
+  int common_time_unit_ps;
+  int freq1_reduced, freq2_reduced;
+  int freq_min_reduced;
+  int freq_max_reduced;
+  int freq3, freq4;
+
+  g = gcd (freq1, freq2);
+  freq1_reduced = freq1 / g;
+  freq2_reduced = freq2 / g;
+  freq_min_reduced = min (freq1_reduced, freq2_reduced);
+  freq_max_reduced = max (freq1_reduced, freq2_reduced);
+
+  common_time_unit_ps = div_roundup (900000, lcm (freq1, freq2));
+  freq3 = div_roundup (num_cycles_2, common_time_unit_ps) - 1;
+  freq4 = div_roundup (num_cycles_1, common_time_unit_ps) - 1;
+  if (add_freqs)
+  {
+    freq3 += freq2_reduced;
+    freq4 += freq1_reduced;
+  }
+
+  if (round_it)
+  {
+    result->freq3_to_2_remainder = 0;
+    result->freq3_to_2_remaindera = 0;
+    result->freq4_to_max_remainder = 0;
+    result->divisor_f4_to_f2 = 0;
+    result->divisor_f3_to_f1 = 0;
+  }
+  else
+  {
+    if (freq2_reduced < freq1_reduced)
+    {
+      result->freq3_to_2_remainder = result->freq3_to_2_remaindera = freq3 % freq1_reduced - freq1_reduced + 1;
+      result->freq4_to_max_remainder = -(freq4 % freq1_reduced);
+      result->divisor_f3_to_f1 = freq3 / freq1_reduced;
+      result->divisor_f4_to_f2 = (freq4 - (freq1_reduced - freq2_reduced)) / freq2_reduced;
+      result->freq4_to_2_remainder = -(char)((freq1_reduced - freq2_reduced) + ((u8)freq4 - (freq1_reduced - freq2_reduced)) % (u8)freq2_reduced);
+    }
+    else
+    {
+      if (freq2_reduced > freq1_reduced)
+	{
+	  result->freq4_to_max_remainder = (freq4 % freq2_reduced) - freq2_reduced + 1;
+	  result->freq4_to_2_remainder = freq4 % freq_max_reduced - freq_max_reduced + 1;
+	}
+      else
+	{
+	  result->freq4_to_max_remainder = -(freq4 % freq2_reduced);
+	  result->freq4_to_2_remainder = -(char)(freq4 % freq_max_reduced);
+	}
+      result->divisor_f4_to_f2 = freq4 / freq2_reduced;
+      result->divisor_f3_to_f1 = (freq3 - (freq2_reduced - freq1_reduced)) / freq1_reduced;
+      result->freq3_to_2_remainder = -(freq3 % freq2_reduced);
+      result->freq3_to_2_remaindera = -(char)((freq_max_reduced - freq_min_reduced) + (freq3 - (freq_max_reduced - freq_min_reduced)) % freq1_reduced);
+    }
+  }
+  result->divisor_f3_to_fmax = freq3 / freq_max_reduced;
+  result->divisor_f4_to_fmax = freq4 / freq_max_reduced;
+  if (round_it)
+  {
+    if (freq2_reduced > freq1_reduced)
+    {
+      if (freq3 % freq_max_reduced)
+        result->divisor_f3_to_fmax++;
+    }
+    if (freq2_reduced < freq1_reduced)
+    {
+      if (freq4 % freq_max_reduced)
+        result->divisor_f4_to_fmax++;
+    }
+  }
+  result->freqs_reversed = (freq2_reduced < freq1_reduced);
+  result->freq_diff_reduced = freq_max_reduced - freq_min_reduced;
+  result->freq_min_reduced = freq_min_reduced;
+  result->common_time_unit_ps = common_time_unit_ps;
+  result->freq_max_reduced = freq_max_reduced;
+}
+
+static void
+set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, int num_cycles_2, int num_cycles_1, int num_cycles_3, int num_cycles_4, int reverse)
+{
+  struct stru1 vv;
+  char multiplier;
+
+  compute_frequence_ratios (info, freq1, freq2, num_cycles_2, num_cycles_1, 0, 1, &vv);
+
+  multiplier = div_roundup (max (div_roundup (num_cycles_2, vv.common_time_unit_ps) + div_roundup (num_cycles_3, vv.common_time_unit_ps),
+			  div_roundup (num_cycles_1, vv.common_time_unit_ps) + div_roundup (num_cycles_4, vv.common_time_unit_ps))
+		     + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1;
+
+  u32 y = (u8)((vv.freq_max_reduced - vv.freq_min_reduced) + vv.freq_max_reduced * multiplier)
+     | (vv.freqs_reversed << 8) | ((u8)(vv.freq_min_reduced * multiplier) << 16) | ((u8)(vv.freq_min_reduced * multiplier) << 24);
+  u32 x = vv.freq3_to_2_remaindera | (vv.freq4_to_2_remainder << 8) | (vv.divisor_f3_to_f1 << 16) | (vv.divisor_f4_to_f2 << 20) | (vv.freq_min_reduced << 24);
+  if (reverse)
+  {
+    write_mchbar32 (reg, y);
+    write_mchbar32 (reg + 4, x);
+  }
+  else
+  {
+    write_mchbar32 (reg + 4, y);
+    write_mchbar32 (reg, x);
+  }
+}
+
+static void
+set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, int num_cycles_1, int num_cycles_2, int num_cycles_3, int num_cycles_4)
+{
+  struct stru1 ratios1;
+  struct stru1 ratios2;
+
+  compute_frequence_ratios(info, freq1, freq2, num_cycles_1, num_cycles_2, 0, 1, &ratios2);
+  compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1);
+  write_mchbar32 (reg, ratios1.freq4_to_max_remainder | (ratios2.freq4_to_max_remainder << 8) 
+		  | (ratios1.divisor_f4_to_fmax << 16) | (ratios2.divisor_f4_to_fmax << 20));
+}
+
+static void
+set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2, int num_cycles_2, int num_cycles_1, int round_it, int add_freqs)
+{
+  struct stru1 ratios;
+
+  compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1, round_it, add_freqs, &ratios);
+  switch (mode)
+    {
+    case 0:
+      write_mchbar32 (reg + 4, ratios.freq_diff_reduced | (ratios.freqs_reversed << 8));
+      write_mchbar32 (reg, ratios.freq3_to_2_remainder | (ratios.freq4_to_max_remainder << 8)
+		      | (ratios.divisor_f3_to_fmax << 16) | (ratios.divisor_f4_to_fmax << 20) | (ratios.freq_min_reduced << 24));
+      break;
+
+    case 1:
+      write_mchbar32 (reg, ratios.freq3_to_2_remainder | (ratios.divisor_f3_to_fmax << 16));
+      break;
+
+    case 2:
+      write_mchbar32 (reg, ratios.freq3_to_2_remainder | (ratios.freq4_to_max_remainder << 8) | (ratios.divisor_f3_to_fmax << 16) | (ratios.divisor_f4_to_fmax << 20));
+      break;
+
+    case 4:
+      write_mchbar32 (reg, (ratios.divisor_f3_to_fmax << 4)
+		      | (ratios.divisor_f4_to_fmax << 8) | (ratios.freqs_reversed << 12) | (ratios.freq_min_reduced << 16) | (ratios.freq_diff_reduced << 24));
+      break;
+    }
+}
+
+static void
+set_2dxx_series (struct raminfo *info)
+{
+  set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11 (info) / 2, 1359, 1005, 0, 1);
+  set_2dx8_reg(info, 0x2d08, 0, 0x78, 0x78, 3273, 5033, 1, 1);
+  set_2dx8_reg(info, 0x2d10, 0, 0x78, info->fsb_frequency, 1475, 1131, 0, 1);
+  set_2dx8_reg(info, 0x2d18, 0, 2 * info->fsb_frequency, frequency_11 (info), 1231, 1524, 0, 1);
+  set_2dx8_reg(info, 0x2d20, 0, 2 * info->fsb_frequency, frequency_11 (info) / 2, 1278, 2008, 0, 1);
+  set_2dx8_reg(info, 0x2d28, 0, info->fsb_frequency, frequency_11 (info), 1167, 1539, 0, 1);
+  set_2dx8_reg(info, 0x2d30, 0, info->fsb_frequency, frequency_11 (info) / 2, 1403, 1318, 0, 1);
+  set_2dx8_reg(info, 0x2d38, 0, info->fsb_frequency, 0x78, 3460, 5363, 1, 1);
+  set_2dx8_reg(info, 0x2d40, 0, info->fsb_frequency, 0x3c, 2792, 5178, 1, 1);
+  set_2dx8_reg(info, 0x2d48, 0, 2 * info->fsb_frequency, 0x78, 2738, 4610, 1, 1);
+  set_2dx8_reg(info, 0x2d50, 0, info->fsb_frequency, 0x78, 2819, 5932, 1, 1);
+  set_2dx8_reg(info, 0x6d4, 1, info->fsb_frequency, frequency_11 (info) / 2, 4000, 0, 0, 0);
+  set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency, frequency_11 (info) / 2, 4000, 4000, 0, 0);
+
+  set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11 (info), 0, info->delay46_ps[0], 0, info->delay54_ps[0]);
+  set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency, frequency_11 (info), 2500, 0, 0, 0);
+  set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11 (info) / 2, 3500, 0, 0, 0);
+  set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11 (info), 0, info->delay46_ps[1], 0, info->delay54_ps[1]);
+  set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0);
+  set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455, 470, 0);
+  set_2d5x_reg(info, 0x2d68, 0x195, 0x3c, 2707, 5632, 3277, 2207, 0);
+  set_2d5x_reg(info, 0x2d70, 0x195, frequency_11 (info) / 2, 1276, 758, 454, 459, 0);
+  set_2d5x_reg(info, 0x2d78, 0x195, 0x78, 1021, 799, 510, 513, 0);
+  set_2d5x_reg(info, 0x2d80, info->fsb_frequency, 0xe1, 0, 2862, 2579, 2588, 0);
+  set_2d5x_reg(info, 0x2d88, info->fsb_frequency, 0xe1, 0, 2690, 2405, 2405, 0);
+  set_2d5x_reg(info, 0x2da0, 0x78, 0xe1, 0, 2560, 2264, 2251, 0);
+  set_2d5x_reg(info, 0x2da8, 0x195, frequency_11 (info), 1060, 775, 484, 480, 0);
+  set_2d5x_reg(info, 0x2db0, 0x195, 0x78, 4183, 6023, 2217, 2048, 0);
+  write_mchbar32 (0x2dbc, ((frequency_11 (info) / 2) - 1) | 0xe00000);
+  write_mchbar32 (0x2db8, ((info->fsb_frequency - 1) << 16) | 0x77);
+}
+
+static u16 
+get_max_timing (struct raminfo *info, int channel)
+{
+  int slot, rank, lane;
+  u16 ret = 0;
+
+  if ((read_mchbar8 (0x2ca8) >> 2) < 1)
+    return 384;
+    
+  if (info->revision < 8)
+    return 256;
+
+  for (slot = 0; slot < NUM_SLOTS; slot++)
+    for (rank = 0; rank < NUM_RANKS; rank++)
+      if (info->populated_ranks[channel][slot][rank])
+	for (lane = 0; lane < 8 + info->use_ecc; lane++)
+	  ret = max (ret, read_500 (info, channel, 
+				    get_timing_register_addr (lane, 0, slot, rank), 9));
+  return ret;
+}
+
+static void
+set_274265 (struct raminfo *info)
+{
+  int delay_a_ps, delay_b_ps, delay_c_ps, delay_d_ps;
+  int delay_e_ps, delay_e_cycles, delay_f_cycles;
+  int delay_e_over_cycle_ps;
+  int cycletime_ps;
+  int channel;
+
+  delay_a_ps = 4 * halfcycle_ps (info) + 6 * fsbcycle_ps (info);
+  info->reg2ca9_bit0 = 0;
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      cycletime_ps = 900000 / lcm (2 * info->fsb_frequency, frequency_11 (info));
+      delay_d_ps = (halfcycle_ps (info) * get_max_timing (info, channel) >> 6)
+	- info->some_delay_3_ps_rounded
+	+ 200;
+      if (!((info->silicon_revision == 0 || info->silicon_revision == 1)
+	    && (info->revision >= 8)))
+	delay_d_ps += halfcycle_ps (info) * 2;
+      delay_d_ps += halfcycle_ps (info) * (!info->revision_flag_1 + info->some_delay_2_halfcycles_ceil + 2 * info->some_delay_1_cycle_floor
+				    + info->clock_speed_index + 2 * info->cas_latency - 7 + 11);
+      delay_d_ps += info->revision >= 8 ? 2758 : 4428;
+
+      write_mchbar32 (0x140, (read_mchbar32 (0x140) & 0xfaffffff) | 0x2000000);
+      write_mchbar32 (0x138, (read_mchbar32 (0x138) & 0xfaffffff) | 0x2000000);
+      if ( (read_mchbar8 (0x144) & 0x1f) > 0x13 )
+	delay_d_ps += 650;
+      delay_c_ps = delay_d_ps + 1800;
+      if (delay_c_ps <= delay_a_ps)
+	delay_e_ps = 0;
+      else
+	delay_e_ps = cycletime_ps * div_roundup (delay_c_ps - delay_a_ps, cycletime_ps);
+ 
+      delay_e_over_cycle_ps = delay_e_ps % (2 * halfcycle_ps (info));
+      delay_e_cycles = delay_e_ps / (2 * halfcycle_ps (info));
+      delay_f_cycles = div_roundup (2500 - delay_e_over_cycle_ps, 2 * halfcycle_ps (info));
+      if (delay_f_cycles > delay_e_cycles)
+	{
+	  info->delay46_ps[channel] = delay_e_ps;
+	  delay_e_cycles = 0;
+	}
+      else
+	{
+	  info->delay46_ps[channel] = delay_e_over_cycle_ps + 2 * halfcycle_ps (info) * delay_f_cycles;
+	  delay_e_cycles -= delay_f_cycles;
+	}
+
+      if (info->delay46_ps[channel] < 2500)
+	{
+	  info->delay46_ps[channel] = 2500;
+	  info->reg2ca9_bit0 = 1;
+	}
+      delay_b_ps = halfcycle_ps (info) + delay_c_ps;
+      if (delay_b_ps <= delay_a_ps)
+	delay_b_ps = 0;
+      else
+	delay_b_ps -= delay_a_ps;
+      info->delay54_ps[channel] = cycletime_ps * div_roundup (delay_b_ps, cycletime_ps) - 2 * halfcycle_ps (info) * delay_e_cycles;
+      if (info->delay54_ps[channel] < 2500)
+	info->delay54_ps[channel] = 2500;
+      info->reg274265[channel][0] = delay_e_cycles;
+      if (delay_d_ps + 7 * halfcycle_ps (info) <= 24 * halfcycle_ps (info))
+	info->reg274265[channel][1] = 0;
+      else
+	info->reg274265[channel][1] = div_roundup (delay_d_ps + 7 * halfcycle_ps (info), 4 * halfcycle_ps (info)) - 6;
+      write_mchbar32 ((channel << 10) + 0x274, info->reg274265[channel][1] | (info->reg274265[channel][0] << 16));
+      info->reg274265[channel][2] = div_roundup (delay_c_ps + 3 * fsbcycle_ps (info), 4 * halfcycle_ps (info)) + 1;
+      write_mchbar16 ((channel << 10) + 0x265, info->reg274265[channel][2] << 8);
+    }
+  if (info->reg2ca9_bit0)
+    write_mchbar8 (0x2ca9, read_mchbar8 (0x2ca9) | 1);
+  else
+    write_mchbar8 (0x2ca9, read_mchbar8 (0x2ca9) & ~1);
+}
+
+static void
+restore_274265 (struct raminfo *info)
+{
+  int channel;
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_mchbar32 ((channel << 10) + 0x274, (info->reg274265[channel][0] << 16) | info->reg274265[channel][1]);
+      write_mchbar16 ((channel << 10) + 0x265, info->reg274265[channel][2] << 8);
+    }
+  if (info->reg2ca9_bit0)
+    write_mchbar8 (0x2ca9, read_mchbar8 (0x2ca9) | 1);
+  else
+    write_mchbar8 (0x2ca9, read_mchbar8 (0x2ca9) & ~1);
+}
+
+static void
+pre_raminit (void)
+{
+  u16 si;
+
+#if ! REAL
+  outb (0x0, 0x62);
+
+  unsigned number_cores;
+  struct cpuid_result result;
+  unsigned threads_per_package, threads_per_core;
+
+  /* Logical processors (threads) per core */
+  result = cpuid_ext(0xb, 0);
+  threads_per_core = result.ebx & 0xffff;
+
+  /* Logical processors (threads) per package */
+  result = cpuid_ext(0xb, 1);
+  threads_per_package = result.ebx & 0xffff;
+
+  if (threads_per_package == 0 || threads_per_core == 0 || threads_per_package % threads_per_core)
+    number_cores = 1;
+  else
+    number_cores = threads_per_package / threads_per_core;
+
+  u8 al = nvram_read (0x4c);
+  if (number_cores <= 1)
+    si = 0;
+  else if (!(al & 1))
+    si = 1;
+  else if (number_cores <= 2)
+    si = 0;
+  else if (!(al & 2))
+    si = 2;
+  else
+    si = 0;
+  if (!(nvram_read (0x55) & 2))
+    si |= 0x100;
+#else
+  /* bit 0 = disable multicore,
+     bit 1 = disable quadcore,
+     bit 8 = disable hyperthreading.  */
+  si = 0;
+#endif
+
+  pci_write32 (0xff, 0x0, 0x0, 0x80,
+	       (pci_read32 (0xff, 0x0, 0x0, 0x80) & 0xfffffefc) | 0x10000 | si);
+#if !REAL
+  outb (0x1, 0x62);
+  outb (0x4, 0x62);
+  pci_write32 (SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+#endif
+  gav (read32 (DEFAULT_RCBA | 0x3410));
+  write32 (DEFAULT_RCBA | 0x3410, 0xc61);
+  gav (read32 (DEFAULT_RCBA | 0x3410));
+#if !REAL
+  pci_write32 (SOUTHBRIDGE, PMBASE, 0x400);
+  pci_write8 (SOUTHBRIDGE, ACPI_CNTL, 0x80);
+#endif
+
+  u16 t4041 = read_tco16 (0x8);
+  gav (t4041);
+  write_tco16 (0x8, t4041);
+  pci_write32 (SOUTHBRIDGE, 0xd0, 0x0);
+#if !REAL
+  pci_write16 (SOUTHBRIDGE, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | COMA_LPC_EN);
+#endif
+
+  u32 t4046 = pci_read32 (SOUTHBRIDGE, 0xdc);
+  gav (t4046);
+  pci_write32 (SOUTHBRIDGE, BIOS_CNTL, t4046);
+#if !REAL
+  pci_write32 (QUICKPATH_BUS, 0x0, 0x1, 0x50, DEFAULT_PCIEXBAR | 1);
+  pci_write32 (SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+#endif
+  gav (read32 (DEFAULT_RCBA | 0x3410));
+  write32 (DEFAULT_RCBA | 0x3410, 0xc61);
+
+#if !REAL
+  pci_write32 (SOUTHBRIDGE, LPC_GEN1_DEC, 0x7c1601);
+  pci_write32 (SOUTHBRIDGE, LPC_GEN3_DEC, 0x1c1681);
+  outb (0x2, 0x62);
+
+  my_write_msr (0x79, 0xffec1410);
+  //Unrecognised: [ffff000:fc22] 00c0.00c1   Microcode Update: ERROR: Cannot fake write in a post-hook.
+
+  //Unrecognised: [ffff000:fb6a] 00c8.00c9   CPUID: eax: 00000006; ecx: 0000008b => 00000005.00000002.00000001.00000000
+#endif
+
+  {
+    u8 reg8;
+    struct cpuid_result result;
+    result = cpuid_ext (0x6, 0x8b);
+    if (!(result.eax & 0x2))
+      {
+	reg8 = ((my_read_msr (0xce) & 0xff00) >> 8) + 1;
+	my_write_msr (0x199, (my_read_msr (0x199) & ~0xffULL) | reg8);
+	my_write_msr (0x1a0, (my_read_msr (0x1a0) & ~0x0000004000000000ULL) | 0x10000);
+      }
+
+    reg8 = ((my_read_msr (0xce) & 0xff00) >> 8);
+    my_write_msr (0x199, (my_read_msr (0x199) & ~0xffULL) | reg8);
+    my_write_msr (0x1a0, my_read_msr (0x1a0) | 0x10000);
+    my_write_msr (0x1f1, my_read_msr (0x1f1) | 1);
+  }
+
+#if !REAL
+  outb (0x5, 0x62);
+
+  /*Unrecognised: [ffff000:fc9f] 00ed.00ee   LAPIC: [00000300] <= 000c4500
+
+    Unrecognised: [ffff000:fc9f] 00ed.00ef   LAPIC: [00000300] => 000c0500
+  */
+  outb (0x3, 0x62);
+
+  outb (0x0, 0x62);
+  outb (0x2, 0x62);
+  outb (0x2c, 0x62);
+  outb (0x12, 0x62);
+  outb (0x30, 0x62);
+  /*Unrecognised: addr ff7ff7da val ff7ff856*/
+
+  outb (0x13, 0x62);
+  outb (0x28, 0x62);
+  outb (0x29, 0x62);
+  outb (0x17, 0x62);
+  outb (0x27, 0x62);
+  outb (0x4a, 0x62);
+  /*Unrecognised: addr ff7ff7da val ff7ff856*/
+
+  gav (pci_mm_read16 (SOUTHBRIDGE, PMBASE)); // = 0x1001
+
+  outb (0x11, 0x62);
+  outb (0x40, 0x62);
+
+  pci_write32 (NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+#endif
+
+  pci_write32 (0, 0x1f, 0x3, SMB_BASE, SMBUS_IO_BASE);
+  pci_write32 (0, 0x1f, 0x3, HOSTC, 0x1);
+  gav (pci_read16 (0, 0x1f, 0x3, 0x4)); // = 0x1
+  pci_write16 (0, 0x1f, 0x3, 0x4, 0x1);
+#if !REAL
+  pci_write32 (SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
+  gav (pci_mm_read8 (HECIDEV, PCI_VENDOR_ID)); // = 0x86
+  pci_write32 (SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+  gav (pci_read32 (SOUTHBRIDGE, PMBASE)); // = 0x1001
+  pci_write32 (SOUTHBRIDGE, PMBASE, 0x1001);
+  gav (pci_read8 (SOUTHBRIDGE, ACPI_CNTL)); // = 0x80
+  pci_write8 (SOUTHBRIDGE, ACPI_CNTL, 0x80);
+#endif
+  gav (pci_read8 (SOUTHBRIDGE, 0xa6)); // = 0x2
+  pci_write8 (SOUTHBRIDGE, 0xa6, 0x2);
+#if !REAL
+  gav (pci_read32 (SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+  pci_write32 (SOUTHBRIDGE, GPIOBASE, DEFAULT_GPIOBASE | 1);
+  gav (pci_read8 (SOUTHBRIDGE, GPIO_CNTL)); // = 0x10
+  pci_write8 (SOUTHBRIDGE, GPIO_CNTL, 0x10);
+  gav (pci_read8 (SOUTHBRIDGE, 0x8)); // = 0x6
+  gav (pci_read8 (SOUTHBRIDGE, 0x8)); // = 0x6
+  gav (read32 (DEFAULT_RCBA | 0x3598));
+  gav (pci_read32 (0, 0x1d, 0x0, 0xfc)); // = 0x20191708
+  pci_write32 (0, 0x1d, 0x0, 0xfc, 0x20191708);
+  gav (pci_read8 (SOUTHBRIDGE, 0x8)); // = 0x6
+  gav (pci_read8 (SOUTHBRIDGE, 0x8)); // = 0x6
+  gav (pci_read8 (0, 0x1d, 0x0, 0x88)); // = 0xa0
+  pci_write8 (0, 0x1d, 0x0, 0x88, 0xa0);
+  gav (pci_read32 (0, 0x1a, 0x0, 0xfc)); // = 0x20191708
+  pci_write32 (0, 0x1a, 0x0, 0xfc, 0x20191708);
+  gav (pci_read8 (SOUTHBRIDGE, 0x8)); // = 0x6
+  gav (pci_read8 (SOUTHBRIDGE, 0x8)); // = 0x6
+  gav (pci_read8 (0, 0x1a, 0x0, 0x88)); // = 0xa0
+  pci_write8 (0, 0x1a, 0x0, 0x88, 0xa0);
+  write8 (DEFAULT_RCBA | 0x14, 0x11);
+  write16 (DEFAULT_RCBA | 0x50, 0x7654);
+#endif
+
+  enable_hpet ();
+  u32 t4143 = read32 (0xfed00010);
+  gav (t4143);
+  write32 (0xfed00010, t4143 | 1);
+  gav (read8 (DEFAULT_RCBA | 0x3428));
+  write8 (DEFAULT_RCBA | 0x3428, 0x1d);
+  pci_mm_write32 (0, 0x1f, 0x6, 0x40, 0x40000000);
+  pci_mm_write32 (0, 0x1f, 0x6, 0x44, 0x0);
+  gav (pci_mm_read32 (0, 0x1f, 0x6, 0x40)); // = 0x40000004
+  pci_mm_write32 (0, 0x1f, 0x6, 0x40, 0x40000005);
+  u16 t4;
+  t4 = read16 (0x4000001a);
+  gav (t4);
+  write16 (0x4000001a, (t4 & ~0xf) | 0x10f0);
+  gav (pci_mm_read32 (0, 0x1f, 0x6, 0x40)); // = 0x40000005
+  pci_mm_write32 (0, 0x1f, 0x6, 0x40, 0x40000004);
+  pci_mm_write32 (0, 0x1f, 0x6, 0x40, 0x0);
+#if !REAL
+  pci_read16 (SOUTHBRIDGE, PMBASE); // = 0x1001
+  pci_read16 (SOUTHBRIDGE, GPIOBASE); // = DEFAULT_GPIOBASE | 1
+#endif
+  gav (read8 (DEFAULT_RCBA | 0x3414));
+  gav (read_acpi16 (0x0));
+}
+
+static void
+pre_raminit_2a (void)
+{
+  pci_mm_write8 (SOUTHBRIDGE, GEN_PMCON_3,
+		 (gav (pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_3)) & ~2) | 1);
+
+  pci_mm_write8 (0, 0x3, 0x0, 0x4, 0x0);
+  write16 (DEFAULT_RCBA | 0x3124, 0x2321);
+  pci_mm_write8 (SOUTHBRIDGE, 0xdc, 0x0);
+
+#if !REAL
+  pci_mm_write32 (SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1);
+#endif
+  gav (pci_mm_read16 (SOUTHBRIDGE, LPC_IO_DEC)); // = 0x10
+  pci_mm_write16 (SOUTHBRIDGE, LPC_IO_DEC, 0x10);
+#if !REAL
+  pci_mm_write16 (SOUTHBRIDGE, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN);
+#endif
+}
+
+static void
+pre_raminit_2b (void)
+{
+#if !REAL
+  pci_mm_write16 (SOUTHBRIDGE, GPIOBASE, DEFAULT_GPIOBASE);
+  pci_mm_read8 (SOUTHBRIDGE, GPIO_CNTL); // = 0x10
+  pci_mm_write8 (SOUTHBRIDGE, GPIO_CNTL, 0x10);
+  gav (inw (DEFAULT_GPIOBASE | 0x38)); // = 0x10
+
+  outl (0x1963a5ff, DEFAULT_GPIOBASE);
+  outl (0xffffffff, DEFAULT_GPIOBASE | 0xc);
+  outl (0x87bf6aff, DEFAULT_GPIOBASE | 0x4);
+  outl (0x0, DEFAULT_GPIOBASE | 0x18);
+  outl (0x120c6, DEFAULT_GPIOBASE | 0x2c);
+  outl (0x27706fe, DEFAULT_GPIOBASE | 0x30);
+  outl (0x29fffff, DEFAULT_GPIOBASE | 0x38);
+  outl (0x1b01f9f4, DEFAULT_GPIOBASE | 0x34);
+  outl (0x0, DEFAULT_GPIOBASE | 0x40);
+  outl (0x0, DEFAULT_GPIOBASE | 0x48);
+  outl (0xf00, DEFAULT_GPIOBASE | 0x44);
+
+  pci_mm_write16 (SOUTHBRIDGE, PMBASE, DEFAULT_PMBASE);
+  gav (pci_mm_read8 (SOUTHBRIDGE, ACPI_CNTL)); // = 0x80
+  pci_mm_write8 (SOUTHBRIDGE, ACPI_CNTL, 0x80);
+#endif
+  pci_mm_write32 (SOUTHBRIDGE, ETR3, gav (pci_mm_read32 (SOUTHBRIDGE, ETR3)) & ~ETR3_CF9GR); // OK
+#if !REAL
+  pci_mm_write32 (SOUTHBRIDGE, LPC_GEN1_DEC, 0xc0681);
+#endif
+
+  gav (read32 (DEFAULT_RCBA | 0x3400));
+  write32 (DEFAULT_RCBA | 0x3400, 0x1c);
+  gav (read32 (DEFAULT_RCBA | 0x3410));
+  write32 (DEFAULT_RCBA | 0x3410, 0xc61);
+
+  gav (read_tco16 (0x8));
+  write_tco16 (0x8, 0x800);
+  write_tco8 (0x6, gav (read_tco8 (0x6)) | 0x2);
+#if !REAL
+  gav (inb (0x61)); // = 0x2
+  outb (0x3c, 0x61);
+#endif
+  enable_hpet ();
+#if !REAL
+  if (pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_3) & 4)
+    {
+      nvram_write (0xa, nvram_read (0xa) | 0x70);
+      nvram_write (0xb, nvram_read (0xb) | 0x80);
+      nvram_write (0xa, nvram_read (0xa) & ~0x50);
+      nvram_write (0xb, nvram_read (0xb) & ~0x80);
+    }
+#endif
+  gav (read32 (DEFAULT_RCBA | 0x3410));   
+  write32 (DEFAULT_RCBA | 0x3410, 0xc61);
+  gav (pci_read8 (SOUTHBRIDGE, 0x8)); // = 0x6
+#if !REAL
+  gav (inl (DEFAULT_GPIOBASE)); // = 0x6
+  outl (0x7963a5ff, DEFAULT_GPIOBASE);
+  gav (inl (DEFAULT_GPIOBASE | 0x4)); // = 0x7963a5ff
+  outl (0x87bf6aff, DEFAULT_GPIOBASE | 0x4);
+  outl (gav (inl (DEFAULT_GPIOBASE | 0xc)) | 0x40000000, DEFAULT_GPIOBASE | 0xc);
+  gav (inl (DEFAULT_GPIOBASE | 0x60)); // = 0xfffbfffb
+  outl (0x41000000, DEFAULT_GPIOBASE | 0x60);
+  pci_write32 (SOUTHBRIDGE, LPC_GEN3_DEC, 0x1c1681);
+  pci_write32 (SOUTHBRIDGE, LPC_GEN2_DEC, 0xc15e1);
+  pci_write32 (SOUTHBRIDGE, LPC_GEN1_DEC, 0x7c1601);
+  gav (inl (DEFAULT_GPIOBASE | 0xc)); // = 0x7c1601
+  outb (0x15, 0x62);
+  outb (0x16, 0x62);
+#endif
+}
+
+static void
+pre_raminit_4a (int x2ca8)
+{
+  int i;
+
+#if !REAL
+  outb (0x55, 0x62);
+
+  outb (0x32, 0x62);
+  /*Unrecognised: addr ff7ff7da val ff7ff856*/
+
+  gav (pci_read32 (0, 0x1f, 0x3, 0x0)); // = 0x3b308086
+#endif
+  pci_write32 (0, 0x1f, 0x3, 0x20, 0x1100);
+  gav (pci_read8 (0, 0x1f, 0x3, 0x4)); // = 0x1
+  pci_write8 (0, 0x1f, 0x3, 0x4, 0x1);
+  gav (pci_read8 (0, 0x1f, 0x3, 0x40)); // = 0x1
+  pci_write8 (0, 0x1f, 0x3, 0x40, 0x9);
+  gav (pci_read8 (0, 0x1f, 0x3, 0x40)); // = 0x1
+  pci_write8 (0, 0x1f, 0x3, 0x40, 0x1);
+#if !REAL
+  outb (0x4f, 0x62);
+  outb (0x50, 0x62);
+#endif
+  /*Unrecognised: addr ff7ff7da val ff7ff856*/
+
+  gav (pci_read8 (NORTHBRIDGE, D0F0_CAPID0 + 8)); // = 0x88
+  my_read_msr (0x17);// !!!
+  /*Unrecognised: [0000:fffaf715] 1a183.1a184   Microcode Update: ERROR: Cannot fake write in a post-hook.*/
+
+  my_read_msr (0x17);// !!!
+  /*Unrecognised: [0000:fffaf715] 1a25d.1a25e   Microcode Update: ERROR: Cannot fake write in a post-hook.*/
+
+#if !REAL
+  outb (0x48, 0x62);
+#endif
+  if (x2ca8 != 0)
+    {
+      outb (0x42, 0x15ec);
+      gav (inb (0x15ee)); // = 0x42
+    }
+
+#if REAL
+  /* Enable SMBUS. */
+  enable_smbus();
+#endif
+
+  gav (pci_mm_read16 (SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+  u16 t3;
+
+  if (x2ca8 == 0)
+    {
+      gav (t3 = inw (DEFAULT_GPIOBASE | 0x38));
+      outw (t3 & ~0x400, DEFAULT_GPIOBASE | 0x38);
+      gav (smbus_read_byte (0x5c, 0x06));
+      smbus_write_byte (0x5c, 0x06, 0x8f);
+       
+      for (i = 0; i < 5; i++)
+	pm_wait (0x3e8);
+
+      gav (smbus_read_byte (0x5c, 0x07));
+      smbus_write_byte (0x5c, 0x07, 0x8f);
+       
+      for (i = 0; i < 5; i++)
+	pm_wait (0x3e8);
+      gav (pci_mm_read16 (SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+      outw (t3 | 0x400, DEFAULT_GPIOBASE | 0x38);
+      outb (0x42, 0x15ec);
+      gav (inb (0x15ee)); // = 0x42
+      gav (pci_mm_read16 (SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+    }
+
+  gav (t3 = inw (DEFAULT_GPIOBASE | 0x38));
+  outw (t3 & ~0x400, DEFAULT_GPIOBASE | 0x38);
+
+  gav (smbus_read_byte (0x57, 0x55));
+  gav (pci_mm_read16 (SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1
+  outw (t3 | 0x400, DEFAULT_GPIOBASE | 0x38);
+
+#if !REAL
+  outb (0x42, 0x62);
+#endif
+  gav (read_tco16 (0x6));
+#if !REAL
+  pci_mm_write32 (NORTHBRIDGE, PCI_SUBSYSTEM_VENDOR_ID, 0x219317aa);
+  pci_mm_write32 (0, 0x1, 0x0, 0x8c, 0x219417aa);
+  pci_mm_write32 (0xff, 0, 0, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+  pci_mm_write32 (0xff, 0, 1, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+  pci_mm_write32 (0xff, 2, 0, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+  pci_mm_write32 (0xff, 2, 1, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_MCHBAR_HI, 0x0);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_DMIBAR_HI, 0x0);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
+  pci_mm_write32 (NORTHBRIDGE, D0F0_EPBAR_HI, 0x0);
+  pci_mm_read32 (NORTHBRIDGE, D0F0_MCHBAR_LO); // = DEFAULT_MCHBAR | 1
+  pci_mm_read32 (NORTHBRIDGE, D0F0_MCHBAR_HI); // = 0x0
+#endif
+  gav (read8 (DEFAULT_DMIBAR | 0x254));
+  write8 (DEFAULT_DMIBAR | 0x254, 0x1);
+  gav (pci_mm_read32 (SOUTHBRIDGE, 0xec)); // = 0x2b83806
+  write16 (DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+  pci_mm_write16 (NORTHBRIDGE, D0F0_DEVEN, pci_mm_read16 (NORTHBRIDGE, D0F0_DEVEN) & 0xfeff);
+  read_mchbar16 (0x48);
+  write_mchbar16 (0x48, 0x2);
+  my_read_msr (0x17);
+
+  pci_mm_read32 (NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1
+  if (pci_mm_read16 (0, 0x1, 0x0, 0x0) != 0xffff)
+    {
+      gav (pci_mm_read16 (0, 0x1, 0x0, 0xac));
+      pci_mm_write32 (0, 0x1, 0x0, 0x200, pci_mm_read32 (0, 0x1, 0x0, 0x200) & ~0x100);
+      pci_mm_write8 (0, 0x1, 0x0, 0x1f8, (pci_mm_read8 (0, 0x1, 0x0, 0x1f8) & ~1) | 4);
+      u32 t4431 = read32 (DEFAULT_DMIBAR | 0xd68);
+      gav (t4431);
+      write32 (DEFAULT_DMIBAR | 0xd68, t4431 | 0x08000000);
+      pci_mm_write32 (0, 0x1, 0x0, 0x200, pci_mm_read32 (0, 0x1, 0x0, 0x200) & ~0x00200000);
+      gav (pci_mm_read8 (0, 0x1, 0x0, 0xd60)); // = 0x0
+      gav (pci_mm_read8 (0, 0x1, 0x0, 0xd60)); // = 0x0
+      pci_mm_write8 (0, 0x1, 0x0, 0xd60, 0x3);
+      gav (pci_mm_read16 (0, 0x1, 0x0, 0xda8)); // = 0xbf9
+      gav (pci_mm_read16 (0, 0x1, 0x0, 0xda8)); // = 0xbf9
+      pci_mm_write16 (0, 0x1, 0x0, 0xda8, 0xf9);
+      pci_mm_read16 (0, 0x1, 0x0, 0xda8); // = 0xf9
+      pci_mm_read16 (0, 0x1, 0x0, 0xda8); // = 0xf9
+      pci_mm_write16 (0, 0x1, 0x0, 0xda8, 0x79);
+      pci_mm_read8 (0, 0x1, 0x0, 0xd0); // = 0x2
+      pci_mm_read8 (0, 0x1, 0x0, 0xd0); // = 0x2
+      pci_mm_write8 (0, 0x1, 0x0, 0xd0, 0x1);
+      pci_mm_read16 (0, 0x1, 0x0, 0x224); // = 0xd
+      pci_mm_read32 (NORTHBRIDGE, D0F0_CAPID0); // = 0x10c0009
+      pci_mm_read32 (NORTHBRIDGE, D0F0_CAPID0 + 4); // = 0x316126
+      pci_mm_read16 (0, 0x1, 0x0, 0x224); // = 0xd
+      pci_mm_write16 (0, 0x1, 0x0, 0x224, 0x1d);
+      pci_mm_read16 (0, 0x6, 0x0, 0x0); // = 0xffff
+      pci_mm_read16 (0, 0x1, 0x0, 0x224); // = 0x1d
+      pci_mm_read16 (0, 0x6, 0x0, 0x0); // = 0xffff
+      pci_mm_write16 (0, 0x1, 0x0, 0xac, 0x4d01);
+      pci_mm_read16 (0, 0x1, 0x0, 0x224); // = 0x1d
+      pci_mm_read8 (0, 0x1, 0x0, 0xba); // = 0x0
+      pci_mm_read16 (0, 0x1, 0x0, 0x0); // = 0x8086
+      pci_mm_read32 (0, 0x1, 0x0, 0xc00); // = 0xffffffff
+      pci_mm_write32 (0, 0x1, 0x0, 0xc00, 0xffffc0fc);
+      pci_mm_read32 (0, 0x1, 0x0, 0xc04); // = 0x9600000f
+      pci_mm_write32 (0, 0x1, 0x0, 0xc04, 0x96000000);
+      pci_mm_read32 (0, 0x1, 0x0, 0xc04); // = 0x96000000
+      pci_mm_write32 (0, 0x1, 0x0, 0xc04, 0x16000000);
+      pci_mm_write32 (0, 0x1, 0x0, 0xc08, 0x0);
+    }
+  else
+    pci_mm_read16 (0, 0x1, 0x0, 0x0); // = 0xffff
+
+#if !REAL
+  pci_mm_read32 (NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1
+  pci_mm_read16 (0, 0x6, 0x0, 0x0); // = 0xffff
+  pci_mm_read16 (0, 0x6, 0x0, 0x0); // = 0xffff
+#endif
+  pci_mm_write32 (HECIDEV, HECIBAR, DEFAULT_HECIBAR);
+  pci_mm_write32 (HECIDEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+    
+  outl ((gav (inl (DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000, DEFAULT_GPIOBASE | 0x38);
+  gav (inb (DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e
+
+#if !REAL
+  pci_mm_write32 (0, 0x2, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x215a17aa);
+#endif
+  pci_mm_write8 (NORTHBRIDGE, D0F0_DEVEN, pci_mm_read8 (NORTHBRIDGE, D0F0_DEVEN) | 2);
+  pci_mm_write16 (0, 0x1, 0x0, 0x224, pci_mm_read16 (0, 0x1, 0x0, 0x224) | 1);
+  pci_mm_write16 (NORTHBRIDGE, D0F0_GGC, pci_mm_read16 (NORTHBRIDGE, D0F0_GGC) | 2);
+  pci_mm_read32 (NORTHBRIDGE, D0F0_MCHBAR_LO); // = DEFAULT_MCHBAR | 1
+  pci_mm_read32 (NORTHBRIDGE, D0F0_MCHBAR_HI); // = 0x0
+  pci_mm_read32 (NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1
+  pci_mm_read32 (NORTHBRIDGE, D0F0_DMIBAR_HI); // = 0x0
+
+#if !REAL
+  const struct { int dev, func; } bridges[] = { {0x1e, 0}, {0x1c, 0}, {0x1c, 1}, {0x1c, 2}, {0x1c, 3}, {0x1c, 4}, {0x1c, 5}, {0x1c, 6}, {0x1c, 7} };
+  for (i = 0; i < sizeof (bridges) / sizeof (bridges[0]); i++)
+    {
+      u16 dev;
+      pci_mm_write32 (0, bridges[i].dev, bridges[i].func, 0x18, 0x20200);
+      for (dev = 0; dev < 0x20; dev++)
+	{
+	  u16 vendor = pci_mm_read16 (2, dev, 0x0, 0x0);
+	  if (vendor == 0xffff)
+	    continue;
+	  pci_mm_read16 (2, dev, 0x0, 0xa);
+	}
+      pci_mm_write32 (0, bridges[i].dev, bridges[i].func, 0x18, 0x0);
+    }
+
+  pci_mm_read16 (0, 0x1, 0x0, 0x0); // = 0x8086
+  pci_mm_read8 (NORTHBRIDGE, D0F0_CAPID0 + 6); // = 0x31
+  pci_mm_read8 (0, 0x1, 0x0, 0xba); // = 0x0
+  pci_mm_read16 (0, 0x6, 0x0, 0x0); // = 0xffff
+  pci_mm_read8 (NORTHBRIDGE, D0F0_CAPID0 + 6); // = 0x31
+  pci_mm_read8 (0, 0x6, 0x0, 0xba); // = 0xff
+  pci_mm_read16 (0, 0x1, 0x0, 0x11a); // = 0x2
+  pci_mm_read16 (0, 0x6, 0x0, 0x11a); // = 0xffff
+  pci_mm_read16 (0, 0x1, 0x0, 0x0); // = 0x8086
+  pci_mm_read32 (0, 0x1, 0x0, 0x18); // = 0x0
+  pci_mm_write32 (0, 0x1, 0x0, 0x18, 0x0);
+  pci_mm_read16 (0, 0x6, 0x0, 0x0); // = 0xffff
+#endif
+}
+
+static void
+pre_raminit_4b (int s3resume)
+{
+#if !REAL
+  int i;
+
+  for (i = 0x10; i < 0x28; )
+    {
+      u32 s;
+      pci_mm_read32 (0, 0x2, 0x0, i); // = 0xffffffff
+      pci_mm_read32 (0, 0x2, 0x0, i); // = 0xffffffff
+      pci_mm_write32 (0, 0x2, 0x0, i, 0x0);
+      pci_mm_read32 (0, 0x2, 0x0, i); // = 0xffffffff
+      pci_mm_write32 (0, 0x2, 0x0, i, 0xffffffff);
+      s = pci_mm_read32 (0, 0x2, 0x0, i);
+      if (s != 0xffffffff && s != 0)
+	{
+	  if (s & 1)
+	    {
+	      pci_mm_write32 (0, 0x2, 0x0, i, s & 0x7);
+	      i += 4;
+	    }
+	  else
+	    {
+	      pci_mm_read32 (0, 0x2, 0x0, i); // = 0xffffffff
+	      pci_mm_write32 (0, 0x2, 0x0, i, s & 0xf);
+	      i += 8;
+	    }
+	}
+      else
+	i += 4;
+    }
+#endif
+
+  outb ((gav (inb (DEFAULT_GPIOBASE | 0x3a)) & ~0x2) | 0x20,
+	DEFAULT_GPIOBASE | 0x3a);
+  outb (0x50, 0x15ec);
+  outb (inb (0x15ee) & 0x70, 0x15ee);
+#if !REAL
+  pci_mm_read8 (0, 0x1d, 0x0, 0x80); // = 0x0
+  pci_mm_write8 (0, 0x1d, 0x0, 0x80, 0x1);
+  pci_mm_read8 (0, 0x1a, 0x0, 0x80); // = 0x0
+  pci_mm_write8 (0, 0x1a, 0x0, 0x80, 0x1);
+  pci_mm_write32 (HECIDEV, PCI_SUBSYSTEM_VENDOR_ID, 0x215f17aa);
+  pci_mm_write32 (0, 0x16, 0x2, PCI_SUBSYSTEM_VENDOR_ID, 0x216117aa);
+  pci_mm_write32 (0, 0x16, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x216217aa);
+  pci_mm_write32 (0, 0x1a, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x216317aa);
+  pci_mm_write32 (0, 0x1b, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x215e17aa);
+  pci_mm_write32 (0, 0x1c, 0x0, 0x94, 0x216417aa);
+  pci_mm_write32 (0, 0x1c, 0x1, 0x94, 0x216417aa);
+  pci_mm_write32 (0, 0x1c, 0x2, 0x94, 0x216417aa);
+  pci_mm_write32 (0, 0x1c, 0x3, 0x94, 0x216417aa);
+  pci_mm_write32 (0, 0x1c, 0x4, 0x94, 0x216417aa);
+  pci_mm_write32 (0, 0x1d, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x216317aa);
+  pci_mm_write32 (0, 0x1e, 0x0, 0x54, 0x216517aa);
+  pci_mm_write32 (SOUTHBRIDGE, PCI_SUBSYSTEM_VENDOR_ID, 0x216617aa);
+  pci_mm_write32 (0, 0x1f, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x216717aa);
+  pci_mm_write32 (0, 0x1f, 0x5, PCI_SUBSYSTEM_VENDOR_ID, 0x216a17aa);
+  pci_mm_write32 (0, 0x1f, 0x6, PCI_SUBSYSTEM_VENDOR_ID, 0x219017aa);
+  pci_mm_read8 (0, 0x1d, 0x0, 0x80); // = 0x1
+  pci_mm_write8 (0, 0x1d, 0x0, 0x80, 0x0);
+  pci_mm_read8 (0, 0x1a, 0x0, 0x80); // = 0x1
+  pci_mm_write8 (0, 0x1a, 0x0, 0x80, 0x0);
+  pci_mm_write32 (13, 0x0, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x213317aa);
+  pci_mm_write32 (13, 0x0, 0x1, PCI_SUBSYSTEM_VENDOR_ID, 0x213417aa);
+  pci_mm_write32 (13, 0x0, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x213617aa);
+#endif
+
+  pci_mm_write32 (HECIDEV, HECIBAR, DEFAULT_HECIBAR);
+  pci_mm_write32 (HECIDEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+  write_acpi16 (0x2, 0x0);
+  write_acpi32 (0x28, 0x0);
+  write_acpi32 (0x2c, 0x0);
+  if (!s3resume)
+    {
+      gav (read_acpi32 (0x4));
+      gav (read_acpi32 (0x20));
+      gav (read_acpi32 (0x34));
+      write_acpi16 (0x0, 0x900);
+      write_acpi32 (0x20, 0xffff7ffe);
+      write_acpi32 (0x34, 0x56974);
+      pci_mm_write8 (SOUTHBRIDGE, GEN_PMCON_3, pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_3) | 2);
+    }
+  gav (read32 (DEFAULT_RCBA | 0x3410));
+
+#if !REAL
+  if (gav (read32 (DEFAULT_RCBA | 0x3804)) & 0x4000)
+    {
+      u32 v;
+
+      write8 (DEFAULT_RCBA | 0x3894, 0x6);
+      write8 (DEFAULT_RCBA | 0x3895, 0x50);
+      write8 (DEFAULT_RCBA | 0x3896, 0x3b);
+      write8 (DEFAULT_RCBA | 0x3897, 0x14);
+      write8 (DEFAULT_RCBA | 0x3898, 0x2);
+      write8 (DEFAULT_RCBA | 0x3899, 0x3);
+      write8 (DEFAULT_RCBA | 0x389a, 0x20);
+      write8 (DEFAULT_RCBA | 0x389b, 0x5);
+      write8 (DEFAULT_RCBA | 0x389c, 0x9f);
+      write8 (DEFAULT_RCBA | 0x389d, 0x20);
+      write8 (DEFAULT_RCBA | 0x389e, 0x1);
+      write8 (DEFAULT_RCBA | 0x389f, 0x6);
+      write8 (DEFAULT_RCBA | 0x3890, 0xc);
+      gav (read8 (DEFAULT_RCBA | 0x3890));
+      write32 (DEFAULT_RCBA | 0x3808, 0x0);
+      gav (read32 (DEFAULT_RCBA | 0x3808));
+      write16 (DEFAULT_RCBA | 0x3891, 0x4242);
+      gav (read16 (DEFAULT_RCBA | 0x3891));
+      gav (read8 (DEFAULT_RCBA | 0x3890));
+      write8 (DEFAULT_RCBA | 0x3890, 0xc);
+      gav (read8 (DEFAULT_RCBA | 0x3890));
+      if ((gav (read32 (DEFAULT_RCBA | 0x3810)) & 0x20) || WTF1)
+	v = 0x2005;
+      else
+	v = 0x2015;
+      write32 (DEFAULT_RCBA | 0x38c8, v);
+      write32 (DEFAULT_RCBA | 0x38c4, 0x800000 | v);
+      gav (read32 (DEFAULT_RCBA | 0x38b0));
+      write32 (DEFAULT_RCBA | 0x38b0, 0x1000);
+      gav (read32 (DEFAULT_RCBA | 0x38b4));
+      gav (read32 (DEFAULT_RCBA | 0x38b0));
+      write32 (DEFAULT_RCBA | 0x38b0, 0x4);
+      gav (read32 (DEFAULT_RCBA | 0x38b4));
+      write32 (DEFAULT_RCBA | 0x3874, 0x1fff07d0);
+    }
+#endif
+  gav (inb (DEFAULT_GPIOBASE | 0xe)); // = 0x1fff07d0
+
+#if REAL
+  /* Enable SMBUS. */
+  enable_smbus();
+#endif
+
+  {
+    u8 block[5];
+    u16 fsbfreq = 62879;
+    smbus_block_read (0x69, 0, 5, block);
+    block[0] = fsbfreq;
+    block[1] = fsbfreq >> 8;
+
+    smbus_block_write (0x69, 0, 5, block);
+  }
+
+#if !REAL
+  outb (0x44, 0x62);
+  outb (0x3c, 0x62);
+  nvram_read (0x71);
+  my_read_msr (0xfe);
+  my_read_msr (0x201);
+  my_read_msr (0x203);
+  my_read_msr (0x205);
+  my_read_msr (0x207);
+#endif
+
+  gav (read32 (DEFAULT_RCBA | 0x3410));
+  write32 (DEFAULT_RCBA | 0x3410, 0xc61);
+  gav (read8 (0xfed40000));
+  pci_mm_read32 (0xff, 0, 0, 0x88);
+  read_mchbar32 (0x28);
+  gav (read8 (0xfed30008));
+}
+
+#if REAL
+void raminit (const int s3resume)
+#else
+void raminit (int s3resume)
+#endif
+{
+  unsigned channel, slot, lane, rank;
+  int i;
+  struct raminfo info;
+#if CONFIG_COLLECT_TIMESTAMPS
+  extern tsc_t before_spd, after_spd, before_training, after_training;
+#endif
+
+  pre_raminit ();
+
+#if !REAL
+  u16 pm1cnt;
+  gav (pm1cnt = read_acpi16 (0x4));
+  s3resume = ((pm1cnt >> 10) & 7) == 5;
+  if (s3resume)
+    {
+      u8 ra2, ra4;
+      gav (ra2 = pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_2)); // = 0xa0
+      gav (ra4 = pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_3)); // = 0x9
+      if (!(ra2 & 0x20))
+	{
+	  s3resume = 0;
+	  write_acpi16 (0x4, 0);
+	}
+    }
+#endif
+
+  pre_raminit_2a ();
+
+  if (s3resume)
+    {
+      read_mchbar32 (0x1e8);
+      write_mchbar32 (0x1e8, 0x6);
+      read_mchbar32 (0x1e8);
+      write_mchbar32 (0x1e8, 0x4);
+    }
+
+  pre_raminit_2b ();
+
+  gav (pci_read32 (NORTHBRIDGE, D0F0_MCHBAR_LO)); // = DEFAULT_MCHBAR | 1
+  u8 x2ca8;
+
+  gav (x2ca8 = read_mchbar8 (0x2ca8));
+  if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume))
+    {
+      printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+      write_mchbar8 (0x2ca8, 0);
+      outb (0xe, 0xcf9);
+#if REAL
+      while (1)
+	{
+	  asm volatile ("hlt");
+	}
+#else
+      printf ("CP5\n");
+      exit (0);
+#endif
+    }
+
+#if !REAL
+  if (!s3resume)
+  {
+    pre_raminit_3 (x2ca8);
+  }
+#endif
+
+  pre_raminit_4a (x2ca8);
+
+  write_mchbar16 (0x1170, 0xa880);
+  write_mchbar8 (0x11c1, 0x1);
+  write_mchbar16 (0x1170, 0xb880);
+  read_mchbar8 (0x1210);
+  write_mchbar8 (0x1210, 0x84);
+  pci_mm_read8 (NORTHBRIDGE, D0F0_GGC); // = 0x52
+  pci_mm_write8 (NORTHBRIDGE, D0F0_GGC, 0x2);
+  pci_mm_read8 (NORTHBRIDGE, D0F0_GGC); // = 0x2
+  pci_mm_write8 (NORTHBRIDGE, D0F0_GGC, 0x52);
+  pci_mm_read16 (NORTHBRIDGE, D0F0_GGC); // = 0xb52
+
+  pci_mm_write16 (NORTHBRIDGE, D0F0_GGC, 0xb52);
+
+  u16 deven;
+  deven = pci_mm_read16 (NORTHBRIDGE, D0F0_DEVEN); // = 0x3
+
+  if (deven & 8)
+    {
+      write_mchbar8 (0x2c30, 0x20);
+      pci_mm_read8 (0, 0x0, 0x0, 0x8); // = 0x18
+      write_mchbar16 (0x2c30, read_mchbar16 (0x2c30) | 0x200);
+      write_mchbar16 (0x2c32, 0x434);
+      read_mchbar32 (0x2c44);
+      write_mchbar32 (0x2c44, 0x1053687);
+      pci_mm_read8 (0, 0x2, 0x0, 0x62); // = 0x2
+      pci_mm_write8 (0, 0x2, 0x0, 0x62, 0x2);
+      read8 (DEFAULT_RCBA | 0x2318);
+      write8 (DEFAULT_RCBA | 0x2318, 0x47);
+      read8 (DEFAULT_RCBA | 0x2320);
+      write8 (DEFAULT_RCBA | 0x2320, 0xfc);
+    }
+
+  read_mchbar32 (0x30);
+  write_mchbar32 (0x30, 0x40);
+
+  pci_mm_read8 (SOUTHBRIDGE, 0x8); // = 0x6
+  pci_mm_read16 (NORTHBRIDGE, D0F0_GGC); // = 0xb52
+  pci_mm_write16 (NORTHBRIDGE, D0F0_GGC, 0xb50);
+  gav (read32 (DEFAULT_RCBA | 0x3428));
+  write32 (DEFAULT_RCBA | 0x3428, 0x1d);
+
+  pre_raminit_4b (s3resume);
+
+  memset (&info, 0x5a, sizeof (info));
+
+  info.last_500_command[0] = 0;
+  info.last_500_command[1] = 0;
+
+  info.fsb_frequency = 135 * 2;
+  info.board_lane_delay[0] = 0x14;
+  info.board_lane_delay[1] = 0x07;
+  info.board_lane_delay[2] = 0x07;
+  info.board_lane_delay[3] = 0x08;
+  info.board_lane_delay[4] = 0x56;
+  info.board_lane_delay[5] = 0x04;
+  info.board_lane_delay[6] = 0x04;
+  info.board_lane_delay[7] = 0x05;
+  info.board_lane_delay[8] = 0x10;
+
+  info.training.reg_178 = 0;
+  info.training.reg_10b = 0;
+
+  info.heci_bar = 0;
+  info.memory_reserved_for_heci_mb = 0;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+  before_spd = rdtsc ();
+#endif
+
+  if (!s3resume || REAL)
+    {
+      pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
+
+      collect_system_info (&info);
+
+#if REAL
+      /* Enable SMBUS. */
+      enable_smbus();
+#endif
+
+      memset (&info.populated_ranks, 0, sizeof (info.populated_ranks));
+
+      info.use_ecc = 1;
+      for (channel = 0; channel < NUM_CHANNELS; channel++)
+	for (slot = 0; slot < NUM_CHANNELS; slot++)
+	  {
+	    int v;
+	    int try;
+	    int addr;
+	    const u8 useful_addresses[] = 
+	      {
+		DEVICE_TYPE,
+		MODULE_TYPE,
+		DENSITY,
+		RANKS_AND_DQ,
+		MEMORY_BUS_WIDTH,
+		TIMEBASE_DIVIDEND,
+		TIMEBASE_DIVISOR,
+		CYCLETIME,
+		CAS_LATENCIES_LSB,
+		CAS_LATENCIES_MSB,
+		CAS_LATENCY_TIME,
+		0x11, 0x12, 0x13, 0x14, 0x15,
+		0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
+		THERMAL_AND_REFRESH,
+		0x20,
+		REFERENCE_RAW_CARD_USED,
+		RANK1_ADDRESS_MAPPING,
+		0x75, 0x76, 0x77, 0x78,
+		0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
+		0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95
+	      };
+	    if (slot)
+	      continue;
+	    for (try = 0; try < 5; try++)
+	      {
+		v = smbus_read_byte (0x50 + channel, DEVICE_TYPE);
+		if (v >= 0)
+		  break;
+	      }
+	    if (v < 0)
+	      continue;
+	    for (addr = 0; addr < sizeof (useful_addresses) / sizeof (useful_addresses[0]); addr++)
+	      gav (info.spd[channel][0][useful_addresses[addr]] = smbus_read_byte (0x50 + channel, useful_addresses[addr]));
+	    if (info.spd[channel][0][DEVICE_TYPE] != 11 )
+	      die ("Only DDR3 is supported");
+
+	    v = info.spd[channel][0][RANKS_AND_DQ];
+	    info.populated_ranks[channel][0][0] = 1;
+	    info.populated_ranks[channel][0][1] = ((v >> 3) & 7);
+	    if (((v >> 3) & 7) > 1)
+	      die ("At most 2 ranks are supported");
+	    if ((v & 7) == 0 || (v & 7) > 2) 
+	      die ("Only x8 and x16 modules are supported");
+	    if ((info.spd[channel][slot][MODULE_TYPE] & 0xF) != 2
+		&& (info.spd[channel][slot][MODULE_TYPE] & 0xF) != 3)
+	      die ("Registered memory is not supported");
+	    info.is_x16_module[channel][0] = (v & 7) - 1;
+	    info.density[channel][slot] = info.spd[channel][slot][DENSITY] & 0xF;
+	    if (!(info.spd[channel][slot][MEMORY_BUS_WIDTH] & 0x18))
+	      info.use_ecc = 0;
+	  }
+
+      gav (0x55);
+
+      for (channel = 0; channel < NUM_CHANNELS; channel++)
+	{
+	  int v = 0;
+	  for (slot = 0; slot < NUM_SLOTS; slot++)
+	    for (rank = 0; rank < NUM_RANKS; rank++)
+	      v |= info.populated_ranks[channel][slot][rank] << (2 * slot + rank);
+	  info.populated_ranks_mask[channel] = v;
+	}
+
+      gav (0x55);
+
+      gav (pci_mm_read32 (NORTHBRIDGE, D0F0_CAPID0 + 4));
+    }
+  else
+    {
+      memset (info.populated_ranks, 0, sizeof (info.populated_ranks));
+#if 0
+      info.populated_ranks[0][0][0] = 1;
+      info.populated_ranks[0][0][1] = 1;
+      info.populated_ranks_mask[0] = 3;
+      info.populated_ranks_mask[1] = 0;
+      info.use_ecc = 0;
+      info.max_slots_used_in_channel = 1;
+
+      info.spd[0][0][0x02] = 0x0b;
+      info.spd[0][0][0x03] = 0x03;
+      info.spd[0][0][0x04] = 0x03;
+      info.spd[0][0][0x07] = 0x09;
+      info.spd[0][0][0x08] = 0x03;
+      info.spd[0][0][0x0a] = 0x01;
+      info.spd[0][0][0x0b] = 0x08;
+      info.spd[0][0][0x0c] = 0x0c;
+      info.spd[0][0][0x0e] = 0x3e;
+      info.spd[0][0][0x0f] = 0x00;
+      info.spd[0][0][0x10] = 0x69;
+      info.spd[0][0][0x11] = 0x78;
+      info.spd[0][0][0x12] = 0x69;
+      info.spd[0][0][0x13] = 0x30;
+      info.spd[0][0][0x14] = 0x69;
+      info.spd[0][0][0x15] = 0x11;
+      info.spd[0][0][0x16] = 0x20;
+      info.spd[0][0][0x17] = 0x89;
+      info.spd[0][0][0x18] = 0x00;
+      info.spd[0][0][0x19] = 0x05;
+      info.spd[0][0][0x1a] = 0x3c;
+      info.spd[0][0][0x1b] = 0x3c;
+      info.spd[0][0][0x1c] = 0x00;
+      info.spd[0][0][0x1d] = 0xf0;
+      info.spd[0][0][0x1f] = 0x05;
+      info.spd[0][0][0x20] = 0x00;
+      info.spd[0][0][0x3e] = 0x05;
+      info.spd[0][0][0x3f] = 0x00;
+      info.spd[0][0][0x75] = 0x80;
+      info.spd[0][0][0x76] = 0xad;
+      info.spd[0][0][0x77] = 0x01;
+      info.spd[0][0][0x78] = 0x10;
+      info.spd[0][0][0x79] = 0x52;
+      info.spd[0][0][0x7a] = 0x26;
+      info.spd[0][0][0x7b] = 0x50;
+      info.spd[0][0][0x7c] = 0xf4;
+      info.spd[0][0][0x7d] = 0x7d;
+      info.spd[0][0][0x7e] = 0xb0;
+      info.spd[0][0][0x7f] = 0xcf;
+      info.spd[0][0][0x80] = 0x48;
+      info.spd[0][0][0x81] = 0x4d;
+      info.spd[0][0][0x82] = 0x54;
+      info.spd[0][0][0x83] = 0x33;
+      info.spd[0][0][0x84] = 0x35;
+      info.spd[0][0][0x85] = 0x31;
+      info.spd[0][0][0x86] = 0x53;
+      info.spd[0][0][0x87] = 0x36;
+      info.spd[0][0][0x88] = 0x42;
+      info.spd[0][0][0x89] = 0x46;
+      info.spd[0][0][0x8a] = 0x52;
+      info.spd[0][0][0x8b] = 0x38;
+      info.spd[0][0][0x8c] = 0x43;
+      info.spd[0][0][0x8d] = 0x2d;
+      info.spd[0][0][0x8e] = 0x48;
+      info.spd[0][0][0x8f] = 0x39;
+      info.spd[0][0][0x90] = 0x20;
+      info.spd[0][0][0x91] = 0x20;
+      info.spd[0][0][0x92] = 0x4e;
+      info.spd[0][0][0x93] = 0x30;
+      info.spd[0][0][0x94] = 0x80;
+      info.spd[0][0][0x95] = 0xad;
+#else
+      info.populated_ranks[0][0][0] = 1;
+      info.populated_ranks[0][0][1] = 1;
+      info.populated_ranks[1][0][0] = 1;
+      info.populated_ranks[1][0][1] = 1;
+      info.populated_ranks_mask[0] = 3;
+      info.populated_ranks_mask[1] = 3;
+      info.use_ecc = 0;
+      info.max_slots_used_in_channel = 1;
+
+      info.spd[0][0][0x02] = 0x0b;
+      info.spd[0][0][0x03] = 0x03;
+      info.spd[0][0][0x04] = 0x03;
+      info.spd[0][0][0x07] = 0x09;
+      info.spd[0][0][0x08] = 0x03;
+      info.spd[0][0][0x0a] = 0x01;
+      info.spd[0][0][0x0b] = 0x08;
+      info.spd[0][0][0x0c] = 0x0c;
+      info.spd[0][0][0x0e] = 0x3e;
+      info.spd[0][0][0x0f] = 0x00;
+      info.spd[0][0][0x10] = 0x69;
+      info.spd[0][0][0x11] = 0x78;
+      info.spd[0][0][0x12] = 0x69;
+      info.spd[0][0][0x13] = 0x30;
+      info.spd[0][0][0x14] = 0x69;
+      info.spd[0][0][0x15] = 0x11;
+      info.spd[0][0][0x16] = 0x20;
+      info.spd[0][0][0x17] = 0x89;
+      info.spd[0][0][0x18] = 0x00;
+      info.spd[0][0][0x19] = 0x05;
+      info.spd[0][0][0x1a] = 0x3c;
+      info.spd[0][0][0x1b] = 0x3c;
+      info.spd[0][0][0x1c] = 0x00;
+      info.spd[0][0][0x1d] = 0xf0;
+      info.spd[0][0][0x1f] = 0x05;
+      info.spd[0][0][0x20] = 0x00;
+      info.spd[0][0][0x3e] = 0x05;
+      info.spd[0][0][0x3f] = 0x00;
+      info.spd[0][0][0x75] = 0x80;
+      info.spd[0][0][0x76] = 0xad;
+      info.spd[0][0][0x77] = 0x01;
+      info.spd[0][0][0x78] = 0x10;
+      info.spd[0][0][0x79] = 0x52;
+      info.spd[0][0][0x7a] = 0x26;
+      info.spd[0][0][0x7b] = 0x50;
+      info.spd[0][0][0x7c] = 0xf4;
+      info.spd[0][0][0x7d] = 0x7d;
+      info.spd[0][0][0x7e] = 0xb0;
+      info.spd[0][0][0x7f] = 0xcf;
+      info.spd[0][0][0x80] = 0x48;
+      info.spd[0][0][0x81] = 0x4d;
+      info.spd[0][0][0x82] = 0x54;
+      info.spd[0][0][0x83] = 0x33;
+      info.spd[0][0][0x84] = 0x35;
+      info.spd[0][0][0x85] = 0x31;
+      info.spd[0][0][0x86] = 0x53;
+      info.spd[0][0][0x87] = 0x36;
+      info.spd[0][0][0x88] = 0x42;
+      info.spd[0][0][0x89] = 0x46;
+      info.spd[0][0][0x8a] = 0x52;
+      info.spd[0][0][0x8b] = 0x38;
+      info.spd[0][0][0x8c] = 0x43;
+      info.spd[0][0][0x8d] = 0x2d;
+      info.spd[0][0][0x8e] = 0x48;
+      info.spd[0][0][0x8f] = 0x39;
+      info.spd[0][0][0x90] = 0x20;
+      info.spd[0][0][0x91] = 0x20;
+      info.spd[0][0][0x92] = 0x4e;
+      info.spd[0][0][0x93] = 0x30;
+      info.spd[0][0][0x94] = 0x80;
+      info.spd[0][0][0x95] = 0xad;
+
+      info.spd[1][0][0x02] = 0x0b;
+      info.spd[1][0][0x03] = 0x03;
+      info.spd[1][0][0x04] = 0x03;
+      info.spd[1][0][0x07] = 0x09;
+      info.spd[1][0][0x08] = 0x03;
+      info.spd[1][0][0x0a] = 0x01;
+      info.spd[1][0][0x0b] = 0x08;
+      info.spd[1][0][0x0c] = 0x0c;
+      info.spd[1][0][0x0e] = 0x3e;
+      info.spd[1][0][0x0f] = 0x00;
+      info.spd[1][0][0x10] = 0x69;
+      info.spd[1][0][0x11] = 0x78;
+      info.spd[1][0][0x12] = 0x69;
+      info.spd[1][0][0x13] = 0x30;
+      info.spd[1][0][0x14] = 0x69;
+      info.spd[1][0][0x15] = 0x11;
+      info.spd[1][0][0x16] = 0x20;
+      info.spd[1][0][0x17] = 0x89;
+      info.spd[1][0][0x18] = 0x00;
+      info.spd[1][0][0x19] = 0x05;
+      info.spd[1][0][0x1a] = 0x3c;
+      info.spd[1][0][0x1b] = 0x3c;
+      info.spd[1][0][0x1c] = 0x00;
+      info.spd[1][0][0x1d] = 0xf0;
+      info.spd[1][0][0x1f] = 0x05;
+      info.spd[1][0][0x20] = 0x00;
+      info.spd[1][0][0x3e] = 0x05;
+      info.spd[1][0][0x3f] = 0x00;
+      info.spd[1][0][0x75] = 0x80;
+      info.spd[1][0][0x76] = 0xad;
+      info.spd[1][0][0x77] = 0x01;
+      info.spd[1][0][0x78] = 0x10;
+      info.spd[1][0][0x79] = 0x52;
+      info.spd[1][0][0x7a] = 0x26;
+      info.spd[1][0][0x7b] = 0x50;
+      info.spd[1][0][0x7c] = 0xf4;
+      info.spd[1][0][0x7d] = 0x7d;
+      info.spd[1][0][0x7e] = 0xb0;
+      info.spd[1][0][0x7f] = 0xcf;
+      info.spd[1][0][0x80] = 0x48;
+      info.spd[1][0][0x81] = 0x4d;
+      info.spd[1][0][0x82] = 0x54;
+      info.spd[1][0][0x83] = 0x33;
+      info.spd[1][0][0x84] = 0x35;
+      info.spd[1][0][0x85] = 0x31;
+      info.spd[1][0][0x86] = 0x53;
+      info.spd[1][0][0x87] = 0x36;
+      info.spd[1][0][0x88] = 0x42;
+      info.spd[1][0][0x89] = 0x46;
+      info.spd[1][0][0x8a] = 0x52;
+      info.spd[1][0][0x8b] = 0x38;
+      info.spd[1][0][0x8c] = 0x43;
+      info.spd[1][0][0x8d] = 0x2d;
+      info.spd[1][0][0x8e] = 0x48;
+      info.spd[1][0][0x8f] = 0x39;
+      info.spd[1][0][0x90] = 0x20;
+      info.spd[1][0][0x91] = 0x20;
+      info.spd[1][0][0x92] = 0x4e;
+      info.spd[1][0][0x93] = 0x30;
+      info.spd[1][0][0x94] = 0x80;
+      info.spd[1][0][0x95] = 0xad;
+
+#endif
+      info.is_x16_module[0][0] = (info.spd[0][0][RANKS_AND_DQ] & 7) - 1;
+      info.density[0][0] = info.spd[0][0][DENSITY] & 0xF;
+
+      info.is_x16_module[1][0] = (info.spd[1][0][RANKS_AND_DQ] & 7) - 1;
+      info.density[1][0] = info.spd[1][0][DENSITY] & 0xF;
+    }
+
+#if CONFIG_COLLECT_TIMESTAMPS
+  after_spd = rdtsc ();
+#endif
+
+  write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8) & 0xfc);
+  my_read_msr (0x207); // !!!
+
+  collect_system_info (&info);
+  calculate_timings (&info);
+
+#if !REAL
+  pci_mm_write8 (NORTHBRIDGE, 0xdf, 0x82);
+#endif
+
+  if (!s3resume)
+    {
+      u8 reg8 = pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_2);
+      if (x2ca8 == 0 && (reg8 & 0x80))
+	{
+		/* Don't enable S4-assertion stretch. Makes trouble on roda/rk9.
+		reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08);
+		*/
+
+		/* Clear bit7. */
+	        pci_write8 (SOUTHBRIDGE, GEN_PMCON_2, (reg8 & ~(1 << 7)));
+
+		printk(BIOS_INFO, "Interrupted RAM init, reset required.\n");
+		outb (0x6, 0xcf9);
+#if REAL
+		while (1)
+		  {
+		    asm volatile ("hlt");
+		  }
+#endif
+	}
+    }
+
+#if !REAL
+  gav (read_mchbar8 (0x2ca8)); ///!!!!
+#endif
+
+  if (!s3resume && x2ca8 == 0)
+    pci_mm_write8 (SOUTHBRIDGE, GEN_PMCON_2, pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_2) | 0x80);
+
+  compute_derived_timings (&info);
+
+  if (x2ca8 == 0)
+    {
+      gav (read_mchbar8 (0x164));
+      write_mchbar8 (0x164, 0x26);
+      write_mchbar16 (0x2c20, 0x10);
+    }
+
+  write_mchbar32 (0x18b4, read_mchbar32 (0x18b4) | 0x210000); /* OK */
+  write_mchbar32 (0x1890, read_mchbar32 (0x1890) | 0x2000000); /* OK */
+  write_mchbar32 (0x18b4, read_mchbar32 (0x18b4) | 0x8000);
+	
+  gav (pci_mm_read32 (0xff, 2, 1, 0x50)); // !!!!
+  pci_mm_write8 (0xff, 2, 1, 0x54, 0x12);
+
+  gav (read_mchbar16 (0x2c10)); // !!!!
+  write_mchbar16 (0x2c10, 0x412);
+  gav (read_mchbar16 (0x2c10)); // !!!!
+  write_mchbar16 (0x2c12, read_mchbar16 (0x2c12) | 0x100); /* OK */
+
+  gav (read_mchbar8 (0x2ca8)); // !!!!
+  write_mchbar32 (0x1804, (read_mchbar32 (0x1804) & 0xfffffffc) | 0x8400080);
+
+  pci_mm_read32 (0xff, 2, 1, 0x6c); // !!!!
+  pci_mm_write32 (0xff, 2, 1, 0x6c, 0x40a0a0);
+  gav (read_mchbar32 (0x1c04)); // !!!!
+  gav (read_mchbar32 (0x1804)); // !!!!
+
+  if (x2ca8 == 0)
+    {
+      write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8) | 1);
+    }
+
+  write_mchbar32 (0x18d8, 0x120000);
+  write_mchbar32 (0x18dc, 0x30a484a);
+  pci_mm_write32 (0xff, 2, 1, 0xe0, 0x0);
+  pci_mm_write32 (0xff, 2, 1, 0xf4, 0x9444a);
+  write_mchbar32 (0x18d8, 0x40000);
+  write_mchbar32 (0x18dc, 0xb000000);
+  pci_mm_write32 (0xff, 2, 1, 0xe0, 0x60000);
+  pci_mm_write32 (0xff, 2, 1, 0xf4, 0x0);
+  write_mchbar32 (0x18d8, 0x180000);
+  write_mchbar32 (0x18dc, 0xc0000142);
+  pci_mm_write32 (0xff, 2, 1, 0xe0, 0x20000);
+  pci_mm_write32 (0xff, 2, 1, 0xf4, 0x142);
+  write_mchbar32 (0x18d8, 0x1e0000);
+ 
+  gav (read_mchbar32 (0x18dc)); // !!!!
+  write_mchbar32 (0x18dc, 0x3);
+  gav (read_mchbar32 (0x18dc)); // !!!!
+
+  if (x2ca8 == 0)
+    {
+      write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8) | 1); // guess
+    }
+
+  write_mchbar32 (0x188c, 0x20bc09);
+  pci_mm_write32 (0xff, 2, 1, 0xd0, 0x40b0c09);
+  write_mchbar32 (0x1a10, 0x4200010e);
+  write_mchbar32 (0x18b8, read_mchbar32 (0x18b8) | 0x200);
+  gav (read_mchbar32 (0x1918)); // !!!!
+  write_mchbar32 (0x1918, 0x332);
+
+  gav (read_mchbar32 (0x18b8)); // !!!!
+  write_mchbar32 (0x18b8, 0xe00);
+  gav (read_mchbar32 (0x182c)); // !!!!
+  write_mchbar32 (0x182c, 0x10202);
+  gav (pci_mm_read32 (0xff, 2, 1, 0x94)); // !!!!
+  pci_mm_write32 (0xff, 2, 1, 0x94, 0x10202);
+  write_mchbar32 (0x1a1c, read_mchbar32 (0x1a1c) & 0x8fffffff);
+  write_mchbar32 (0x1a70, read_mchbar32 (0x1a70) | 0x100000);
+
+  write_mchbar32 (0x18b4, read_mchbar32 (0x18b4) & 0xffff7fff);
+  gav (read_mchbar32 (0x1a68)); // !!!!
+  write_mchbar32 (0x1a68, 0x343800);
+  gav (read_mchbar32 (0x1e68)); // !!!!
+  gav (read_mchbar32 (0x1a68)); // !!!!
+
+  if (x2ca8 == 0)
+    {
+      write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8) | 1); // guess
+    }
+
+  pci_mm_read32 (0xff, 2, 0, 0x048); // !!!!
+  pci_mm_write32 (0xff, 2, 0, 0x048, 0x140000);
+  pci_mm_read32 (0xff, 2, 0, 0x058); // !!!!
+  pci_mm_write32 (0xff, 2, 0, 0x058, 0x64555);
+  pci_mm_read32 (0xff, 2, 0, 0x058); // !!!!
+  pci_mm_read32 (0xff, 0, 0, 0xd0); // !!!!
+  pci_mm_write32 (0xff, 0, 0, 0xd0, 0x180);
+  gav (read_mchbar32 (0x1af0)); // !!!!
+  gav (read_mchbar32 (0x1af0)); // !!!!
+  write_mchbar32 (0x1af0, 0x1f020003);
+  gav (read_mchbar32 (0x1af0)); // !!!!
+
+  if (((x2ca8 == 0)))
+    {
+      write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8) | 1); // guess
+    }
+
+  gav (read_mchbar32 (0x1890)); // !!!!
+  write_mchbar32 (0x1890, 0x80102);
+  gav (read_mchbar32 (0x18b4)); // !!!!
+  write_mchbar32 (0x18b4, 0x216000);
+  write_mchbar32 (0x18a4, 0x22222222);
+  write_mchbar32 (0x18a8, 0x22222222);
+  write_mchbar32 (0x18ac, 0x22222);
+
+  udelay (1000);
+
+  if (x2ca8 == 0)
+    {
+      if (s3resume)
+	{
+#if REAL && 0
+	  info.reg2ca9_bit0 = 0;
+	  info.reg274265[0][0] = 5;
+	  info.reg274265[0][1] = 5;
+	  info.reg274265[0][2] = 0xe;
+	  info.reg274265[1][0] = 5;
+	  info.reg274265[1][1] = 5;
+	  info.reg274265[1][2] = 0xe;
+	  info.delay46_ps[0] = 0xa86;
+	  info.delay46_ps[1] = 0xa86;
+	  info.delay54_ps[0] = 0xdc6;
+	  info.delay54_ps[1] = 0xdc6;
+#else
+	  info.reg2ca9_bit0 = 0;
+	  info.reg274265[0][0] = 3;
+	  info.reg274265[0][1] = 5;
+	  info.reg274265[0][2] = 0xd;
+	  info.reg274265[1][0] = 4;
+	  info.reg274265[1][1] = 5;
+	  info.reg274265[1][2] = 0xd;
+	  info.delay46_ps[0] = 0x110a;
+	  info.delay46_ps[1] = 0xb58;
+	  info.delay54_ps[0] = 0x144a;
+	  info.delay54_ps[1] = 0xe98;
+#endif
+	  restore_274265 (&info);
+	}
+      else
+	set_274265 (&info);
+      int j;
+      printk (BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0);
+      for (i = 0; i < 2; i++)
+	for (j = 0; j < 3; j++)
+	  printk (BIOS_DEBUG, "reg274265[%d][%d] = %x\n",i,j, info.reg274265[i][j]);
+      for (i = 0; i < 2; i++)
+	printk (BIOS_DEBUG, "delay46_ps[%d] = %x\n", i, info.delay46_ps[i]);
+      for (i = 0; i < 2; i++)
+	printk (BIOS_DEBUG, "delay54_ps[%d] = %x\n", i, info.delay54_ps[i]);
+
+      set_2dxx_series (&info);
+
+      if (!(deven & 8))
+	{
+	  read_mchbar32 (0x2cb0);
+	  write_mchbar32 (0x2cb0, 0x40);
+	}
+
+      udelay (1000);
+	
+      if (deven & 8)
+	{
+	  write_mchbar32 (0xff8, 0x1800 | read_mchbar32 (0xff8));
+	  read_mchbar32 (0x2cb0);
+	  write_mchbar32 (0x2cb0, 0x00);
+	  pci_mm_read8 (0, 0x2, 0x0, 0x4c);
+	  pci_mm_read8 (0, 0x2, 0x0, 0x4c);
+	  pci_mm_read8 (0, 0x2, 0x0, 0x4e);
+
+	  read_mchbar8 (0x1150);
+	  read_mchbar8 (0x1151);
+	  read_mchbar8 (0x1022);
+	  read_mchbar8 (0x16d0);
+	  write_mchbar32 (0x1300, 0x60606060);
+	  write_mchbar32 (0x1304, 0x60606060);
+	  write_mchbar32 (0x1308, 0x78797a7b);
+	  write_mchbar32 (0x130c, 0x7c7d7e7f);
+	  write_mchbar32 (0x1310, 0x60606060);
+	  write_mchbar32 (0x1314, 0x60606060);
+	  write_mchbar32 (0x1318, 0x60606060);
+	  write_mchbar32 (0x131c, 0x60606060);
+	  write_mchbar32 (0x1320, 0x50515253);
+	  write_mchbar32 (0x1324, 0x54555657);
+	  write_mchbar32 (0x1328, 0x58595a5b);
+	  write_mchbar32 (0x132c, 0x5c5d5e5f);
+	  write_mchbar32 (0x1330, 0x40414243);
+	  write_mchbar32 (0x1334, 0x44454647);
+	  write_mchbar32 (0x1338, 0x48494a4b);
+	  write_mchbar32 (0x133c, 0x4c4d4e4f);
+	  write_mchbar32 (0x1340, 0x30313233);
+	  write_mchbar32 (0x1344, 0x34353637);
+	  write_mchbar32 (0x1348, 0x38393a3b);
+	  write_mchbar32 (0x134c, 0x3c3d3e3f);
+	  write_mchbar32 (0x1350, 0x20212223);
+	  write_mchbar32 (0x1354, 0x24252627);
+	  write_mchbar32 (0x1358, 0x28292a2b);
+	  write_mchbar32 (0x135c, 0x2c2d2e2f);
+	  write_mchbar32 (0x1360, 0x10111213);
+	  write_mchbar32 (0x1364, 0x14151617);
+	  write_mchbar32 (0x1368, 0x18191a1b);
+	  write_mchbar32 (0x136c, 0x1c1d1e1f);
+	  write_mchbar32 (0x1370, 0x10203);
+	  write_mchbar32 (0x1374, 0x4050607);
+	  write_mchbar32 (0x1378, 0x8090a0b);
+	  write_mchbar32 (0x137c, 0xc0d0e0f);
+	  write_mchbar8 (0x11cc, 0x4e);
+	  write_mchbar32 (0x1110, 0x73970404);
+	  write_mchbar32 (0x1114, 0x72960404);
+	  write_mchbar32 (0x1118, 0x6f950404);
+	  write_mchbar32 (0x111c, 0x6d940404);
+	  write_mchbar32 (0x1120, 0x6a930404);
+	  write_mchbar32 (0x1124, 0x68a41404);
+	  write_mchbar32 (0x1128, 0x66a21404);
+	  write_mchbar32 (0x112c, 0x63a01404);
+	  write_mchbar32 (0x1130, 0x609e1404);
+	  write_mchbar32 (0x1134, 0x5f9c1404);
+	  write_mchbar32 (0x1138, 0x5c961404);
+	  write_mchbar32 (0x113c, 0x58a02404);
+	  write_mchbar32 (0x1140, 0x54942404);
+	  write_mchbar32 (0x1190, 0x900080a);
+	  write_mchbar16 (0x11c0, 0xc40b);
+	  write_mchbar16 (0x11c2, 0x303);
+	  write_mchbar16 (0x11c4, 0x301);
+	  read_mchbar32 (0x1190);
+	  write_mchbar32 (0x1190, 0x8900080a);
+	  write_mchbar32 (0x11b8, 0x70c3000);
+	  write_mchbar8 (0x11ec, 0xa);
+	  write_mchbar16 (0x1100, 0x800);
+	  read_mchbar32 (0x11bc);
+	  write_mchbar32 (0x11bc, 0x1e84800);
+	  write_mchbar16 (0x11ca, 0xfa);
+	  write_mchbar32 (0x11e4, 0x4e20);
+	  write_mchbar8 (0x11bc, 0xf);
+	  write_mchbar16 (0x11da, 0x19);
+	  write_mchbar16 (0x11ba, 0x470c);
+	  write_mchbar32 (0x1680, 0xe6ffe4ff);
+	  write_mchbar32 (0x1684, 0xdeffdaff);
+	  write_mchbar32 (0x1688, 0xd4ffd0ff);
+	  write_mchbar32 (0x168c, 0xccffc6ff);
+	  write_mchbar32 (0x1690, 0xc0ffbeff);
+	  write_mchbar32 (0x1694, 0xb8ffb0ff);
+	  write_mchbar32 (0x1698, 0xa8ff0000);
+	  write_mchbar32 (0x169c, 0xc00);
+	  write_mchbar32 (0x1290, 0x5000000);
+	}
+
+      write_mchbar32 (0x124c, 0x15040d00);
+      write_mchbar32 (0x1250, 0x7f0000);
+      write_mchbar32 (0x1254, 0x1e220004);
+      write_mchbar32 (0x1258, 0x4000004);
+      write_mchbar32 (0x1278, 0x0);
+      write_mchbar32 (0x125c, 0x0);
+      write_mchbar32 (0x1260, 0x0);
+      write_mchbar32 (0x1264, 0x0);
+      write_mchbar32 (0x1268, 0x0);
+      write_mchbar32 (0x126c, 0x0);
+      write_mchbar32 (0x1270, 0x0);
+      write_mchbar32 (0x1274, 0x0);
+    }
+
+  if ((deven & 8) && x2ca8 == 0)
+    {
+      write_mchbar16 (0x1214, 0x320);
+      write_mchbar32 (0x1600, 0x40000000);
+      read_mchbar32 (0x11f4);
+      write_mchbar32 (0x11f4, 0x10000000);
+      read_mchbar16 (0x1230);
+      write_mchbar16 (0x1230, 0x8000);
+      write_mchbar32 (0x1400, 0x13040020);
+      write_mchbar32 (0x1404, 0xe090120);
+      write_mchbar32 (0x1408, 0x5120220);
+      write_mchbar32 (0x140c, 0x5120330);
+      write_mchbar32 (0x1410, 0xe090220);
+      write_mchbar32 (0x1414, 0x1010001);
+      write_mchbar32 (0x1418, 0x1110000);
+      write_mchbar32 (0x141c, 0x9020020);
+      write_mchbar32 (0x1420, 0xd090220);
+      write_mchbar32 (0x1424, 0x2090220);
+      write_mchbar32 (0x1428, 0x2090330);
+      write_mchbar32 (0x142c, 0xd090220);
+      write_mchbar32 (0x1430, 0x1010001);
+      write_mchbar32 (0x1434, 0x1110000);
+      write_mchbar32 (0x1438, 0x11040020);
+      write_mchbar32 (0x143c, 0x4030220);
+      write_mchbar32 (0x1440, 0x1060220);
+      write_mchbar32 (0x1444, 0x1060330);
+      write_mchbar32 (0x1448, 0x4030220);
+      write_mchbar32 (0x144c, 0x1010001);
+      write_mchbar32 (0x1450, 0x1110000);
+      write_mchbar32 (0x1454, 0x4010020);
+      write_mchbar32 (0x1458, 0xb090220);
+      write_mchbar32 (0x145c, 0x1090220);
+      write_mchbar32 (0x1460, 0x1090330);
+      write_mchbar32 (0x1464, 0xb090220);
+      write_mchbar32 (0x1468, 0x1010001);
+      write_mchbar32 (0x146c, 0x1110000);
+      write_mchbar32 (0x1470, 0xf040020);
+      write_mchbar32 (0x1474, 0xa090220);
+      write_mchbar32 (0x1478, 0x1120220);
+      write_mchbar32 (0x147c, 0x1120330);
+      write_mchbar32 (0x1480, 0xa090220);
+      write_mchbar32 (0x1484, 0x1010001);
+      write_mchbar32 (0x1488, 0x1110000);
+      write_mchbar32 (0x148c, 0x7020020);
+      write_mchbar32 (0x1490, 0x1010220);
+      write_mchbar32 (0x1494, 0x10210);
+      write_mchbar32 (0x1498, 0x10320);
+      write_mchbar32 (0x149c, 0x1010220);
+      write_mchbar32 (0x14a0, 0x1010001);
+      write_mchbar32 (0x14a4, 0x1110000);
+      write_mchbar32 (0x14a8, 0xd040020);
+      write_mchbar32 (0x14ac, 0x8090220);
+      write_mchbar32 (0x14b0, 0x1111310);
+      write_mchbar32 (0x14b4, 0x1111420);
+      write_mchbar32 (0x14b8, 0x8090220);
+      write_mchbar32 (0x14bc, 0x1010001);
+      write_mchbar32 (0x14c0, 0x1110000);
+      write_mchbar32 (0x14c4, 0x3010020);
+      write_mchbar32 (0x14c8, 0x7090220);
+      write_mchbar32 (0x14cc, 0x1081310);
+      write_mchbar32 (0x14d0, 0x1081420);
+      write_mchbar32 (0x14d4, 0x7090220);
+      write_mchbar32 (0x14d8, 0x1010001);
+      write_mchbar32 (0x14dc, 0x1110000);
+      write_mchbar32 (0x14e0, 0xb040020);
+      write_mchbar32 (0x14e4, 0x2030220);
+      write_mchbar32 (0x14e8, 0x1051310);
+      write_mchbar32 (0x14ec, 0x1051420);
+      write_mchbar32 (0x14f0, 0x2030220);
+      write_mchbar32 (0x14f4, 0x1010001);
+      write_mchbar32 (0x14f8, 0x1110000);
+      write_mchbar32 (0x14fc, 0x5020020);
+      write_mchbar32 (0x1500, 0x5090220);
+      write_mchbar32 (0x1504, 0x2071310);
+      write_mchbar32 (0x1508, 0x2071420);
+      write_mchbar32 (0x150c, 0x5090220);
+      write_mchbar32 (0x1510, 0x1010001);
+      write_mchbar32 (0x1514, 0x1110000);
+      write_mchbar32 (0x1518, 0x7040120);
+      write_mchbar32 (0x151c, 0x2090220);
+      write_mchbar32 (0x1520, 0x70b1210);
+      write_mchbar32 (0x1524, 0x70b1310);
+      write_mchbar32 (0x1528, 0x2090220);
+      write_mchbar32 (0x152c, 0x1010001);
+      write_mchbar32 (0x1530, 0x1110000);
+      write_mchbar32 (0x1534, 0x1010110);
+      write_mchbar32 (0x1538, 0x1081310);
+      write_mchbar32 (0x153c, 0x5041200);
+      write_mchbar32 (0x1540, 0x5041310);
+      write_mchbar32 (0x1544, 0x1081310);
+      write_mchbar32 (0x1548, 0x1010001);
+      write_mchbar32 (0x154c, 0x1110000);
+      write_mchbar32 (0x1550, 0x1040120);
+      write_mchbar32 (0x1554, 0x4051210);
+      write_mchbar32 (0x1558, 0xd051200);
+      write_mchbar32 (0x155c, 0xd051200);
+      write_mchbar32 (0x1560, 0x4051210);
+      write_mchbar32 (0x1564, 0x1010001);
+      write_mchbar32 (0x1568, 0x1110000);
+      write_mchbar16 (0x1222, 0x220a);
+      write_mchbar16 (0x123c, 0x1fc0);
+      write_mchbar16 (0x1220, 0x1388);
+    }
+
+  read_mchbar32 (0x2c80); // !!!!
+  write_mchbar32 (0x2c80, 0x1053688);
+  read_mchbar32 (0x1c04); // !!!!
+  write_mchbar32 (0x1804, 0x406080);
+
+  read_mchbar8 (0x2ca8);
+
+  if (x2ca8 == 0)
+    {
+      write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8) & ~3);
+      write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8) + 4);
+      write_mchbar32 (0x1af0, read_mchbar32 (0x1af0) | 0x10);
+#if REAL
+      while (1)
+	{
+	  asm volatile ("hlt");
+	}
+#else
+      printf ("CP5\n");
+      exit (0);
+#endif
+    }
+
+  write_mchbar8 (0x2ca8, read_mchbar8 (0x2ca8));
+  read_mchbar32 (0x2c80); // !!!!
+  write_mchbar32 (0x2c80, 0x53688);
+  pci_mm_write32 (0xff, 0, 0, 0x60, 0x20220);
+  read_mchbar16 (0x2c20); // !!!!
+  read_mchbar16 (0x2c10); // !!!!
+  read_mchbar16 (0x2c00); // !!!!
+  write_mchbar16 (0x2c00, 0x8c0);
+  udelay (1000);
+  write_1d0 (0, 0x33d, 0, 0);
+  write_500 (&info, 0, 0, 0xb61, 0, 0);
+  write_500 (&info, 1, 0, 0xb61, 0, 0);
+  write_mchbar32 (0x1a30, 0x0);
+  write_mchbar32 (0x1a34, 0x0);
+  write_mchbar16 (0x614, 0xb5b | (info.populated_ranks[1][0][0] * 0x404) | (info.populated_ranks[0][0][0] * 0xa0));
+  write_mchbar16 (0x616, 0x26a);
+  write_mchbar32 (0x134, 0x856000);
+  write_mchbar32 (0x160, 0x5ffffff);
+  read_mchbar32 (0x114); // !!!!
+  write_mchbar32 (0x114, 0xc2024440);
+  read_mchbar32 (0x118); // !!!!
+  write_mchbar32 (0x118, 0x4);
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    write_mchbar32 (0x260 + (channel << 10), 0x30809ff | ((info.populated_ranks_mask[channel] & 3) << 20));
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_mchbar16 (0x31c + (channel << 10), 0x101);
+      write_mchbar16 (0x360 + (channel << 10), 0x909);
+      write_mchbar16 (0x3a4 + (channel << 10), 0x101);
+      write_mchbar16 (0x3e8 + (channel << 10), 0x101);
+      write_mchbar32 (0x320 + (channel << 10), 0x29002900);
+      write_mchbar32 (0x324 + (channel << 10), 0x0);
+      write_mchbar32 (0x368 + (channel << 10), 0x32003200);
+      write_mchbar16 (0x352 + (channel << 10), 0x505);
+      write_mchbar16 (0x354 + (channel << 10), 0x3c3c);
+      write_mchbar16 (0x356 + (channel << 10), 0x1040);
+      write_mchbar16 (0x39a + (channel << 10), 0x73e4);
+      write_mchbar16 (0x3de + (channel << 10), 0x77ed);
+      write_mchbar16 (0x422 + (channel << 10), 0x1040);
+    }
+
+  write_1d0 (0x4, 0x151, 4, 1);
+  write_1d0 (0, 0x142, 3, 1);
+  my_read_msr (0x1ac); // !!!!
+  write_500 (&info, 1, 1, 0x6b3, 4, 1);
+  write_500 (&info, 1, 1, 0x6cf, 4, 1);
+
+  rmw_1d0 (0x21c, 0x38, 0, 6, 1);
+
+  write_1d0 (((!info.populated_ranks[1][0][0]) << 1) | ((!info.populated_ranks[0][0][0]) << 0), 0x1d1, 3, 1);
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_mchbar16 (0x38e + (channel << 10), 0x5f5f);
+      write_mchbar16 (0x3d2 + (channel << 10), 0x5f5f);
+    }
+
+  set_334 (0);
+
+  program_base_timings (&info);
+
+  write_mchbar8 (0x5ff, read_mchbar8 (0x5ff) | 0x80); /* OK */
+
+  write_1d0 (0x2, 0x1d5, 2, 1);
+  write_1d0 (0x20, 0x166, 7, 1);
+  write_1d0 (0x0, 0xeb, 3, 1);
+  write_1d0 (0x0, 0xf3, 6, 1);
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    for (lane = 0; lane < 9; lane++)
+      {
+	u16 addr = 0x125 + get_lane_offset (0, 0, lane);
+	u8 a;
+	a = read_500 (&info, channel, addr, 6); // = 0x20040080 //!!!!
+	write_500 (&info, channel, a, addr, 6, 1);
+      }
+
+  udelay (1000);
+
+  info.cached_training = get_cached_training();
+
+  if (s3resume)
+    {
+      if (info.cached_training == NULL)
+	{
+	  u32 reg32;
+	  printk (BIOS_ERR, "Couldn't find training data. Rebooting\n");
+	  reg32 = inl(DEFAULT_PMBASE + 0x04);
+	  outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+	  outb (0xe, 0xcf9);
+
+#if REAL
+	  while (1)
+	    {
+	      asm volatile ("hlt");
+	    }
+#else
+	  printf ("CP5\n");
+	  exit (0);
+#endif
+	}
+      int tm;
+      info.training =  *info.cached_training;
+      for (tm = 0; tm < 4; tm++)
+	for (channel = 0; channel < NUM_CHANNELS; channel++)
+	  for (slot = 0; slot < NUM_SLOTS; slot++)
+	    for (rank = 0; rank < NUM_RANKS; rank++)
+	      for (lane = 0; lane < 9; lane++)
+		write_500 (&info, channel, info.training.lane_timings[tm][channel][slot][rank][lane], get_timing_register_addr (lane, tm, slot, rank), 9, 0);
+      write_1d0 (info.cached_training->reg_178, 0x178, 7, 1);
+      write_1d0 (info.cached_training->reg_10b, 0x10b, 6, 1);
+    }
+
+  read_mchbar32 (0x1f4); // !!!!
+  write_mchbar32 (0x1f4, 0x20000);
+  write_mchbar32 (0x1f0, 0x1d000200);
+  read_mchbar8 (0x1f0); // !!!!
+  write_mchbar8 (0x1f0, 0x1);
+  read_mchbar8 (0x1f0); // !!!!
+
+  program_board_delay(&info);
+
+  write_mchbar8 (0x5ff, 0x0); /* OK */
+  write_mchbar8 (0x5ff, 0x80); /* OK */
+  write_mchbar8 (0x5f4, 0x1); /* OK */
+
+  write_mchbar32 (0x130, read_mchbar32 (0x130) & 0xfffffffd); // | 2 when ?
+  while (read_mchbar32 (0x130) & 1);
+  gav (read_1d0 (0x14b, 7)); // = 0x81023100
+  write_1d0 (0x30, 0x14b, 7, 1);
+  read_1d0 (0xd6, 6); // = 0xfa008080 // !!!!
+  write_1d0 (7, 0xd6, 6, 1);
+  read_1d0 (0x328, 6); // = 0xfa018080 // !!!!
+  write_1d0 (7, 0x328, 6, 1);
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    set_4cf (&info, channel, info.populated_ranks[channel][0][0] ? 8 : 0);
+
+  read_1d0 (0x116, 4); // = 0x4040432 // !!!!
+  write_1d0 (2, 0x116, 4, 1);
+  read_1d0 (0xae, 6); // = 0xe8088080 // !!!!
+  write_1d0 (0, 0xae, 6, 1);
+  read_1d0 (0x300, 4); // = 0x48088080 // !!!!
+  write_1d0 (0, 0x300, 6, 1);
+  read_mchbar16 (0x356); // !!!!
+  write_mchbar16 (0x356, 0x1040);
+  read_mchbar16 (0x756); // !!!!
+  write_mchbar16 (0x756, 0x1040);
+  write_mchbar32 (0x140, read_mchbar32 (0x140) & ~0x07000000);
+  write_mchbar32 (0x138, read_mchbar32 (0x138) & ~0x07000000);
+  write_mchbar32 (0x130, 0x31111301);
+  while (read_mchbar32 (0x130) & 1);
+
+  {
+    u32 t;
+    u8 val_a1;
+    val_a1 = read_1d0 (0xa1, 6); // = 0x1cf4040 // !!!!
+    t = read_1d0 (0x2f3, 6); // = 0x10a4040 // !!!!
+    rmw_1d0 (0x320, 0x07, (t & 4) | ((t & 8) >> 2) | ((t & 0x10) >> 4), 6, 1);
+    rmw_1d0 (0x14b, 0x78, ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & 4), 7, 1);
+    rmw_1d0 (0xce, 0x38, ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & 4), 6, 1);
+  }
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    set_4cf (&info, channel, info.populated_ranks[channel][0][0] ? 9 : 1);
+
+  rmw_1d0 (0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!!
+  read_mchbar32 (0x144); // !!!!
+  write_1d0 (2, 0xae, 6, 1);
+  write_1d0 (2, 0x300, 6, 1);
+  write_1d0 (2, 0x121, 3, 1);
+  read_1d0 (0xd6, 6); // = 0xfa00c0c7 // !!!!
+  write_1d0 (4, 0xd6, 6, 1);
+  read_1d0 (0x328, 6); // = 0xfa00c0c7 // !!!!
+  write_1d0 (4, 0x328, 6, 1);
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    set_4cf (&info, channel, info.populated_ranks[channel][0][0] ? 9 : 0);
+
+  write_mchbar32 (0x130, 0x11111301 | (info.populated_ranks[1][0][0] << 30) | (info.populated_ranks[0][0][0] << 29));
+  while (read_mchbar8 (0x130) & 1); // !!!!
+  read_1d0 (0xa1, 6); // = 0x1cf4054 // !!!!
+  read_1d0 (0x2f3, 6); // = 0x10a4054 // !!!!
+  read_1d0 (0x21c, 6); // = 0xafa00c0 // !!!!
+  write_1d0 (0, 0x21c, 6, 1);
+  read_1d0 (0x14b, 7); // = 0x810231b0 // !!!!
+  write_1d0 (0x35, 0x14b, 7, 1);
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    set_4cf (&info, channel, info.populated_ranks[channel][0][0] ? 0xb : 0x2);
+
+  set_334 (1);
+
+  write_mchbar8 (0x1e8, 0x4); /* OK */
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_500 (&info, channel, 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2, 1);
+      write_500 (&info, channel, 0x3, 0x69b, 2, 1);
+    }
+  write_mchbar32 (0x2d0, (read_mchbar32 (0x2d0) & 0xff2c01ff) | 0x200000); /* OK */
+  write_mchbar16 (0x6c0, 0x14a0); /* OK */
+  write_mchbar32 (0x6d0, (read_mchbar32 (0x6d0) & 0xff0080ff) | 0x8000); /* OK */
+  write_mchbar16 (0x232, 0x8);
+  write_mchbar32 (0x234, (read_mchbar32 (0x234) & 0xfffbfffb) | 0x40004); /* 0x40004 or 0 depending on ? */
+  write_mchbar32 (0x34, (read_mchbar32 (0x34) & 0xfffffffd) | 5); /* OK */
+  write_mchbar32 (0x128, 0x2150d05);
+  write_mchbar8 (0x12c, 0x1f); /* OK */
+  write_mchbar8 (0x12d, 0x56); /* OK */
+  write_mchbar8 (0x12e, 0x31);
+  write_mchbar8 (0x12f, 0x0); /* OK */
+  write_mchbar8 (0x271, 0x2); /* OK */
+  write_mchbar8 (0x671, 0x2); /* OK */
+  write_mchbar8 (0x1e8, 0x4); /* OK */
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    write_mchbar32 (0x294 + (channel << 10), (info.populated_ranks_mask[channel] & 3) << 16);
+  write_mchbar32 (0x134, (read_mchbar32 (0x134) & 0xfc01ffff) | 0x10000); /* OK */
+  write_mchbar32 (0x134, (read_mchbar32 (0x134) & 0xfc85ffff) | 0x850000); /* OK */
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    write_mchbar32 (0x260 + (channel << 10), (read_mchbar32 (0x260 + (channel << 10)) & ~0xf00000) | 0x8000000 |((info.populated_ranks_mask[channel] & 3) << 20));
+
+  if (!s3resume)
+    jedec_init (&info);
+
+  int totalrank = 0;
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    for (slot = 0; slot < NUM_SLOTS; slot++)
+      for (rank = 0; rank < NUM_RANKS; rank++)
+	if (info.populated_ranks[channel][slot][rank])
+	  {
+	    jedec_read (&info, channel, slot, rank, totalrank, 0xa, 0x400);
+	    totalrank++;
+	  }
+
+  write_mchbar8 (0x12c, 0x9f);
+
+  read_mchbar8 (0x271); // 2 // !!!!
+  write_mchbar8 (0x271, 0xe);
+  read_mchbar8 (0x671); // !!!!
+  write_mchbar8 (0x671, 0xe);
+
+  if (!s3resume)
+    {
+      for (channel = 0; channel < NUM_CHANNELS; channel++)
+	{
+	  write_mchbar32 (0x294 + (channel << 10), (info.populated_ranks_mask[channel] & 3) << 16);
+	  write_mchbar16 (0x298 + (channel << 10), (info.populated_ranks[channel][0][0]) | (info.populated_ranks[channel][0][1] << 5));
+	  write_mchbar32 (0x29c + (channel << 10), 0x77a);
+	}
+      read_mchbar32 (0x2c0); /// !!!
+      write_mchbar32 (0x2c0, 0x6009cc00);
+
+      {
+	u8 a, b;
+	a = read_mchbar8 (0x243); // !!!!
+	b = read_mchbar8 (0x643); // !!!!
+	write_mchbar8 (0x243, a | 2);
+	write_mchbar8 (0x643, b | 2);
+      }
+
+      write_1d0 (7, 0x19b, 3, 1);
+      write_1d0 (7, 0x1c0, 3, 1);
+      write_1d0 (4, 0x1c6, 4, 1);
+      write_1d0 (4, 0x1cc, 4, 1);
+      read_1d0 (0x151, 4); // = 0x408c6d74 // !!!!
+      write_1d0 (4, 0x151, 4 ,1);
+      write_mchbar32 (0x584, 0xfffff);
+      write_mchbar32 (0x984, 0xfffff);
+
+      for (channel = 0; channel < NUM_CHANNELS; channel++)
+	for (slot = 0; slot < NUM_SLOTS; slot++)
+	  for (rank = 0; rank < NUM_RANKS; rank++)
+	    if (info.populated_ranks[channel][slot][rank])
+	      config_rank (&info, s3resume, channel, slot, rank);
+
+      write_mchbar8 (0x243, 0x1);
+      write_mchbar8 (0x643, 0x1);
+    }
+
+  /* was == 1 but is common */
+  pci_mm_write16 (NORTHBRIDGE, 0xc8, 3);
+  write_26c (0, 0x820);
+  write_26c (1, 0x820);
+  write_mchbar32 (0x130, read_mchbar32 (0x130) | 2);
+  /* end */
+
+  if (s3resume)
+    {
+      for (channel = 0; channel < NUM_CHANNELS; channel++)
+	{
+	  write_mchbar32 (0x294 + (channel << 10), (info.populated_ranks_mask[channel] & 3) << 16);
+	  write_mchbar16 (0x298 + (channel << 10), (info.populated_ranks[channel][0][0]) | (info.populated_ranks[channel][0][1] << 5));
+	  write_mchbar32 (0x29c + (channel << 10), 0x77a);
+	}
+      read_mchbar32 (0x2c0); /// !!!
+      write_mchbar32 (0x2c0, 0x6009cc00);
+    }
+
+  write_mchbar32 (0xfa4, read_mchbar32 (0xfa4) & ~0x01000002);
+  write_mchbar32 (0xfb0, 0x2000e019);
+
+#if !REAL
+  printf ("CP16\n");
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+  before_training = rdtsc ();
+#endif
+
+  if (!s3resume)
+    ram_training (&info);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+  after_training = rdtsc ();
+#endif
+
+  dump_timings (&info);
+
+#if 0
+  ram_check (0x100000, 0x200000);
+#endif
+  program_modules_memory_map (&info, 0);
+  program_total_memory_map (&info);
+
+  if (info.non_interleaved_part_mb != 0 && info.interleaved_part_mb != 0)
+    write_mchbar8 (0x111, 0x20 | (0 << 2) | (1 << 6) | (0 << 7));
+  else if (have_match_ranks (&info, 0, 4) && have_match_ranks (&info, 1, 4))
+    write_mchbar8 (0x111, 0x20 | (3 << 2) | (0 << 6) | (1 << 7));
+  else if (have_match_ranks (&info, 0, 2) && have_match_ranks (&info, 1, 2))
+    write_mchbar8 (0x111, 0x20 | (3 << 2) | (0 << 6) | (0 << 7));
+  else
+    write_mchbar8 (0x111, 0x20 | (3 << 2) | (1 << 6) | (0 << 7));
+
+  write_mchbar32 (0xfac, read_mchbar32 (0xfac) & ~0x80000000); // OK
+  write_mchbar32 (0xfb4, 0x4800); // OK
+  write_mchbar32 (0xfb8, (info.revision < 8) ? 0x20 : 0x0); // OK
+  write_mchbar32 (0xe94, 0x7ffff); // OK
+  write_mchbar32 (0xfc0, 0x80002040); // OK
+  write_mchbar32 (0xfc4, 0x701246); // OK
+  write_mchbar8 (0xfc8, read_mchbar8 (0xfc8) & ~0x70); // OK
+  write_mchbar32 (0xe5c, 0x1000000 | read_mchbar32 (0xe5c)); // OK
+  write_mchbar32 (0x1a70, (read_mchbar32 (0x1a70) | 0x00200000) & ~0x00100000); // OK
+  write_mchbar32 (0x50, 0x700b0); // OK
+  write_mchbar32 (0x3c, 0x10); // OK
+  write_mchbar8 (0x1aa8, (read_mchbar8 (0x1aa8) & ~0x35) | 0xa); // OK
+  write_mchbar8 (0xff4, read_mchbar8 (0xff4) | 0x2); // OK
+  write_mchbar32 (0xff8, (read_mchbar32 (0xff8) & ~0xe008) | 0x1020); // OK
+
+#if REAL
+  write_mchbar32 (0xd00, IOMMU_BASE2 | 1);
+  write_mchbar32 (0xd40, IOMMU_BASE1 | 1);
+  write_mchbar32 (0xdc0, IOMMU_BASE4 | 1);
+
+  write32 (IOMMU_BASE1 | 0xffc, 0x80000000);
+  write32 (IOMMU_BASE2 | 0xffc, 0xc0000000);
+  write32 (IOMMU_BASE4 | 0xffc, 0x80000000);
+
+#else
+  {
+    u32 eax;      
+    eax = read32 (0xffc + (read_mchbar32 (0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
+    write32 (0xffc + (read_mchbar32 (0xd00) & ~1), eax);// OK
+    eax = read32 (0xffc + (read_mchbar32 (0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
+    write32 (0xffc + (read_mchbar32 (0xdc0) & ~1), eax);// OK
+  }
+#endif
+
+  {
+    u32 eax;      
+
+    eax = info.fsb_frequency / 9;
+    write_mchbar32 (0xfcc, (read_mchbar32 (0xfcc) & 0xfffc0000) | (eax * 0x280) | (eax * 0x5000) | eax | 0x40000);// OK
+    write_mchbar32 (0x20, 0x33001); //OK
+  }
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_mchbar32 (0x220 + (channel << 10),
+		      read_mchbar32 (0x220 + (channel << 10)) & ~0x7770); //OK
+      if (info.max_slots_used_in_channel == 1)
+	write_mchbar16 (0x237 + (channel << 10), (read_mchbar16 (0x237 + (channel << 10)) | 0x0201)); //OK
+      else
+	write_mchbar16 (0x237 + (channel << 10), (read_mchbar16 (0x237 + (channel << 10)) & ~0x0201)); //OK
+
+      write_mchbar8 (0x241 + (channel << 10), read_mchbar8 (0x241 + (channel << 10)) | 1); // OK
+
+      if (info.clock_speed_index <= 1 && (info.silicon_revision == 2 || info.silicon_revision == 3))
+	write_mchbar32 (0x248 + (channel << 10),
+			(read_mchbar32 (0x248 + (channel << 10)) | 0x00102000)); // OK
+      else
+	write_mchbar32 (0x248 + (channel << 10),
+			(read_mchbar32 (0x248 + (channel << 10)) & ~0x00102000)); // OK
+    }
+
+  write_mchbar32 (0x115, read_mchbar32 (0x115) | 0x1000000); // OK
+
+  {
+    u8 al;
+    al = 0xd;
+    if (!(info.silicon_revision == 0 || info.silicon_revision == 1))
+      al += 2;
+    al |= ((1 << (info.max_slots_used_in_channel - 1)) - 1) << 4;
+    write_mchbar32 (0x210, (al << 16) | 0x20); // OK
+  }
+
+  for (channel = 0; channel < NUM_CHANNELS; channel++)
+    {
+      write_mchbar32 (0x288 + (channel << 10), 0x70605040); // OK
+      write_mchbar32 (0x28c + (channel << 10), 0xfffec080); // OK
+      write_mchbar32 (0x290 + (channel << 10), 0x282091c | ((info.max_slots_used_in_channel - 1) << 0x16)); // OK
+    }
+  u32 reg1c;
+  pci_mm_read32 (NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+  reg1c = read32 (DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
+  pci_mm_read32 (NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
+  write32 (DEFAULT_EPBAR | 0x01c, reg1c); // OK
+  read_mchbar8 (0xe08); // = 0x0 
+  pci_mm_read32 (NORTHBRIDGE, 0xe4); // = 0x316126
+  write_mchbar8 (0x1210, read_mchbar8 (0x1210) | 2); // OK
+  write_mchbar32 (0x1200, 0x8800440); // OK
+  write_mchbar32 (0x1204, 0x53ff0453); // OK
+  write_mchbar32 (0x1208, 0x19002043); // OK
+  write_mchbar16 (0x1214, 0x320); // OK
+
+  if (info.revision == 0x10 || info.revision == 0x11)
+    {
+      write_mchbar16 (0x1214, 0x220); // OK
+      write_mchbar8 (0x1210, read_mchbar8 (0x1210) | 0x40); // OK
+    }
+
+  write_mchbar8 (0x1214, read_mchbar8 (0x1214) | 0x4); // OK
+  write_mchbar8 (0x120c, 0x1); // OK
+  write_mchbar8 (0x1218, 0x3); // OK
+  write_mchbar8 (0x121a, 0x3); // OK
+  write_mchbar8 (0x121c, 0x3); // OK
+  write_mchbar16 (0xc14, 0x0); // OK
+  write_mchbar16 (0xc20, 0x0); // OK
+  write_mchbar32 (0x1c, 0x0); // OK
+
+  /* revision dependent here.  */
+
+  write_mchbar16 (0x1230, read_mchbar16 (0x1230) | 0x1f07); // OK
+
+  if (info.uma_enabled)
+    write_mchbar32 (0x11f4, read_mchbar32 (0x11f4) | 0x10000000); // OK
+
+  write_mchbar16 (0x1230, read_mchbar16 (0x1230) | 0x8000); // OK
+  write_mchbar8 (0x1214, read_mchbar8 (0x1214) | 1); // OK
+
+  u8 bl, ebpb;
+  u16 reg_1020;
+
+  reg_1020 = read_mchbar32 (0x1020); // = 0x6c733c  // OK
+  write_mchbar8 (0x1070, 0x1); // OK
+
+  write_mchbar32 (0x1000, 0x100); // OK
+  write_mchbar8 (0x1007, 0x0); // OK
+
+  if (reg_1020 != 0)
+    {
+      write_mchbar16 (0x1018, 0x0); // OK
+      bl = reg_1020 >> 8;
+      ebpb = reg_1020 & 0xff;
+    }
+  else
+    {
+      ebpb = 0;
+      bl = 8;
+    }
+
+  my_read_msr (0x1a2);
+
+  write_mchbar32 (0x1014, 0xffffffff); // OK
+
+  write_mchbar32 (0x1010, ((((ebpb + 0x7d) << 7) / bl) & 0xff) * (!!reg_1020)); // OK
+
+  write_mchbar8 (0x101c, 0xb8); // OK
+
+  write_mchbar8 (0x123e, (read_mchbar8 (0x123e) & 0xf) | 0x60); // OK
+  if (reg_1020 != 0)
+    {
+      write_mchbar32 (0x123c, (read_mchbar32 (0x123c) & ~0x00900000) | 0x600000); // OK
+      write_mchbar8 (0x101c, 0xb8); // OK
+    }
+
+  setup_heci_uma (&info);
+
+  if (info.uma_enabled)
+    {
+      u16 ax;
+      write_mchbar32 (0x11b0, read_mchbar32 (0x11b0) | 0x4000); // OK
+      write_mchbar32 (0x11b4, read_mchbar32 (0x11b4) | 0x4000); // OK
+      write_mchbar16 (0x1190, read_mchbar16 (0x1190) | 0x4000); // OK
+
+      ax = read_mchbar16 (0x1190) & 0xf00; // = 0x480a  // OK
+      write_mchbar16 (0x1170, ax | (read_mchbar16 (0x1170) & 0x107f) | 0x4080); // OK
+      write_mchbar16 (0x1170, read_mchbar16 (0x1170) | 0x1000); // OK
+#if REAL
+      udelay (1000);
+#endif
+      u16 ecx;
+      for (ecx = 0xffff; ecx && (read_mchbar16 (0x1170) & 0x1000); ecx--);// OK
+      write_mchbar16 (0x1190, read_mchbar16 (0x1190) & ~0x4000);// OK
+    }
+
+  pci_mm_write8 (SOUTHBRIDGE, GEN_PMCON_2, pci_mm_read8 (SOUTHBRIDGE, GEN_PMCON_2) & ~0x80);
+  udelay (10000);
+  write_mchbar16 (0x2ca8, 0x0);
+
+#if REAL
+  udelay (1000);
+  dump_timings (&info);
+  if (!s3resume)
+    save_timings (&info);
+#endif
+}
+
+#if REAL
+unsigned long get_top_of_ram(void)
+{
+	/* Base of TSEG is top of usable DRAM */
+	u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+	return (unsigned long) tom;
+}
+
+struct cbmem_entry *get_cbmem_toc(void)
+{
+	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
+}
+#endif
+
+#if !REAL
+int
+main (void)
+{
+  raminit (0);
+  return 0;
+}
+#endif
diff --git a/src/northbridge/intel/calpella/raminit.h b/src/northbridge/intel/calpella/raminit.h
new file mode 100644
index 0000000..82fd20a
--- /dev/null
+++ b/src/northbridge/intel/calpella/raminit.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#include "calpella.h"
+
+void raminit(int s3resume);
+unsigned long get_top_of_ram(void);
+int fixup_sandybridge_errata(void);
+
+#endif				/* RAMINIT_H */
diff --git a/src/northbridge/intel/calpella/raminit_fake.c b/src/northbridge/intel/calpella/raminit_fake.c
new file mode 100644
index 0000000..6645610
--- /dev/null
+++ b/src/northbridge/intel/calpella/raminit_fake.c
@@ -0,0 +1,1413 @@
+static u32 gav_real (int line, u32 in)
+{
+  //  printf ("%d: GAV: %x\n", line, in);
+  return in;
+}
+
+#define gav(x) gav_real (__LINE__, (x))
+
+#include <parse.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+static void pm_wait (u16 us);
+
+#define ARRAY_SIZE(array) (sizeof (array) / sizeof (array[0]))
+
+#define CONFIG_SMM_TSEG_SIZE (8 << 20)
+
+#define MTRR_TYPE_WRPROT     5
+#define MTRRdefTypeEn		(1 << 11)
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+#define PCI_VENDOR_ID		0x00	/* 16 bits */
+#define PCI_COMMAND		0x04	/* 16 bits */
+#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
+#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
+#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
+#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
+#define PCI_REVISION_ID 8
+#define PCI_DEVICE_ID 2
+
+#define CONFIG_MMCONF_BASE_ADDRESS 0xe0000000
+
+
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+
+static void
+write32 (u32 addr, u32 val)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val || op.type != MEM)
+	{
+		printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write16 (u32 addr, u16 val)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val || op.type != MEM)
+	{
+	  printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write8 (u32 addr, u8 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val || op.type != MEM)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+
+static int
+smbus_read_byte (u32 dev, u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != SMBUS || op.dev != dev)
+	{
+		printf ("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr, SMBUS, addr, op.type);
+		exit (1);
+	}
+	return (signed short) op.val;
+}
+
+static int
+smbus_block_read (u32 dev, u32 addr, u32 len, u8 *block)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != len || op.addr != addr || op.type != OPCODE_SMBUS_BLOCK || op.dev != dev)
+	{
+		printf ("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr, OPCODE_SMBUS_BLOCK, addr, op.type);
+		exit (1);
+	}
+	memcpy (block, &op.val, len);
+	return 0;
+}
+
+static int
+smbus_block_write (u32 dev, u32 addr, u32 len, const u8 *block)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != len || op.addr != addr || op.type != OPCODE_SMBUS_BLOCK || op.dev != dev || memcmp (block, &op.val, len) != 0)
+	{
+		printf ("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr, OPCODE_SMBUS_BLOCK, addr, op.type);
+		exit (1);
+	}
+	return 0;
+}
+
+static void
+smbus_write_byte (u32 dev, u32 addr, u8 val)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != SMBUS || op.dev != dev || op.val != val)
+	{
+		printf ("Bad %d: %x, %d vs %x, %d\n", __LINE__, addr, SMBUS, op.addr, op.type);
+		exit (1);
+	}
+}
+
+static void
+write_mchbar32 (u32 addr, u32 val)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val || op.type != OPCODE_MCHBAR)
+	{
+		printf ("Bad [%x] = %x vs [%x] = %llx\n", addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write_acpi32 (u32 addr, u32 val)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val || op.type != ACPI)
+	{
+		printf ("Bad [%x] = %x vs [%x] = %llx\n", addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write_mchbar16 (u32 addr, u16 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val || op.type != OPCODE_MCHBAR)
+	{
+		printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write_acpi16 (u32 addr, u16 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val || op.type != ACPI)
+	{
+		printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write_tco16 (u32 addr, u16 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val || op.type != TCO)
+	{
+		printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write_tco8 (u32 addr, u8 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val || op.type != TCO)
+	{
+		printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+write_mchbar8 (u32 addr, u8 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val || op.type != OPCODE_MCHBAR)
+	{
+		printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static u32
+read_mchbar32 (u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 32 || op.addr != addr || op.type != OPCODE_MCHBAR)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u32
+read_mchbar32_bypass (u32 addr)
+{
+  return read_mchbar32 (addr);
+}
+
+static u32
+read_acpi32 (u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 32 || op.addr != addr || op.type != ACPI)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u16
+read_mchbar16 (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 16 || op.addr != addr || op.type != OPCODE_MCHBAR)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u16
+read_tco16 (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 16 || op.addr != addr || op.type != TCO)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u16
+read_acpi16 (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 16 || op.addr != addr || op.type != ACPI)
+	{
+	  printf ("Bad %d: %x, 16 vs %x, %d\n", __LINE__, addr, op.addr, op.data_width);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u8
+read_mchbar8 (u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != OPCODE_MCHBAR)
+	{
+		printf ("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u8
+read_tco8 (u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != TCO)
+	{
+		printf ("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u32
+read32 (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 32 || op.addr != addr || op.type != MEM)
+	{
+		printf ("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u64
+read64 (u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 64 || op.addr != addr || op.type != MEM)
+	{
+		printf ("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+		exit (1);
+	}
+	return op.val;
+}
+
+static void
+clflush (u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+
+	if (op.addr != addr || op.type != CLFLUSH)
+	{
+		printf ("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+		exit (1);
+	}
+}
+
+static void
+read128 (u32 addr, u64 *out)
+{
+  out[0] = read64 (addr);
+  out[1] = read64 (addr + 8);
+}
+
+static u16
+read16 (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 16 || op.addr != addr || op.type != MEM)
+	{
+		printf ("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u8
+read8 (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != MEM)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u8
+inb (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCIO)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static void
+outb (u8 val, u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCIO || op.val != val)
+	{
+	  printf ("Bad %d: %x, %x, 8, %d, 0 vs %x, %llx, %d, %d, %d\n", __LINE__, addr, val, PCIO, op.addr, op.val, op.data_width, op.type,
+		  op.is_in);
+	  printf ("%x, %llx, %d\n", val, op.val, op.val != val);
+		exit (1);
+	}
+}
+
+static void
+outw (u16 val, u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCIO || op.val != val)
+	{
+	  printf ("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, op.addr, op.val);
+		exit (1);
+	}
+}
+
+static void
+outl (u32 val, u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCIO || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static u32
+inl (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCIO)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u16
+inw (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCIO)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static void
+pci_mm_write8 (int bus, int dev, int func, u32 addr, u8 val)
+{
+	struct opcode op;
+	if (bus == 0xff)
+	  {
+	    write8 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr, val);
+	    return;
+	  }
+
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCIMM || op.dev != dev || op.func != func || op.bus != bus || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static void
+pci_write8 (int bus, int dev, int func, u32 addr, u8 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCI || op.dev != dev || op.func != func || op.bus != bus || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static void
+pci_write16 (int bus, int dev, int func, u32 addr, u16 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCI || op.dev != dev || op.func != func || op.bus != bus || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static void
+pci_mm_write16 (int bus, int dev, int func, u32 addr, u16 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCIMM || op.dev != dev || op.func != func || op.bus != bus || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static void
+pci_mm_write32 (int bus, int dev, int func, u32 addr, u32 val)
+{
+	struct opcode op;
+	if (bus == 0xff)
+	  {
+	    write32 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr, val);
+	    return;
+	  }
+
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+
+	if (op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCIMM || op.dev != dev || op.func != func || op.bus != bus || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static void
+pci_write32 (int bus, int dev, int func, u32 addr, u32 val)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCI || op.dev != dev || op.func != func || op.bus != bus || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static u8
+pci_read8 (int bus, int dev, int func, u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCI || op.dev != dev || op.func != func || op.bus != bus)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u8
+nvram_read (u8 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.addr != addr || op.type != NVRAM)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static void
+nvram_write (u8 addr, u8 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.addr != addr || op.type != NVRAM || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+}
+
+static u8
+pci_mm_read8 (int bus, int dev, int func, u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCIMM || op.dev != op.dev || op.func != op.func || op.bus != op.bus)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u16
+pci_mm_read16 (int bus, int dev, int func, u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCIMM || op.dev != dev || op.func != func || op.bus != bus)
+	{
+	  printf ("Bad %d: %x vs %x\n", __LINE__, addr, op.addr);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u16
+pci_read16 (int bus, int dev, int func, u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCI || op.dev != op.dev || op.func != op.func || op.bus != op.bus)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u32
+pci_mm_read32 (int bus, int dev, int func, u32 addr)
+{
+	struct opcode op;
+
+	if (bus == 0xff)
+	  return read32 (DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | (func << 12) | addr);
+
+	fetch_opcode (&op);
+	if (!op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCIMM || op.dev != op.dev || op.func != op.func || op.bus != op.bus)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u32
+pci_read32 (int bus, int dev, int func, u32 addr)
+{
+	struct opcode op;
+	if (!fetch_opcode (&op))
+	{
+		printf ("EOF\n");
+		exit (1);
+	}
+	if (!op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCI || op.dev != op.dev || op.func != op.func || op.bus != op.bus)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+struct cpuid_result
+{
+  u32 eax, ebx;
+};
+
+
+struct cpuid_result
+cpuid_ext(u32 eax, u32 ecx)
+{
+  struct cpuid_result ret;
+  struct opcode op;
+  if (!fetch_opcode (&op))
+    {
+      printf ("EOF\n");
+      exit (1);
+    }
+  if (op.addr != eax || op.type != CPUID || op.ecx != ecx)
+    {
+      printf ("Bad %d\n", __LINE__);
+      exit (1);
+    }
+  ret.eax = op.val;
+  ret.ebx = op.val >> 32;
+  return ret;
+}
+
+static u64
+my_read_msr (u32 addr)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (!op.is_in || op.addr != addr || op.type != MSR)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static u64
+my_write_msr (u32 addr, u64 val)
+{
+	struct opcode op;
+	fetch_opcode (&op);
+	if (op.is_in || op.addr != addr || op.type != MSR || op.val != val)
+	{
+		printf ("Bad %d\n", __LINE__);
+		exit (1);
+	}
+	return op.val;
+}
+
+static void
+die (const char *msg)
+{
+  printf ("%s\n", msg);
+  exit (1);
+}
+
+static void
+intel_early_me_init (void)
+{
+}
+
+static unsigned
+intel_early_me_uma_size (void)
+{
+  u32 t;
+  t = pci_mm_read32 (HECIDEV, 0x44);
+  if ( t & 0x10000 )
+    return t & 0x3F;
+  return 0;
+}
+
+static u8
+read_mchbar8_bypass (u32 addr)
+{
+  return read_mchbar8 (addr);
+}
+
+#define printk(condition, fmt, args...) printf(fmt, ## args)
+
+#define udelay(x)
+
+
+
+#if 1
+static const struct ram_training *
+get_cached_training (void)
+{
+  return NULL;
+#if 0
+  static const struct ram_training ret =
+    {
+#if 1
+      .lane_timings =
+      {
+	{
+	  {
+	    {
+	      { 5, 5, 3, 4, 4, 3, 4, 4, 21 },
+	      { 5, 4, 2, 5, 4, 3, 4, 4, 21 }
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	},
+	{
+	  {
+	    {
+	      { 0x6e, 0x64, 0x7b, 0x56, 0xbd, 0xa0, 0xae, 0xad, 0x100 },
+	      { 0x6e, 0x67, 0x7a, 0x54, 0xbd, 0x9f, 0xac, 0xac, 0x100 }
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	},
+	{
+	  {
+	    {
+	      { 0x59, 0x55, 0x6d, 0x44, 0xa3, 0x76, 0x90, 0x81, 0x80 },
+	      { 0x58, 0x51, 0x6b, 0x41, 0xa1, 0x75, 0x8e, 0x7f, 0x80 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	},
+	{
+	  {
+	    {
+	      { 0x78, 0x74, 0x8b, 0x64, 0xc1, 0x94, 0xaf, 0x9d, 0x80 },
+	      { 0x76, 0x6e, 0x88, 0x60, 0xbe, 0x93, 0xae, 0x9d, 0x80 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	}
+      },
+      .reg_178 = 0x42,
+      .reg_10b = 1,
+      .v775 = { 19, 35 },
+      .v777 = 
+      {
+	{
+	  {
+	    { 
+	      { 0x01, 0x25 },
+	      { 0x01, 0x25 },
+	      { 0x01, 0x21 },
+	      { 0x02, 0x22 },
+	      { 0x00, 0x23 },
+	      { 0x00, 0x21 },
+	      { 0x01, 0x22 },
+	      { 0x01, 0x22 },
+	      { 0x00, 0x00 }
+	    },
+	    { 
+	      { 0x01, 0x24 },
+	      { 0x02, 0x23 },
+	      { 0x01, 0x20 },
+	      { 0x01, 0x24 },
+	      { 0x00, 0x22 },
+	      { 0x01, 0x21 },
+	      { 0x01, 0x21 },
+	      { 0x02, 0x21 },
+	      { 0x00, 0x00 }
+	    },
+	    { 
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    }
+	  },
+	  {
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    }
+	  }
+	},
+	{
+	  {
+	    { 
+	      { 0x00, 0x25 },
+	      { 0x01, 0x24 },
+	      { 0x01, 0x20 },
+	      { 0x01, 0x22 },
+	      { 0x00, 0x22 },
+	      { 0x00, 0x21 },
+	      { 0x01, 0x23 },
+	      { 0x00, 0x22 },
+	      { 0x00, 0x00 }
+	    },
+	    { 
+	      { 0x00, 0x26 },
+	      { 0x01, 0x22 },
+	      { 0x01, 0x20 },
+	      { 0x01, 0x24 },
+	      { 0x00, 0x23 },
+	      { 0x00, 0x21 },
+	      { 0x01, 0x22 },
+	      { 0x01, 0x22 },
+	      { 0x00, 0x00 }
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    }
+	  },
+	  {
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    },
+	    {
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	      { 0x00, 0x00 },
+	    }
+	  }
+	}
+      },
+      .v1065 = 
+      {
+	{
+	  { 0x9c, 0x92, 0xab, 0x85, 0xec, 0xd0, 0xdd, 0xdc, 0x00 },
+	  { 0x9c, 0x96, 0xab, 0x82, 0xec, 0xcf, 0xdb, 0xdb, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+	}
+      },
+      .v1209 = {
+	{
+	  { 0x59, 0x55, 0x6d, 0x44, 0xa3, 0x76, 0x90, 0x81, 0x00 },
+	  { 0x58, 0x51, 0x6b, 0x41, 0xa1, 0x75, 0x8e, 0x7f, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	}
+      },
+      .v1353 = {
+	{
+	  {
+	    { 0x5d, 0x93 },
+	    { 0x59, 0x90 },
+	    { 0x70, 0xa6 },
+	    { 0x49, 0x7f },
+	    { 0xa5, 0xdd },
+	    { 0x79, 0xb0 },
+	    { 0x94, 0xca },
+	    { 0x83, 0xb8 },
+	    { 0x00, 0x00 },
+	  },
+	  {
+	    { 0x5c, 0x91 },
+	    { 0x53, 0x89 },
+	    { 0x6d, 0xa4 },
+	    { 0x45, 0x7c },
+	    { 0xa3, 0xd9 },
+	    { 0x77, 0xaf },
+	    { 0x94, 0xc9 },
+	    { 0x82, 0xb8 },
+	    { 0x00, 0x00 },
+	  },
+	  {
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	  },
+	  {
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	  }
+	},
+	{ 
+	  {
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	  },
+	  {
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	  },
+	  {
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	  },
+	  {
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	    { 0x00, 0x00 },
+	  }
+	}
+      },
+#else
+      .lane_timings =
+      {
+	{
+	  {
+	    {
+	      { 5, 5, 3, 5, 4, 4, 5, 3, 21 },
+	      { 6, 5, 4, 4, 4, 3, 4, 4, 21 }
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 3, 4, 5, 3, 2, 4, 4, 4, 21 },
+	      { 3, 3, 5, 4, 2, 5, 3, 4, 21 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	},
+	{
+	  {
+	    {
+	      { 0x6f, 0x66, 0x82, 0x58, 0xc5, 0xa6, 0xb4, 0xb1, 0x100 },
+	      { 0x70, 0x67, 0x84, 0x59, 0xc5, 0xa3, 0xb4, 0xb2, 0x100 }
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 0x91, 0x87, 0x98, 0x76, 0xdc, 0xb7, 0xcf, 0xc5, 0x100 },
+	      { 0x92, 0x8d, 0x9b, 0x76, 0xde, 0xb9, 0xce, 0xc6, 0x100 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	},
+	{
+	  {
+	    {
+	      { 0x5f, 0x5b, 0x74, 0x4a, 0xa9, 0x7c, 0x95, 0x85, 0x80 },
+	      { 0x5d, 0x59, 0x72, 0x49, 0xa8, 0x7a, 0x96, 0x85, 0x80 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 0x5b, 0x53, 0x6c, 0x49, 0xa8, 0x7a, 0x92, 0x84, 0x80 },
+	      { 0x5b, 0x51, 0x6c, 0x48, 0xa7, 0x79, 0x91, 0x82, 0x80 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	},
+	{
+	  {
+	    {
+	      { 0x7e, 0x7a, 0x92, 0x6a, 0xc7, 0x9b, 0xb6, 0xa4, 0x80 },
+	      { 0x7d, 0x77, 0x8f, 0x69, 0xc6, 0x98, 0xb6, 0xa4, 0x80 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	  {
+	    {
+	      { 0x78, 0x6f, 0x89, 0x65, 0xc4, 0x97, 0xaf, 0x9f, 0x80 },
+	      { 0x78, 0x6b, 0x89, 0x64, 0xc2, 0x96, 0xae, 0x9d, 0x80 },
+	    },
+	    {
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	      { 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	    }
+	  },
+	}
+      },
+      .reg_178 = 0,
+      .reg_10b = 1,
+#endif
+    };
+  return &ret;
+#endif
+}
+#endif
+
+static void
+pre_raminit_3 (int x2ca8)
+{
+  u8 t;
+  int i;
+
+  gav (t = nvram_read (0x33));
+  if (x2ca8 == 0)
+    {
+      nvram_write (0x33, t & ~0x40);
+      gav (read32 (DEFAULT_RCBA | 0x3598));
+      write32 (DEFAULT_RCBA | 0x3598, 0x1);
+      pci_write16 (0, 0x1d, 0x0, 0x20, 0x2000);
+      gav (pci_read8 (0, 0x1d, 0x0, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x0, 0x4, 0xff);
+      pci_write16 (0, 0x1d, 0x1, 0x20, 0x2020);
+      gav (pci_read8 (0, 0x1d, 0x1, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x1, 0x4, 0xff);
+      pci_write16 (0, 0x1d, 0x2, 0x20, 0x2040);
+      gav (pci_read8 (0, 0x1d, 0x2, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x2, 0x4, 0xff);
+      pci_write16 (0, 0x1d, 0x3, 0x20, 0x2060);
+      gav (pci_read8 (0, 0x1d, 0x3, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x3, 0x4, 0xff);
+      pci_write16 (0, 0x1a, 0x0, 0x20, 0x2080);
+      gav (pci_read8 (0, 0x1a, 0x0, 0x4)); // = 0xff
+      pci_write8 (0, 0x1a, 0x0, 0x4, 0xff);
+      pci_write16 (0, 0x1a, 0x1, 0x20, 0x20a0);
+      gav (pci_read8 (0, 0x1a, 0x1, 0x4)); // = 0xff
+      pci_write8 (0, 0x1a, 0x1, 0x4, 0xff);
+      pci_write16 (0, 0x1a, 0x2, 0x20, 0x20e0);
+      gav (pci_read8 (0, 0x1a, 0x2, 0x4)); // = 0xff
+      pci_write8 (0, 0x1a, 0x2, 0x4, 0xff);
+      for (i = 0; i < 15; i++)
+	{
+	  gav (inw (0x2010)); // = 0xff
+	  gav (inw (0x2012)); // = 0xff
+	  gav (inw (0x2030)); // = 0xff
+	  gav (inw (0x2032)); // = 0xff
+	  gav (inw (0x2050)); // = 0xff
+	  gav (inw (0x2052)); // = 0xff
+	  gav (inw (0x2070)); // = 0xff
+	  gav (inw (0x2072)); // = 0xff
+	  gav (inw (0x2090)); // = 0xff
+	  gav (inw (0x2092)); // = 0xff
+	  gav (inw (0x20b0)); // = 0xff
+	  gav (inw (0x20b2)); // = 0xff
+	  gav (inw (0x20f0)); // = 0xff
+	  gav (inw (0x20f2)); // = 0xff
+	  if (i != 14)
+	    pm_wait (0x400); /* <10*/ 
+	}
+      pci_write16 (0, 0x1d, 0x0, 0x20, 0x0);
+      gav (pci_read8 (0, 0x1d, 0x0, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x0, 0x4, 0xfe);
+      pci_write16 (0, 0x1d, 0x1, 0x20, 0x0);
+      gav (pci_read8 (0, 0x1d, 0x1, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x1, 0x4, 0xfe);
+      pci_write16 (0, 0x1d, 0x2, 0x20, 0x0);
+      gav (pci_read8 (0, 0x1d, 0x2, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x2, 0x4, 0xfe);
+      pci_write16 (0, 0x1d, 0x3, 0x20, 0x0);
+      gav (pci_read8 (0, 0x1d, 0x3, 0x4)); // = 0xff
+      pci_write8 (0, 0x1d, 0x3, 0x4, 0xfe);
+      pci_write16 (0, 0x1a, 0x0, 0x20, 0x0);
+      gav (pci_read8 (0, 0x1a, 0x0, 0x4)); // = 0xff
+      pci_write8 (0, 0x1a, 0x0, 0x4, 0xfe);
+      pci_write16 (0, 0x1a, 0x1, 0x20, 0x0);
+      gav (pci_read8 (0, 0x1a, 0x1, 0x4)); // = 0xff
+      pci_write8 (0, 0x1a, 0x1, 0x4, 0xfe);
+      pci_write16 (0, 0x1a, 0x2, 0x20, 0x0);
+      gav (pci_read8 (0, 0x1a, 0x2, 0x4)); // = 0xff
+      pci_write8 (0, 0x1a, 0x2, 0x4, 0xfe);
+      write32 (DEFAULT_RCBA | 0x3598, 0x0);
+    }
+}
+
+
diff --git a/src/northbridge/intel/calpella/raminit_tables.c b/src/northbridge/intel/calpella/raminit_tables.c
new file mode 100644
index 0000000..3404ffc
--- /dev/null
+++ b/src/northbridge/intel/calpella/raminit_tables.c
@@ -0,0 +1,1240 @@
+/* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */
+const u8 u8_FFFD1240[2][5][9][4][4] = {
+  {
+    {
+      {
+	{ 0x3b, 0x53, 0x57, 0x5c },
+	{ 0x3b, 0x52, 0x57, 0x5c },
+	{ 0x3b, 0x4d, 0x51, 0x54 },
+	{ 0x3b, 0x4d, 0x51, 0x54 }
+      },
+      {
+	{ 0x46, 0x63, 0x6b, 0x74 },
+	{ 0x46, 0x62, 0x6b, 0x73 },
+	{ 0x46, 0x5d, 0x65, 0x6c },
+	{ 0x46, 0x5d, 0x65, 0x6c }
+      },
+      {
+	{ 0x51, 0x71, 0x7e, 0x8a },
+	{ 0x51, 0x71, 0x7d, 0x8a },
+	{ 0x51, 0x6c, 0x77, 0x82 },
+	{ 0x51, 0x6c, 0x77, 0x82 }
+      },
+      {
+	{ 0x5c, 0x7b, 0x8a, 0x99 },
+	{ 0x5c, 0x7b, 0x89, 0x98 },
+	{ 0x5c, 0x75, 0x83, 0x90 }, 
+	{ 0x5c, 0x75, 0x83, 0x90 }
+      },
+      {
+	{ 0x65, 0x81, 0x91, 0xa2 },
+	{ 0x65, 0x81, 0x91, 0xa1 },
+	{ 0x65, 0x7c, 0x8b, 0x9a }, 
+	{ 0x65, 0x7c, 0x8b, 0x9a }
+      },
+      {
+	{ 0x70, 0x8b, 0x9e, 0xb1 },
+	{ 0x70, 0x8b, 0x9d, 0xb0 },
+	{ 0x70, 0x86, 0x97, 0xa9 },
+	{ 0x70, 0x86, 0x97, 0xa9 }
+      },
+      {
+	{ 0x73, 0x8f, 0xa3, 0xb7 },
+	{ 0x73, 0x8f, 0xa3, 0xb6 },
+	{ 0x73, 0x8a, 0x9d, 0xaf },
+	{ 0x73, 0x8a, 0x9d, 0xaf },
+      },
+      {
+	{ 0x78, 0x99, 0xaf, 0xc5 },
+	{ 0x78, 0x98, 0xae, 0xc4 }, 
+	{ 0x78, 0x93, 0xa8, 0xbd },
+	{ 0x78, 0x93, 0xa8, 0xbd },
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 }
+      },
+    },
+    {
+      {
+	{ 0x3b, 0x53, 0x57, 0x5c },
+	{ 0x3b, 0x52, 0x57, 0x5c },
+	{ 0x3b, 0x4d, 0x51, 0x54 },
+	{ 0x3b, 0x4d, 0x51, 0x54 }
+      },
+      {
+	{ 0x46, 0x63, 0x6b, 0x74 },
+	{ 0x46, 0x62, 0x6b, 0x73 },
+	{ 0x46, 0x5d, 0x65, 0x6c },
+	{ 0x46, 0x5d, 0x65, 0x6c }
+      },
+      {
+	{ 0x51, 0x71, 0x7e, 0x8a }, 
+	{ 0x51, 0x71, 0x7d, 0x8a },
+	{ 0x51, 0x6c, 0x77, 0x82 },
+	{ 0x51, 0x6c, 0x77, 0x82 }
+      },
+      {
+	{ 0x5c, 0x7b, 0x8a, 0x99 },
+	{ 0x5c, 0x7b, 0x89, 0x98 },
+	{ 0x5c, 0x75, 0x83, 0x90 },
+	{ 0x5c, 0x75, 0x83, 0x90 }
+      },
+      {
+	{ 0x65, 0x81, 0x91, 0xa2 },
+	{ 0x65, 0x81, 0x91, 0xa1 },
+	{ 0x65, 0x7c, 0x8b, 0x9a },
+	{ 0x65, 0x7c, 0x8b, 0x9a }
+      },
+      {
+	{ 0x70, 0x8b, 0x9e, 0xb1 },
+	{ 0x70, 0x8b, 0x9d, 0xb0 },
+	{ 0x70, 0x86, 0x97, 0xa9 },
+	{ 0x70, 0x86, 0x97, 0xa9 }
+      },
+      {
+	{ 0x73, 0x8f, 0xa3, 0xb7 },
+	{ 0x73, 0x8f, 0xa3, 0xb6 },
+	{ 0x73, 0x8a, 0x9d, 0xaf },
+	{ 0x73, 0x8a, 0x9d, 0xaf }
+      },
+      {
+	{ 0x78, 0x99, 0xaf, 0xc5 },
+	{ 0x78, 0x98, 0xae, 0xc4 },
+	{ 0x78, 0x93, 0xa8, 0xbd },
+	{ 0x78, 0x93, 0xa8, 0xbd }
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 }
+      },
+    },
+    {
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e }
+      },
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e }
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d }
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d }
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 }
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 }
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 }
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 }
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 }
+      },
+    },
+    {
+      {
+	{ 0x55, 0x5b, 0x62, 0x61 },
+	{ 0x55, 0x5b, 0x62, 0x61 },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e }
+      },
+      {
+	{ 0x55, 0x5b, 0x62, 0x61 },
+	{ 0x55, 0x5b, 0x62, 0x61 },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e }
+      },
+      {
+	{ 0x5d, 0x67, 0x71, 0x73 },
+	{ 0x5d, 0x67, 0x71, 0x73 },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d }
+      },
+      {
+	{ 0x5d, 0x67, 0x71, 0x73 },
+	{ 0x5d, 0x67, 0x71, 0x73 },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d }
+      },
+      {
+	{ 0x6b, 0x7a, 0x88, 0x8f },
+	{ 0x6b, 0x7a, 0x88, 0x8f },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 }
+      },
+      {
+	{ 0x6b, 0x7a, 0x88, 0x8f },
+	{ 0x6b, 0x7a, 0x88, 0x8f },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 }
+      },
+      {
+	{ 0x75, 0x87, 0x98, 0xa2 },
+	{ 0x75, 0x87, 0x98, 0xa2 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 }
+      },
+      {
+	{ 0x75, 0x87, 0x98, 0xa2 },
+	{ 0x75, 0x87, 0x98, 0xa2 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 }
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 }
+      },
+    },
+    {
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e }
+      },
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e }
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d }
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d }
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 }
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 }
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 }
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 }
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 }
+      },
+    },
+  },
+  {
+    {
+      {
+	{ 0x41, 0x59, 0x5f, 0x65 },
+	{ 0x41, 0x59, 0x5f, 0x65 },
+	{ 0x41, 0x53, 0x58, 0x5d },
+	{ 0x41, 0x53, 0x58, 0x5d }
+      },
+      {
+	{ 0x4b, 0x69, 0x73, 0x7d },
+	{ 0x4b, 0x69, 0x73, 0x7d },
+	{ 0x4b, 0x63, 0x6c, 0x75 },
+	{ 0x4b, 0x63, 0x6c, 0x75 },
+      },
+      {
+	{ 0x54, 0x72, 0x7f, 0x8b },
+	{ 0x54, 0x72, 0x7f, 0x8b },
+	{ 0x54, 0x6c, 0x78, 0x83 },
+	{ 0x54, 0x6c, 0x78, 0x83 },
+      },
+      {
+	{ 0x61, 0x81, 0x91, 0xa2 },
+	{ 0x61, 0x81, 0x91, 0xa2 },
+	{ 0x61, 0x7b, 0x8a, 0x99 },
+	{ 0x61, 0x7b, 0x8a, 0x99 },
+      },
+      {
+	{ 0x6a, 0x87, 0x99, 0xab },
+	{ 0x6a, 0x87, 0x99, 0xab },
+	{ 0x6a, 0x82, 0x92, 0xa3 },
+	{ 0x6a, 0x82, 0x92, 0xa3 },
+      },
+      {
+	{ 0x71, 0x8b, 0x9e, 0xb1 },
+	{ 0x71, 0x8b, 0x9e, 0xb1 },
+	{ 0x71, 0x86, 0x98, 0xa9 },
+	{ 0x71, 0x86, 0x98, 0xa9 },
+      },
+      {
+	{ 0x75, 0x95, 0xab, 0xc0 },
+	{ 0x75, 0x95, 0xab, 0xc0 },
+	{ 0x75, 0x90, 0xa4, 0xb8 },
+	{ 0x75, 0x90, 0xa4, 0xb8 },
+      },
+      {
+	{ 0x7d, 0x9f, 0xb6, 0xce },
+	{ 0x7d, 0x9f, 0xb6, 0xce },
+	{ 0x7d, 0x99, 0xb0, 0xc6 },
+	{ 0x7d, 0x99, 0xb0, 0xc6 },
+      },
+      {
+	{ 0x61, 0x7e, 0x80, 0x9f },
+	{ 0x61, 0x7e, 0x95, 0x9f },
+	{ 0x61, 0x7e, 0x80, 0x9f },
+	{ 0x61, 0x7e, 0x80, 0x9f },
+      },
+    },
+    {
+      {
+	{ 0x41, 0x59, 0x5f, 0x65 },
+	{ 0x41, 0x59, 0x5f, 0x65 },
+	{ 0x41, 0x53, 0x58, 0x5d },
+	{ 0x41, 0x53, 0x58, 0x5d },
+      },
+      {
+	{ 0x4b, 0x69, 0x73, 0x7d },
+	{ 0x4b, 0x69, 0x73, 0x7d },
+	{ 0x4b, 0x63, 0x6c, 0x75 },
+	{ 0x4b, 0x63, 0x6c, 0x75 },
+      },
+      {
+	{ 0x54, 0x72, 0x7f, 0x8b },
+	{ 0x54, 0x72, 0x7f, 0x8b },
+	{ 0x54, 0x6c, 0x78, 0x83 },
+	{ 0x54, 0x6c, 0x78, 0x83 },
+      },
+      {
+	{ 0x61, 0x81, 0x91, 0xa2 },
+	{ 0x61, 0x81, 0x91, 0xa2 },
+	{ 0x61, 0x7b, 0x8a, 0x99 },
+	{ 0x61, 0x7b, 0x8a, 0x99 },
+      },
+      {
+	{ 0x6a, 0x87, 0x99, 0xab },
+	{ 0x6a, 0x87, 0x99, 0xab },
+	{ 0x6a, 0x82, 0x92, 0xa3 },
+	{ 0x6a, 0x82, 0x92, 0xa3 },
+      },
+      {
+	{ 0x71, 0x8b, 0x9e, 0xb1 },
+	{ 0x71, 0x8b, 0x9e, 0xb1 },
+	{ 0x71, 0x86, 0x98, 0xa9 },
+	{ 0x71, 0x86, 0x98, 0xa9 },
+      },
+      {
+	{ 0x75, 0x95, 0xab, 0xc0 },
+	{ 0x75, 0x95, 0xab, 0xc0 },
+	{ 0x75, 0x90, 0xa4, 0xb8 },
+	{ 0x75, 0x90, 0xa4, 0xb8 },
+      },
+      {
+	{ 0x7d, 0x9f, 0xb6, 0xce },
+	{ 0x7d, 0x9f, 0xb6, 0xce },
+	{ 0x7d, 0x99, 0xb0, 0xc6 },
+	{ 0x7d, 0x99, 0xb0, 0xc6 },
+      },
+      {
+	{ 0x61, 0x7e, 0x80, 0x9f },
+	{ 0x61, 0x7e, 0x80, 0x9f },
+	{ 0x61, 0x7e, 0x80, 0x9f },
+	{ 0x61, 0x7e, 0x80, 0x9f },
+      },
+    },
+    {
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+      },
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+      },
+    },
+    {
+      {
+	{ 0x56, 0x5d, 0x65, 0x64 },
+	{ 0x56, 0x5d, 0x65, 0x64 },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+      },
+      {
+	{ 0x56, 0x5d, 0x65, 0x64 },
+	{ 0x56, 0x5d, 0x65, 0x64 },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+      },
+      {
+	{ 0x5e, 0x68, 0x72, 0x74 },
+	{ 0x5e, 0x68, 0x72, 0x74 },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+      },
+      {
+	{ 0x5e, 0x68, 0x72, 0x74 },
+	{ 0x5e, 0x68, 0x72, 0x74 },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+      },
+      {
+	{ 0x68, 0x76, 0x83, 0x89 },
+	{ 0x68, 0x76, 0x83, 0x89 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+      },
+      {
+	{ 0x68, 0x76, 0x83, 0x89 },
+	{ 0x68, 0x76, 0x83, 0x89 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+      },
+      {
+	{ 0x70, 0x80, 0x90, 0x98 },
+	{ 0x70, 0x80, 0x90, 0x98 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+      },
+      {
+	{ 0x70, 0x80, 0x90, 0x98 },
+	{ 0x70, 0x80, 0x90, 0x98 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+      },
+    },
+    {
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+      },
+      {
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+	{ 0x57, 0x5e, 0x66, 0x6e },
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+      },
+      {
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+	{ 0x5e, 0x69, 0x73, 0x7d },
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+      },
+      {
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+	{ 0x69, 0x77, 0x85, 0x92 },
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+      },
+      {
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+	{ 0x70, 0x80, 0x91, 0xa1 },
+      },
+      {
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+	{ 0x5c, 0x79, 0x87, 0x94 },
+      }
+    }
+  }
+};
+
+const u16 u16_FFFE0EB8[2][4] = {
+  { 0x0000, 0x0000, 0x0000, 0x0000 },
+  { 0x0000, 0x0000, 0x0000, 0x0000 }
+};
+
+/* [CARD][LANE][CLOCK_SPEED] */
+const u16 u16_ffd1188[2][9][4] = {
+  {
+    { 0xfff9, 0xfff7, 0xfff5, 0xfff2 },
+    { 0xfff9, 0xfff7, 0xfff5, 0xfff2 },
+    { 0xfffb, 0xfff9, 0xfff7, 0xfff6 }, 
+    { 0xfffb, 0xfff9, 0xfff7, 0xfff6 },
+    { 0xfffc, 0xfffb, 0xfffa, 0xfff8 },
+    { 0xfffc, 0xfffb, 0xfffa, 0xfff8 },
+    { 0xfffd, 0xfffc, 0xfffb, 0xfffa },
+    { 0xfffd, 0xfffc, 0xfffb, 0xfffa },
+    { 0x0000, 0x0000, 0x0000, 0x0000 }
+  }, 
+  {
+    { 0x0001, 0x0001, 0x0001, 0x0002 },
+    { 0xfffa, 0xfff8, 0xfff6, 0xfff4 },
+    { 0x0001, 0x0002, 0x0002, 0x0003 },
+    { 0xffe2, 0xffd8, 0xffce, 0xffc4 }, 
+    { 0x0021, 0x002d, 0x0038, 0x0043 },
+    { 0x0004, 0x0005, 0x0006, 0x0007 },
+    { 0x000e, 0x0013, 0x0018, 0x001d },
+    { 0x0009, 0x000c, 0x000f, 0x0012 },
+    { 0x0000, 0x0000, 0x0000, 0x0000 }
+  }
+};
+
+/* [REVISION][CHANNEL][CLOCK_INDEX][?] */
+const u8 u8_FFFD1891[2][2][4][12] = {
+  {
+    {
+      { 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00 },
+    },
+    {
+      { 0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00 },
+    }
+  },
+  {
+    {
+      { 0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00 },
+    },
+    {
+      { 0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00 },
+      { 0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74 }
+    }
+  }
+};
+
+const u8 u8_FFFD17E0[2][5][4][4] = {
+  {
+    {
+      { 0x00, 0x0c, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x23, 0x19, 0x0f, 0x05 },
+      { 0x23, 0x19, 0x0f, 0x05 },
+    },
+    {
+      { 0x00, 0x0c, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x23, 0x19, 0x0f, 0x05 },
+      { 0x23, 0x19, 0x0f, 0x05 },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x44, 0x45, 0x47, 0x05 },
+      { 0x44, 0x45, 0x47, 0x05 },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x44, 0x45, 0x46, 0x44 },
+      { 0x44, 0x45, 0x46, 0x44 },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x2a, 0x24, 0x1e, 0x16 },
+      { 0x2a, 0x24, 0x1e, 0x16 },
+    },
+  },
+  {
+    {
+      { 0x00, 0x08, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x27, 0x1e, 0x16, 0x0d },
+      { 0x27, 0x1e, 0x16, 0x0d },
+    },
+    {
+      { 0x00, 0x08, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x27, 0x1e, 0x16, 0x0d },
+      { 0x27, 0x1e, 0x16, 0x0d },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x44, 0x45, 0x47, 0x05 },
+      { 0x44, 0x45, 0x47, 0x05 },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x43, 0x44, 0x45, 0x43 },
+      { 0x43, 0x44, 0x45, 0x43 },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x00, 0x00, 0x00, 0x00 },
+      { 0x2a, 0x24, 0x1e, 0x16 },
+      { 0x2a, 0x24, 0x1e, 0x16 },
+    },
+  },
+};
+
+const u8 u8_FFFD0C78[2][5][4][2][2][4] = {
+  {
+    {
+      {
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	},
+	{
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	},
+	{
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	  { 0x00, 0x02, 0x0d, 0x0f },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x06, 0x08, 0x0a },
+	  { 0x04, 0x06, 0x08, 0x0a },
+	},
+	{
+	  { 0x04, 0x06, 0x08, 0x0a },
+	  { 0x04, 0x06, 0x08, 0x0a },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+    },
+  },
+  {
+    {
+      {
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x06, 0x0d, 0x0f },
+	  { 0x00, 0x06, 0x0d, 0x0f },
+	},
+	{
+	  { 0x00, 0x06, 0x0d, 0x0f },
+	  { 0x00, 0x06, 0x0d, 0x0f },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x06, 0x13, 0x17 },
+	  { 0x00, 0x06, 0x13, 0x17 },
+	},
+	{
+	  { 0x00, 0x06, 0x13, 0x17 },
+	  { 0x00, 0x06, 0x13, 0x17 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+	{
+	  { 0x04, 0x05, 0x07, 0x08 },
+	  { 0x04, 0x05, 0x07, 0x08 },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+      {
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+	{
+	  { 0x06, 0x07, 0x09, 0x0b },
+	  { 0x06, 0x07, 0x09, 0x0b },
+	},
+      },
+    },
+    {
+      {
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+	{
+	  { 0x00, 0x00, 0x03, 0x04 },
+	  { 0x00, 0x00, 0x03, 0x04 },
+	},
+      },
+      {
+	{
+	  { 0x04, 0x06, 0x08, 0x0a },
+	  { 0x00, 0x06, 0x0d, 0x0f },
+	},
+	{
+	  { 0x00, 0x06, 0x0d, 0x0f },
+	  { 0x00, 0x06, 0x0d, 0x0f },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+      {
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+	{
+	  { 0x00, 0x00, 0x00, 0x00 },
+	  { 0x00, 0x00, 0x00, 0x00 },
+	},
+      },
+    },
+  },
+};
+
+const u16 u16_fffd0c68[3] = { 0x04c3, 0x064d, 0x068b };
+
+const u16 u16_fffd0c70[2][2] = { 
+  { 0x06c0, 0x06c9 },
+  { 0x06a4, 0x06ad }
+};
+
+const u16 u16_fffd0c50[3][2][2] = {
+  {
+    { 0x04b9, 0x04af },
+    { 0x04a5, 0x049b }
+  },
+  {
+    { 0x0625, 0x062f },
+    { 0x0639, 0x0643 },
+  },
+  {
+    { 0x0663, 0x066d },
+    { 0x0677, 0x0681 }
+  }
+};
+
+/* [CLOCK_INDEX] */
+const u16 min_cycletime[4] = { 0x09c4, 0x0753, 0x05dc, 0x0000 };
+/* [CLOCK_INDEX] */
+const u16 min_cas_latency_time[4] = { 0x30d4, 0x2bf2, 0x2904, 0x0000 };
+
+/* [CHANNEL][EXT_SILICON_REVISION][?][CLOCK_INDEX] */
+/* On other mobos may also depend on slot and rank.  */
+const u8 u8_FFFD0EF8[2][5][4][4] = {
+  {
+    {
+      { 0x00, 0x00, 0x03, 0x04, },
+      { 0x00, 0x02, 0x0d, 0x0f, },
+      { 0x00, 0x00, 0x00, 0x00, },
+      { 0x00, 0x00, 0x00, 0x00, },
+    },
+    {
+      { 0x00, 0x00, 0x03, 0x04, },
+      { 0x00, 0x02, 0x0d, 0x0f, },
+      { 0x00, 0x00, 0x00, 0x00, },
+      { 0x00, 0x00, 0x00, 0x00, },
+    },
+    {
+      { 0x09, 0x0c, 0x0f, 0x12, },
+      { 0x09, 0x0c, 0x0f, 0x12, },
+      { 0x09, 0x0c, 0x0f, 0x12, },
+      { 0x09, 0x0c, 0x0f, 0x12, },
+    },
+    {
+      { 0x06, 0x08, 0x0a, 0x0c, },
+      { 0x06, 0x08, 0x0a, 0x0c, },
+      { 0x06, 0x08, 0x0a, 0x0c, },
+      { 0x06, 0x08, 0x0a, 0x0c, },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00, },
+      { 0x07, 0x0a, 0x0d, 0x10, },
+      { 0x04, 0x06, 0x08, 0x0a, },
+      { 0x04, 0x06, 0x08, 0x0a, },
+    },
+  },
+  {
+    {
+      { 0x00, 0x00, 0x03, 0x04, },
+      { 0x00, 0x06, 0x0d, 0x0f, },
+      { 0x00, 0x00, 0x00, 0x00, },
+      { 0x00, 0x00, 0x00, 0x00, },
+    },
+    {
+      { 0x00, 0x00, 0x03, 0x04, },
+      { 0x00, 0x06, 0x13, 0x17, },
+      { 0x00, 0x00, 0x00, 0x00, },
+      { 0x00, 0x00, 0x00, 0x00, },
+    },
+    {
+      { 0x09, 0x0c, 0x0f, 0x12, },
+      { 0x09, 0x0c, 0x0f, 0x12, },
+      { 0x09, 0x0c, 0x0f, 0x12, },
+      { 0x09, 0x0c, 0x0f, 0x12, },
+    },
+    {
+      { 0x09, 0x0c, 0x10, 0x13, },
+      { 0x09, 0x0c, 0x10, 0x13, },
+      { 0x09, 0x0c, 0x10, 0x13, },
+      { 0x09, 0x0c, 0x10, 0x13, },
+    },
+    {
+      { 0x00, 0x00, 0x00, 0x00, },
+      { 0x07, 0x0a, 0x0d, 0x10, },
+      { 0x04, 0x06, 0x08, 0x0a, },
+      { 0x04, 0x06, 0x08, 0x0a, },
+    },
+  },
+};
+
+/* [CLOCK_SPEED] */
+const u8 u8_FFFD1218[4] = {
+  0x15, 0x15, 0x15, 0x12
+};
+
+const u8 reg178_min[] = { 1, 3, 4, 7 };
+const u8 reg178_max[] = { 62, 60, 59, 56 };
+const u8 reg178_step[] = { 5, 4, 3, 2 };
+
+const u16 u16_ffd1178[2][4] = {
+  { 0xfffb, 0xfffa, 0xfff8, 0xfff7 },
+  { 0xfffb, 0xfffa, 0xfff8, 0xfff7 },
+};
+const u16 u16_fe0eb8[2][4] = {
+  { 0x0000, 0x0000, 0x0000, 0x0000 },
+  { 0x0000, 0x0000, 0x0000, 0x0000 }
+};
+
+const u8 lut16[4] = { 14, 13, 14, 14};
diff --git a/src/northbridge/intel/calpella/udelay.c b/src/northbridge/intel/calpella/udelay.c
new file mode 100644
index 0000000..449b0b9
--- /dev/null
+++ b/src/northbridge/intel/calpella/udelay.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 100, divisor;
+	u32 d;			/* ticks per us */
+
+	msr = rdmsr(0xce);
+	divisor = (msr.lo >> 8) & 0xff;
+
+	d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+	multiply_to_tsc(&tscd, us, d);
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi)
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+}
diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig
index 5637c4a..c428b70 100644
--- a/src/southbridge/intel/Kconfig
+++ b/src/southbridge/intel/Kconfig
@@ -12,4 +12,5 @@ source src/southbridge/intel/i82870/Kconfig
 source src/southbridge/intel/pxhd/Kconfig
 source src/southbridge/intel/sch/Kconfig
 source src/southbridge/intel/bd82x6x/Kconfig
+source src/southbridge/intel/calpella/Kconfig
 source src/southbridge/intel/lynxpoint/Kconfig
diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc
index ba3b1d4..f8b9153 100644
--- a/src/southbridge/intel/Makefile.inc
+++ b/src/southbridge/intel/Makefile.inc
@@ -13,4 +13,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd
 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch
 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x
 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_CALPELLA) += calpella
 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) += lynxpoint
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 5dd492c..1ba6861 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -23,7 +23,10 @@ config SOUTHBRIDGE_INTEL_BD82X6X
 config SOUTHBRIDGE_INTEL_C216
 	bool
 
-if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
+config SOUTHBRIDGE_INTEL_CALPELLA
+	bool
+
+if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_CALPELLA
 
 config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index bc3ff4b..b2a5b72 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -28,6 +28,7 @@ ramstage-y += lpc.c
 ramstage-y += pci.c
 ramstage-y += pcie.c
 ramstage-y += sata.c
+ramstage-y += sata.c
 ramstage-y += usb_ehci.c
 ramstage-y += usb_xhci.c
 ramstage-y += me.c
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 2d854a4..17141d6 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -362,7 +362,7 @@ static struct device_operations azalia_ops = {
 	.ops_pci		= &azalia_pci_ops,
 };
 
-static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 };
+static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0x3b56, 0 };
 
 static const struct pci_driver pch_azalia __pci_driver = {
 	.ops	 = &azalia_ops,
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 9de97e7..d8aff92 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -60,3 +60,18 @@ int smbus_read_byte(unsigned device, unsigned address)
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
+int smbus_write_byte(unsigned device, unsigned address, u8 data)
+{
+  return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
+}
+
+int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf)
+{
+	return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}
+
+int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
+{
+	return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
+}
+
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index bcc2f3d..79d15ec 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -20,7 +20,12 @@
 
 #include <arch/io.h>
 #include <console/post_codes.h>
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
 #include <northbridge/intel/sandybridge/pcie_config.c>
+#endif
+#if CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#include <northbridge/intel/calpella/pcie_config.c>
+#endif
 #include "pch.h"
 #include <spi-generic.h>
 
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index e052150..01055b6 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -51,8 +51,11 @@ static void pch_enable_ioapic(struct device *dev)
 	/* Enable ACPI I/O range decode */
 	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
 
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
 	set_ioapic_id(IO_APIC_ADDR, 0x02);
-
+#else
+	set_ioapic_id(IO_APIC_ADDR, 0x01);
+#endif
 	/* affirm full set of redirection table entries ("write once") */
 	reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
 	io_apic_write(IO_APIC_ADDR, 0x01, reg32);
@@ -377,6 +380,354 @@ static void ppt_pm_init(struct device *dev)
 	RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
 }
 
+static void mobile5_pm_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "Mobile 5 PM init\n");
+	pci_write_config8(dev, 0xa9, 0x47);
+	RCBA32 (0x1d44) = 0x00000000;
+	(void) RCBA32 (0x1d44);
+	RCBA32 (0x1d48) = 0x00030000;
+	(void) RCBA32 (0x1d48);
+	RCBA32 (0x1e80) = 0x000c0801;
+	(void) RCBA32 (0x1e80);
+	RCBA32 (0x1e84) = 0x000200f0;
+	(void) RCBA32 (0x1e84);
+	RCBA32 (0x2010) = 0x00188200;
+	(void) RCBA32 (0x2010);
+	RCBA32 (0x2014) = 0x14000016;
+	(void) RCBA32 (0x2014);
+	RCBA32 (0x2018) = 0xbc4abcb5;
+	(void) RCBA32 (0x2018);
+	RCBA32 (0x201c) = 0x00000000;
+	(void) RCBA32 (0x201c);
+	RCBA32 (0x2020) = 0xf0c9605b;
+	(void) RCBA32 (0x2020);
+	RCBA32 (0x2024) = 0x13683040;
+	(void) RCBA32 (0x2024);
+	RCBA32 (0x2028) = 0x04c8f16e;
+	(void) RCBA32 (0x2028);
+	RCBA32 (0x202c) = 0x09e90170;
+	(void) RCBA32 (0x202c);
+	RCBA32 (0x2100) = 0x00000000;
+	(void) RCBA32 (0x2100);
+	RCBA32 (0x2104) = 0x00000757;
+	(void) RCBA32 (0x2104);
+	RCBA32 (0x2108) = 0x00170001;
+	(void) RCBA32 (0x2108);
+	RCBA32 (0x211c) = 0x00000000;
+	(void) RCBA32 (0x211c);
+	RCBA32 (0x2120) = 0x00010000;
+	(void) RCBA32 (0x2120);
+	RCBA32 (0x21fc) = 0x00000000;
+	(void) RCBA32 (0x21fc);
+	RCBA32 (0x2200) = 0x20000044;
+	(void) RCBA32 (0x2200);
+	RCBA32 (0x2204) = 0x00000001;
+	(void) RCBA32 (0x2204);
+	RCBA32 (0x2208) = 0x00003457;
+	(void) RCBA32 (0x2208);
+	RCBA32 (0x2210) = 0x00000000;
+	(void) RCBA32 (0x2210);
+	RCBA32 (0x2214) = 0x00000001;
+	(void) RCBA32 (0x2214);
+	RCBA32 (0x2218) = 0xa0fff210;
+	(void) RCBA32 (0x2218);
+	RCBA32 (0x221c) = 0x0000df00;
+	(void) RCBA32 (0x221c);
+	RCBA32 (0x2220) = 0x00e30880;
+	(void) RCBA32 (0x2220);
+	RCBA32 (0x2224) = 0x00000070;
+	(void) RCBA32 (0x2224);
+	RCBA32 (0x2228) = 0x00004000;
+	(void) RCBA32 (0x2228);
+	RCBA32 (0x222c) = 0x00000000;
+	(void) RCBA32 (0x222c);
+	RCBA32 (0x2230) = 0x00e30880;
+	(void) RCBA32 (0x2230);
+	RCBA32 (0x2234) = 0x00000070;
+	(void) RCBA32 (0x2234);
+	RCBA32 (0x2238) = 0x00004000;
+	(void) RCBA32 (0x2238);
+	RCBA32 (0x223c) = 0x00000000;
+	(void) RCBA32 (0x223c);
+	RCBA32 (0x2240) = 0x00002301;
+	(void) RCBA32 (0x2240);
+	RCBA32 (0x2244) = 0x36000000;
+	(void) RCBA32 (0x2244);
+	RCBA32 (0x2248) = 0x00010107;
+	(void) RCBA32 (0x2248);
+	RCBA32 (0x224c) = 0x00160000;
+	(void) RCBA32 (0x224c);
+	RCBA32 (0x2250) = 0x00001b01;
+	(void) RCBA32 (0x2250);
+	RCBA32 (0x2254) = 0x36000000;
+	(void) RCBA32 (0x2254);
+	RCBA32 (0x2258) = 0x00010107;
+	(void) RCBA32 (0x2258);
+	RCBA32 (0x225c) = 0x00160000;
+	(void) RCBA32 (0x225c);
+	RCBA32 (0x2260) = 0x00000601;
+	(void) RCBA32 (0x2260);
+	RCBA32 (0x2264) = 0x16000000;
+	(void) RCBA32 (0x2264);
+	RCBA32 (0x2268) = 0x00010107;
+	(void) RCBA32 (0x2268);
+	RCBA32 (0x226c) = 0x00160000;
+	(void) RCBA32 (0x226c);
+	RCBA32 (0x2270) = 0x00001c01;
+	(void) RCBA32 (0x2270);
+	RCBA32 (0x2274) = 0x16000000;
+	(void) RCBA32 (0x2274);
+	RCBA32 (0x2278) = 0x00010107;
+	(void) RCBA32 (0x2278);
+	RCBA32 (0x227c) = 0x00160000;
+	(void) RCBA32 (0x227c);
+	RCBA32 (0x2300) = 0x00000000;
+	(void) RCBA32 (0x2300);
+	RCBA32 (0x2304) = 0x40000000;
+	(void) RCBA32 (0x2304);
+	RCBA32 (0x2308) = 0x4646827b;
+	(void) RCBA32 (0x2308);
+	RCBA32 (0x230c) = 0x6e803131;
+	(void) RCBA32 (0x230c);
+	RCBA32 (0x2310) = 0x32c77887;
+	(void) RCBA32 (0x2310);
+	RCBA32 (0x2314) = 0x00077733;
+	(void) RCBA32 (0x2314);
+	RCBA32 (0x2318) = 0x00007447;
+	(void) RCBA32 (0x2318);
+	RCBA32 (0x231c) = 0x00000040;
+	(void) RCBA32 (0x231c);
+	RCBA32 (0x2320) = 0xcccc0cfc;
+	(void) RCBA32 (0x2320);
+	RCBA32 (0x2324) = 0x0fbb0fff;
+	(void) RCBA32 (0x2324);
+	RCBA32 (0x30fc) = 0x00000000;
+	(void) RCBA32 (0x30fc);
+	RCBA32 (0x3100) = 0x04341200;
+	(void) RCBA32 (0x3100);
+	RCBA32 (0x3104) = 0x00000000;
+	(void) RCBA32 (0x3104);
+	RCBA32 (0x3108) = 0x40043214;
+	(void) RCBA32 (0x3108);
+	RCBA32 (0x310c) = 0x00014321;
+	(void) RCBA32 (0x310c);
+	RCBA32 (0x3110) = 0x00000002;
+	(void) RCBA32 (0x3110);
+	RCBA32 (0x3114) = 0x30003214;
+	(void) RCBA32 (0x3114);
+	RCBA32 (0x311c) = 0x00000002;
+	(void) RCBA32 (0x311c);
+	RCBA32 (0x3120) = 0x00000000;
+	(void) RCBA32 (0x3120);
+	RCBA32 (0x3124) = 0x00002321;
+	(void) RCBA32 (0x3124);
+	RCBA32 (0x313c) = 0x00000000;
+	(void) RCBA32 (0x313c);
+	RCBA32 (0x3140) = 0x00003107;
+	(void) RCBA32 (0x3140);
+	RCBA32 (0x3144) = 0x76543210;
+	(void) RCBA32 (0x3144);
+	RCBA32 (0x3148) = 0x00000010;
+	(void) RCBA32 (0x3148);
+	RCBA32 (0x314c) = 0x00007654;
+	(void) RCBA32 (0x314c);
+	RCBA32 (0x3150) = 0x00000004;
+	(void) RCBA32 (0x3150);
+	RCBA32 (0x3158) = 0x00000000;
+	(void) RCBA32 (0x3158);
+	RCBA32 (0x315c) = 0x00003210;
+	(void) RCBA32 (0x315c);
+	RCBA32 (0x31fc) = 0x03000000;
+	(void) RCBA32 (0x31fc);
+	RCBA32 (0x330c) = 0x00000000;
+	(void) RCBA32 (0x330c);
+	RCBA32 (0x3310) = 0x02060100;
+	(void) RCBA32 (0x3310);
+	RCBA32 (0x3314) = 0x0000000f;
+	(void) RCBA32 (0x3314);
+	RCBA32 (0x3318) = 0x01020000;
+	(void) RCBA32 (0x3318);
+	RCBA32 (0x331c) = 0x80000000;
+	(void) RCBA32 (0x331c);
+	RCBA32 (0x3324) = 0x04000000;
+	(void) RCBA32 (0x3324);
+	RCBA32 (0x3340) = 0x000fffff;
+	(void) RCBA32 (0x3340);
+	RCBA32 (0x3378) = 0x7f8fdfff;
+	(void) RCBA32 (0x3378);
+	RCBA32 (0x33a0) = 0x00003900;
+	(void) RCBA32 (0x33a0);
+	RCBA32 (0x33c0) = 0x00010000;
+	(void) RCBA32 (0x33c0);
+	RCBA32 (0x33cc) = 0x0001004b;
+	(void) RCBA32 (0x33cc);
+	RCBA32 (0x33d0) = 0x06000008;
+	(void) RCBA32 (0x33d0);
+	RCBA32 (0x33d4) = 0x00010000;
+	(void) RCBA32 (0x33d4);
+	RCBA32 (0x33fc) = 0x00000000;
+	(void) RCBA32 (0x33fc);
+	RCBA32 (0x3400) = 0x0000001c;
+	(void) RCBA32 (0x3400);
+	RCBA32 (0x3404) = 0x00000080;
+	(void) RCBA32 (0x3404);
+	RCBA32 (0x340c) = 0x00000000;
+	(void) RCBA32 (0x340c);
+	RCBA32 (0x3410) = 0x00000c61;
+	(void) RCBA32 (0x3410);
+	RCBA32 (0x3414) = 0x00000000;
+	(void) RCBA32 (0x3414);
+	RCBA32 (0x3418) = 0x16e61fe1;
+	(void) RCBA32 (0x3418);
+	RCBA32 (0x341c) = 0xbf4f001f;
+	(void) RCBA32 (0x341c);
+	RCBA32 (0x3420) = 0x00000000;
+	(void) RCBA32 (0x3420);
+	RCBA32 (0x3424) = 0x00060010;
+	(void) RCBA32 (0x3424);
+	RCBA32 (0x3428) = 0x0000001d;
+	(void) RCBA32 (0x3428);
+	RCBA32 (0x343c) = 0x00000000;
+	(void) RCBA32 (0x343c);
+	RCBA32 (0x3440) = 0xdeaddeed;
+	(void) RCBA32 (0x3440);
+	RCBA32 (0x34fc) = 0x00000000;
+	(void) RCBA32 (0x34fc);
+	RCBA32 (0x3500) = 0x20000557;
+	(void) RCBA32 (0x3500);
+	RCBA32 (0x3504) = 0x2000055f;
+	(void) RCBA32 (0x3504);
+	RCBA32 (0x3508) = 0x2000074b;
+	(void) RCBA32 (0x3508);
+	RCBA32 (0x350c) = 0x2000074b;
+	(void) RCBA32 (0x350c);
+	RCBA32 (0x3510) = 0x20000557;
+	(void) RCBA32 (0x3510);
+	RCBA32 (0x3514) = 0x2000014b;
+	(void) RCBA32 (0x3514);
+	RCBA32 (0x3518) = 0x2000074b;
+	(void) RCBA32 (0x3518);
+	RCBA32 (0x351c) = 0x2000074b;
+	(void) RCBA32 (0x351c);
+	RCBA32 (0x3520) = 0x2000074b;
+	(void) RCBA32 (0x3520);
+	RCBA32 (0x3524) = 0x2000074b;
+	(void) RCBA32 (0x3524);
+	RCBA32 (0x3528) = 0x2000055f;
+	(void) RCBA32 (0x3528);
+	RCBA32 (0x352c) = 0x2000055f;
+	(void) RCBA32 (0x352c);
+	RCBA32 (0x3530) = 0x20000557;
+	(void) RCBA32 (0x3530);
+	RCBA32 (0x3534) = 0x2000055f;
+	(void) RCBA32 (0x3534);
+	RCBA32 (0x355c) = 0x00000000;
+	(void) RCBA32 (0x355c);
+	RCBA32 (0x3560) = 0x00000001;
+	(void) RCBA32 (0x3560);
+	RCBA32 (0x3564) = 0x000026a3;
+	(void) RCBA32 (0x3564);
+	RCBA32 (0x3568) = 0x00040002;
+	(void) RCBA32 (0x3568);
+	RCBA32 (0x356c) = 0x01000052;
+	(void) RCBA32 (0x356c);
+	RCBA32 (0x3570) = 0x02000772;
+	(void) RCBA32 (0x3570);
+	RCBA32 (0x3574) = 0x16000f8f;
+	(void) RCBA32 (0x3574);
+	RCBA32 (0x3578) = 0x1800ff4f;
+	(void) RCBA32 (0x3578);
+	RCBA32 (0x357c) = 0x0001d630;
+	(void) RCBA32 (0x357c);
+	RCBA32 (0x359c) = 0x00000000;
+	(void) RCBA32 (0x359c);
+	RCBA32 (0x35a0) = 0xfc000201;
+	(void) RCBA32 (0x35a0);
+	RCBA32 (0x35a4) = 0x3c000201;
+	(void) RCBA32 (0x35a4);
+	RCBA32 (0x35fc) = 0x00000000;
+	(void) RCBA32 (0x35fc);
+	RCBA32 (0x3600) = 0x0a001f00;
+	(void) RCBA32 (0x3600);
+	RCBA32 (0x3608) = 0x00000000;
+	(void) RCBA32 (0x3608);
+	RCBA32 (0x360c) = 0x00000001;
+	(void) RCBA32 (0x360c);
+	RCBA32 (0x3610) = 0x00010000;
+	(void) RCBA32 (0x3610);
+	RCBA32 (0x36d0) = 0x00000000;
+	(void) RCBA32 (0x36d0);
+	RCBA32 (0x36d4) = 0x089c0018;
+	(void) RCBA32 (0x36d4);
+	RCBA32 (0x36dc) = 0x00000000;
+	(void) RCBA32 (0x36dc);
+	RCBA32 (0x36e0) = 0x11111111;
+	(void) RCBA32 (0x36e0);
+	RCBA32 (0x3720) = 0x00000000;
+	(void) RCBA32 (0x3720);
+	RCBA32 (0x3724) = 0x4e564d49;
+	(void) RCBA32 (0x3724);
+	RCBA32 (0x37fc) = 0x00000000;
+	(void) RCBA32 (0x37fc);
+	RCBA32 (0x3800) = 0x07ff0500;
+	(void) RCBA32 (0x3800);
+	RCBA32 (0x3804) = 0x3f04e008;
+	(void) RCBA32 (0x3804);
+	RCBA32 (0x3808) = 0x0058efc0;
+	(void) RCBA32 (0x3808);
+	RCBA32 (0x380c) = 0x00000000;
+	(void) RCBA32 (0x380c);
+	RCBA32 (0x384c) = 0x92000000;
+	(void) RCBA32 (0x384c);
+	RCBA32 (0x3850) = 0x00000a0b;
+	(void) RCBA32 (0x3850);
+	RCBA32 (0x3854) = 0x00000000;
+	(void) RCBA32 (0x3854);
+	RCBA32 (0x3858) = 0x07ff0500;
+	(void) RCBA32 (0x3858);
+	RCBA32 (0x385c) = 0x04ff0003;
+	(void) RCBA32 (0x385c);
+	RCBA32 (0x3860) = 0x00020001;
+	(void) RCBA32 (0x3860);
+	RCBA32 (0x3864) = 0x00000fff;
+	(void) RCBA32 (0x3864);
+	RCBA32 (0x3870) = 0x00000000;
+	(void) RCBA32 (0x3870);
+	RCBA32 (0x3874) = 0x9fff07d0;
+	(void) RCBA32 (0x3874);
+	RCBA32 (0x388c) = 0x00000000;
+	(void) RCBA32 (0x388c);
+	RCBA32 (0x3890) = 0xf8400000;
+	(void) RCBA32 (0x3890);
+	RCBA32 (0x3894) = 0x143b5006;
+	(void) RCBA32 (0x3894);
+	RCBA32 (0x3898) = 0x05200302;
+	(void) RCBA32 (0x3898);
+	RCBA32 (0x389c) = 0x0601209f;
+	(void) RCBA32 (0x389c);
+	RCBA32 (0x38ac) = 0x00000000;
+	(void) RCBA32 (0x38ac);
+	RCBA32 (0x38b0) = 0x00000004;
+	(void) RCBA32 (0x38b0);
+	RCBA32 (0x38b4) = 0x03040002;
+	(void) RCBA32 (0x38b4);
+	RCBA32 (0x38c0) = 0x00000007;
+	(void) RCBA32 (0x38c0);
+	RCBA32 (0x38c4) = 0x00802005;
+	(void) RCBA32 (0x38c4);
+	RCBA32 (0x38c8) = 0x00002005;
+	(void) RCBA32 (0x38c8);
+	RCBA32 (0x3dfc) = 0x00000000;
+	(void) RCBA32 (0x3dfc);
+	RCBA32 (0x3e7c) = 0xffffffff;
+	(void) RCBA32 (0x3e7c);
+	RCBA32 (0x3efc) = 0x00000000;
+	(void) RCBA32 (0x3efc);
+	RCBA32 (0x3f00) = 0x0000010b;
+	(void) RCBA32 (0x3f00);
+}
+
 static void enable_hpet(void)
 {
 	u32 reg32;
@@ -489,12 +840,14 @@ static void pch_disable_smm_only_flashing(struct device *dev)
 
 static void pch_fixups(struct device *dev)
 {
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
 	u8 gen_pmcon_2;
 
 	/* Indicate DRAM init done for MRC S3 to know it can resume */
 	gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
 	gen_pmcon_2 |= (1 << 7);
 	pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+#endif
 
 	/*
 	 * Enable DMI ASPM in the PCH
@@ -542,6 +895,9 @@ static void lpc_init(struct device *dev)
 	case PCH_TYPE_PPT: /* PantherPoint */
 		ppt_pm_init(dev);
 		break;
+	case PCH_TYPE_MOBILE5:
+		mobile5_pm_init (dev);
+		break;
 	default:
 		printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
 	}
@@ -686,7 +1042,7 @@ static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a,
 						 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e,
 						 0x1c4f, 0x1c50, 0x1c52, 0x1c54,
 						 0x1e55, 0x1c56, 0x1e57, 0x1c5c,
-						 0x1e5d, 0x1e5e, 0x1e5f,
+						 0x1e5d, 0x1e5e, 0x1e5f, 0x3b07,
 						 0 };
 
 static const struct pci_driver pch_lpc __pci_driver = {
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 7fdf926..9c6efc3 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -38,7 +38,12 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+# if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
+#  include <northbridge/intel/sandybridge/pcie_config.c>
+# endif
+# if CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#  include <northbridge/intel/calpella/pcie_config.c>
+# endif
 #else
 # include <device/device.h>
 # include <device/pci.h>
@@ -379,7 +384,7 @@ static int mkhi_end_of_post(void)
 }
 #endif
 
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__)
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) && (CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)
 /* Get ME firmware version */
 static int mkhi_get_fw_version(void)
 {
@@ -723,7 +728,7 @@ static void intel_me_init(device_t dev)
 		if (intel_mei_setup(dev) < 0)
 			break;
 
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && (CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)
 		/* Print ME firmware version */
 		mkhi_get_fw_version();
 		/* Print ME firmware capabilities */
@@ -768,10 +773,14 @@ static struct device_operations device_ops = {
 	.ops_pci		= &pci_ops,
 };
 
+static const unsigned short pci_device_ids[] = { 0x1c3a, 0x3b64,
+						 0 };
+
+
 static const struct pci_driver intel_me __pci_driver = {
 	.ops	= &device_ops,
 	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x1c3a,
+	.devices	= pci_device_ids
 };
 
 #endif /* !__SMM__ */
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index aaeb24d..6e2062d 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -194,6 +194,7 @@ struct mei_header {
 #define MKHI_MDES_ENABLE	0x09
 
 #define MKHI_GET_FW_VERSION	0x02
+#define MKHI_SET_UMA  	        0x08
 #define MKHI_END_OF_POST	0x0c
 #define MKHI_FEATURE_OVERRIDE	0x14
 
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index f79adf5..d9d556c 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -38,7 +38,12 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
+#include <northbridge/intel/sandybridge/pcie_config.c>
+#endif
+#if CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#include <northbridge/intel/calpella/pcie_config.c>
+#endif
 #else
 # include <device/device.h>
 # include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 90de855..356dd8a 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -22,8 +22,9 @@
 #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
 
 /* PCH types */
-#define PCH_TYPE_CPT	0x1c /* CougarPoint */
-#define PCH_TYPE_PPT	0x1e /* IvyBridge */
+#define PCH_TYPE_CPT	   0x1c /* CougarPoint */
+#define PCH_TYPE_PPT	   0x1e /* IvyBridge */
+#define PCH_TYPE_MOBILE5   0x3b
 
 /* PCH stepping values for LPC device */
 #define PCH_STEP_A0	0
@@ -73,6 +74,9 @@ void pch_log_state(void);
 void enable_smbus(void);
 void enable_usb_bar(void);
 int smbus_read_byte(unsigned device, unsigned address);
+int smbus_write_byte(unsigned device, unsigned address, u8 data);
+int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
+int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
 int early_spi_read(u32 offset, u32 size, u8 *buffer);
 #endif
 #endif
@@ -343,6 +347,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
 #define D31IP		0x3100	/* 32bit */
 #define D31IP_TTIP	24	/* Thermal Throttle Pin */
 #define D31IP_SIP2	20	/* SATA Pin 2 */
+#define D31IP_UNKIP	16
 #define D31IP_SMIP	12	/* SMBUS Pin */
 #define D31IP_SIP	8	/* SATA Pin */
 #define D30IP		0x3104	/* 32bit */
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 4786d8b..ad7c8f9 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -100,7 +100,7 @@ static struct device_operations smbus_ops = {
 	.ops_pci		= &smbus_pci_ops,
 };
 
-static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 };
+static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 };
 
 static const struct pci_driver pch_smbus __pci_driver = {
 	.ops	 = &smbus_ops,
diff --git a/src/southbridge/intel/bd82x6x/smbus.h b/src/southbridge/intel/bd82x6x/smbus.h
index 81e5949..d6e4ce5 100644
--- a/src/southbridge/intel/bd82x6x/smbus.h
+++ b/src/southbridge/intel/bd82x6x/smbus.h
@@ -98,3 +98,147 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add
 	return byte;
 }
 
+#ifdef __PRE_RAM__
+
+static  int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
+{
+	unsigned char global_status_register;
+
+	if (smbus_wait_until_ready(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(data, smbus_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+	     smbus_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+	global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	if (global_status_register != (1 << 1))
+		return SMBUS_ERROR;
+
+	return 0;
+}
+
+static int do_smbus_block_write(unsigned smbus_base, unsigned device,
+			      unsigned cmd, unsigned bytes, const u8 *buf)
+{
+	u8 status;
+
+	if (smbus_wait_until_ready(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(cmd & 0xff, smbus_base + SMBHSTCMD);
+	/* Set up for a block data write */
+	outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
+	     (smbus_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+	/* set number of bytes to transfer */
+	outb(bytes, smbus_base + SMBHSTDAT0);
+
+	outb(*buf++, smbus_base + SMBBLKDAT);
+	bytes--;
+
+	/* Start the command */
+	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+	     smbus_base + SMBHSTCTL);
+
+	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	/* Poll for transaction completion */
+	do {
+		status = inb(smbus_base + SMBHSTSTAT);
+		if (status & ((1 << 4) | /* FAILED */
+			      (1 << 3) | /* BUS ERR */
+			      (1 << 2))) /* DEV ERR */
+			return SMBUS_ERROR;
+
+		if (status & 0x80) { /* Byte done */
+			outb(*buf++, smbus_base + SMBBLKDAT);
+			outb(status, smbus_base + SMBHSTSTAT);
+		}
+	} while(status & 0x01);
+
+	return 0;
+}
+
+static int do_smbus_block_read(unsigned smbus_base, unsigned device,
+			      unsigned cmd, unsigned bytes, u8 *buf)
+{
+	u8 status;
+	int bytes_read = 0;
+	if (smbus_wait_until_ready(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(cmd & 0xff, smbus_base + SMBHSTCMD);
+	/* Set up for a block data read */
+	outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
+	     (smbus_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+	/* Start the command */
+	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+	     smbus_base + SMBHSTCTL);
+
+	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	/* Poll for transaction completion */
+	do {
+		status = inb(smbus_base + SMBHSTSTAT);
+		if (status & ((1 << 4) | /* FAILED */
+			      (1 << 3) | /* BUS ERR */
+			      (1 << 2))) /* DEV ERR */
+			return SMBUS_ERROR;
+
+		if (status & 0x80) { /* Byte done */
+			*buf = inb(smbus_base + SMBBLKDAT);
+			buf++;
+			bytes_read++;
+			outb(status, smbus_base + SMBHSTSTAT);
+			if (--bytes == 1) {
+				/* indicate that next byte is the last one */
+				outb(inb(smbus_base + SMBHSTCTL) | 0x20,
+					 smbus_base + SMBHSTCTL);
+			}
+		}
+	} while(status & 0x01);
+
+	return bytes_read;
+}
+#endif
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index f34a96e..0bde792 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -34,6 +34,10 @@
 #include "northbridge/intel/sandybridge/sandybridge.h"
 #endif
 
+#if CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#include "northbridge/intel/calpella/calpella.h"
+#endif
+
 extern unsigned char _binary_smm_start;
 extern unsigned char _binary_smm_end;
 
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 545e268..2967e50 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -36,8 +36,15 @@
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
-#include <northbridge/intel/sandybridge/sandybridge.h>
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
+#include "northbridge/intel/sandybridge/sandybridge.h"
 #include <northbridge/intel/sandybridge/pcie_config.c>
+#endif
+
+#if CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#include "northbridge/intel/calpella/calpella.h"
+#include <northbridge/intel/calpella/pcie_config.c>
+#endif
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 09169b1..3a2e62c 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -34,7 +34,12 @@
 #define min(a, b) ((a)<(b)?(a):(b))
 
 #ifdef __SMM__
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
 #include <northbridge/intel/sandybridge/pcie_config.c>
+#endif
+#if CONFIG_NORTHBRIDGE_INTEL_CALPELLA
+#include <northbridge/intel/calpella/pcie_config.c>
+#endif
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pcie_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\
@@ -315,7 +320,8 @@ static inline int get_ich_version(uint16_t device_id)
 	if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
 	     device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
 	    (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
-	     device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
+	     device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)
+	    || device_id == 0x3b07)
 		return 9;
 
 	return 0;
diff --git a/src/southbridge/intel/calpella/Kconfig b/src/southbridge/intel/calpella/Kconfig
new file mode 100644
index 0000000..f18d7b3
--- /dev/null
+++ b/src/southbridge/intel/calpella/Kconfig
@@ -0,0 +1,72 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_CALPELLA
+	bool
+
+if SOUTHBRIDGE_INTEL_CALPELLA
+
+config SOUTH_BRIDGE_OPTIONS # dummy
+	def_bool y
+	select IOAPIC
+	select HAVE_HARD_RESET
+	select HAVE_USBDEBUG
+	select HAVE_SMI_HANDLER
+	select USE_WATCHDOG_ON_BOOT
+	select PCIEXP_ASPM
+	select PCIEXP_COMMON_CLOCK
+	select SPI_FLASH
+
+config EHCI_BAR
+	hex
+	default 0xfef00000
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xa0
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/intel/bd82x6x/bootblock.c"
+
+config SERIRQ_CONTINUOUS_MODE
+	bool
+	default n
+	help
+	  If you set this option to y, the serial IRQ machine will be
+	  operated in continuous mode.
+
+config HPET_MIN_TICKS
+	hex
+	default 0x80
+
+config LOCK_MANAGEMENT_ENGINE
+	bool "Lock Management Engine section"
+	default n
+	help
+	  The Intel Management Engine supports preventing write accesses
+	  from the host to the Management Engine section in the firmware
+	  descriptor. If the ME section is locked, it can only be overwritten
+	  with an external SPI flash programmer. You will want this if you
+	  want to increase security of your ROM image once you are sure
+	  that the ME firmware is no longer going to change.
+
+	  If unsure, say N.
+
+endif
diff --git a/src/southbridge/intel/calpella/Makefile.inc b/src/southbridge/intel/calpella/Makefile.inc
new file mode 100644
index 0000000..63113d9
--- /dev/null
+++ b/src/southbridge/intel/calpella/Makefile.inc
@@ -0,0 +1,77 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+INTERMEDIATE+=bd82x6x_add_me
+
+ramstage-y += ../bd82x6x/pch.c
+ramstage-y += ../bd82x6x/azalia.c
+ramstage-y += ../bd82x6x/lpc.c
+ramstage-y += ../bd82x6x/pci.c
+ramstage-y += ../bd82x6x/pcie.c
+ramstage-y += sata.c
+ramstage-y += usb_ehci.c
+ramstage-y += ../bd82x6x/me.c
+ramstage-y += ../bd82x6x/me_8.x.c
+ramstage-y += ../bd82x6x/smbus.c
+ramstage-y += thermal.c
+
+ramstage-y += ../bd82x6x/me_status.c
+ramstage-y += ../bd82x6x/reset.c
+ramstage-y += ../bd82x6x/watchdog.c
+
+ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
+ramstage-y += ../bd82x6x/spi.c
+ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+smm-$(CONFIG_SPI_FLASH_SMM) += ../bd82x6x/spi.c
+smm-$(CONFIG_USBDEBUG) += usb_debug.c
+
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../bd82x6x/smi.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) +=../bd82x6x/smihandler.c ../bd82x6x/me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
+
+romstage-y += ../bd82x6x/early_usb.c ../bd82x6x/early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c
+romstage-$(CONFIG_USBDEBUG) += usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+smm-$(CONFIG_USBDEBUG) += usb_debug.c
+romstage-y += ../bd82x6x/reset.c
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c
+
+bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL)
+	printf "    DD         Adding Intel Firmware Descriptor\n"
+	dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
+		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
+	$(objutil)/ifdtool/ifdtool \
+		-i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
+		$(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
+	printf "    IFDTOOL    Locking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+else
+	printf "    IFDTOOL    Unlocking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
+
+PHONY += bd82x6x_add_me
diff --git a/src/southbridge/intel/calpella/sata.c b/src/southbridge/intel/calpella/sata.c
new file mode 100644
index 0000000..d6c4c83
--- /dev/null
+++ b/src/southbridge/intel/calpella/sata.c
@@ -0,0 +1,295 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "../bd82x6x/pch.h"
+
+typedef struct southbridge_intel_bd82x6x_config config_t;
+
+static inline u32 sir_read(struct device *dev, int idx)
+{
+	pci_write_config32(dev, SATA_SIRI, idx);
+	return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(struct device *dev, int idx, u32 value)
+{
+	pci_write_config32(dev, SATA_SIRI, idx);
+	pci_write_config32(dev, SATA_SIRD, value);
+}
+
+static void sata_init(struct device *dev)
+{
+	u32 reg32;
+	u16 reg16;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	printk(BIOS_DEBUG, "SATA: Initializing...\n");
+
+	if (config == NULL) {
+		printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
+		return;
+	}
+
+	/* SATA configuration */
+
+	/* Enable BARs */
+	pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+	if (config->ide_legacy_combined) {
+		printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
+
+		/* No AHCI: clear AHCI base */
+		pci_write_config32(dev, 0x24, 0x00000000);
+		/* And without AHCI BAR no memory decoding */
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 &= ~PCI_COMMAND_MEMORY;
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+
+		pci_write_config8(dev, 0x09, 0x80);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* Port enable */
+		reg16 = pci_read_config16(dev, 0x92);
+		reg16 &= ~0x3f;
+		reg16 |= config->sata_port_map;
+		pci_write_config16(dev, 0x92, reg16);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94,
+			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
+	} else if(config->sata_ahci) {
+		u32 abar;
+
+		printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
+
+		/* Set Interrupt Line */
+		/* Interrupt Pin is set by D31IP.PIP */
+		pci_write_config8(dev, INTR_LN, 0x0b);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, 0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL;// | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* for AHCI, Port Enable is managed in memory mapped space */
+		reg16 = pci_read_config16(dev, 0x92);
+		reg16 &= ~0x3f; /* 6 ports SKU + ORM */
+		reg16 |= 0x8100 | config->sata_port_map;
+		pci_write_config16(dev, 0x92, reg16);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94,
+			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183 | 0x40000000);
+		pci_write_config32(dev, 0x98, 0x00590200);
+
+		/* Initialize AHCI memory-mapped space */
+		abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+		printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+		/* CAP (HBA Capabilities) : enable power management */
+		reg32 = read32(abar + 0x00);
+		reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
+		reg32 &= ~0x00020060; // clear SXS+EMS+PMS
+		/* Set ISS, if available */
+		if (config->sata_interface_speed_support)
+		{
+			reg32 &= ~0x00f00000;
+			reg32 |= (config->sata_interface_speed_support & 0x03)
+			  << 20;
+		}
+		write32(abar + 0x00, reg32);
+		/* PI (Ports implemented) */
+		write32(abar + 0x0c, config->sata_port_map);
+		(void) read32(abar + 0x0c); /* Read back 1 */
+		(void) read32(abar + 0x0c); /* Read back 2 */
+		/* CAP2 (HBA Capabilities Extended)*/
+		reg32 = read32(abar + 0x24);
+		reg32 &= ~0x00000002;
+		write32(abar + 0x24, reg32);
+		/* VSP (Vendor Specific Register */
+		reg32 = read32(abar + 0xa0);
+		reg32 &= ~0x00000005;
+		write32(abar + 0xa0, reg32);
+	} else {
+		printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
+
+		/* No AHCI: clear AHCI base */
+		pci_write_config32(dev, 0x24, 0x00000000);
+
+		/* And without AHCI BAR no memory decoding */
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 &= ~PCI_COMMAND_MEMORY;
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+
+		/* Native mode capable on both primary and secondary (0xa)
+		 * or'ed with enabled (0x50) = 0xf
+		 */
+		pci_write_config8(dev, 0x09, 0x8f);
+
+		/* Set Interrupt Line */
+		/* Interrupt Pin is set by D31IP.PIP */
+		pci_write_config8(dev, INTR_LN, 0xff);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_SITRE | IDE_ISP_3_CLOCKS |
+				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* Port enable */
+		reg16 = pci_read_config16(dev, 0x92);
+		reg16 &= ~0x3f;
+		reg16 |= config->sata_port_map;
+		pci_write_config16(dev, 0x92, reg16);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94,
+			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
+	}
+
+	/* Set Gen3 Transmitter settings if needed */
+	if (config->sata_port0_gen3_tx)
+		pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
+				config->sata_port0_gen3_tx);
+
+	if (config->sata_port1_gen3_tx)
+		pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
+				config->sata_port1_gen3_tx);
+
+	/* Additional Programming Requirements */
+	sir_write(dev, 0x04, 0x00000000);
+	sir_write(dev, 0x28, 0x0a000033);
+	reg32 = sir_read(dev, 0x54);
+	reg32 &= 0xff000000;
+	reg32 |= 0x555555;
+	sir_write(dev, 0x54, reg32);
+	sir_write(dev, 0x64, 0xcccccccc);
+	reg32 = sir_read(dev, 0x68);
+	reg32 &= 0xffff0000;
+	reg32 |= 0xcccc;
+	sir_write(dev, 0x68, reg32);
+	reg32 = sir_read(dev, 0x78);
+	reg32 &= 0x0000ffff;
+	reg32 |= 0x88880000;
+	sir_write(dev, 0x78, reg32);
+	sir_write(dev, 0x84, 0x001c7000);
+	sir_write(dev, 0x88, 0x88888888);
+	sir_write(dev, 0xa0, 0x001c7000);
+	// a4
+	sir_write(dev, 0xc4, 0x0c0c0c0c);
+	sir_write(dev, 0xc8, 0x0c0c0c0c);
+	sir_write(dev, 0xd4, 0x10000000);
+
+	pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
+	pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
+}
+
+static void sata_enable(device_t dev)
+{
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+	u16 map = 0;
+
+	if (!config)
+		return;
+
+	/*
+	 * Set SATA controller mode early so the resource allocator can
+	 * properly assign IO/Memory resources for the controller.
+	 */
+	if (config->sata_ahci)
+		map = 0x0060;
+
+	map |= (config->sata_port_map ^ 0x3f) << 8;
+
+	pci_write_config16(dev, 0x90, map);
+}
+
+static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations sata_pci_ops = {
+	.set_subsystem    = sata_set_subsystem,
+};
+
+static struct device_operations sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= sata_init,
+	.enable			= sata_enable,
+	.scan_bus		= 0,
+	.ops_pci		= &sata_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b2e, 0 };
+
+static const struct pci_driver pch_sata __pci_driver = {
+	.ops	 = &sata_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
+
diff --git a/src/southbridge/intel/calpella/thermal.c b/src/southbridge/intel/calpella/thermal.c
new file mode 100644
index 0000000..93d9950
--- /dev/null
+++ b/src/southbridge/intel/calpella/thermal.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "../bd82x6x/pch.h"
+#include <usbdebug.h>
+#include <arch/io.h>
+
+static void thermal_init(struct device *dev)
+{
+  struct resource *res;
+
+  printk(BIOS_DEBUG, "Thermal init start.\n");
+
+  res = find_resource(dev, 0x10);
+  if (!res) return;
+
+  write32 (res->base + 4, 0x3a2b);
+  write8 (res->base + 0xe, 0x40);
+  write32 (res->base + 0x12, 0x1a40);
+  write16 (res->base + 0x16, 0x7746);
+  write16 (res->base + 0x1a, 0x10f0);
+  write16 (res->base + 0x56, 0xffff);
+  write16 (res->base + 0x64, 0xffff);
+  write16 (res->base + 0x66, 0xffff);
+  write16 (res->base + 0x68, 0xfa);
+
+  write8 (res->base + 1, 0xb8);
+
+  printk(BIOS_DEBUG, "Thermal init done.\n");
+}
+
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = set_subsystem,
+};
+
+static struct device_operations thermal_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= thermal_init,
+	.scan_bus		= 0,
+	.ops_pci		= &pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b32, 0 };
+
+static const struct pci_driver pch_thermal __pci_driver = {
+	.ops	 = &thermal_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
diff --git a/src/southbridge/intel/calpella/usb_debug.c b/src/southbridge/intel/calpella/usb_debug.c
new file mode 100644
index 0000000..5b17a79
--- /dev/null
+++ b/src/southbridge/intel/calpella/usb_debug.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include "../bd82x6x/pch.h"
+#include <delay.h>
+#if !defined (__PRE_RAM__) && !defined (__SMM__)
+#define PCI_DEV(bus, dev, fn) dev_find_slot (bus, PCI_DEVFN (dev, fn))
+#endif
+
+
+void enable_usbdebug(unsigned int port)
+{
+	u32 dbgctl;
+	device_t dev = PCI_DEV(0, 0x1a, 0); /* USB EHCI, D29:F7 */
+	device_t bdev = PCI_DEV(0, 0, 0); /* USB EHCI, D29:F7 */
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+
+	pci_write_config16(bdev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	/* Force ownership of the Debug Port to the EHCI controller. */
+	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
+	dbgctl |= (1 << 30);
+	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
+}
+
+/* Required for successful build, but currently empty. */
+void set_debug_port(unsigned int port)
+{
+	/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
+}
+
diff --git a/src/southbridge/intel/calpella/usb_ehci.c b/src/southbridge/intel/calpella/usb_ehci.c
new file mode 100644
index 0000000..ac53f4e
--- /dev/null
+++ b/src/southbridge/intel/calpella/usb_ehci.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "../bd82x6x/pch.h"
+#include <usbdebug.h>
+#include <arch/io.h>
+
+static void usb_ehci_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Disable Wake on Disconnect in RMH */
+	reg32 = RCBA32(0x35b0);
+	reg32 |= 0x22;
+	RCBA32(0x35b0) = reg32;
+
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+
+	if (PCI_SLOT (dev->path.pci.devfn) == 0x1a)
+	  pci_write_config32 (dev, 0x6c, 0x400a2005);
+	else
+	  pci_write_config32 (dev, 0x6c, 0x40082005);
+
+	pci_write_config32 (dev, 0x70, 0x3fdd0000);
+	pci_write_config32 (dev, 0x84, 0x130c8911);
+	pci_write_config32 (dev, 0x88, 0xa0);
+	if (PCI_SLOT (dev->path.pci.devfn) == 0x1a)
+	  pci_write_config32 (dev, 0xec, 0x00629500);
+	else
+	  pci_write_config32 (dev, 0xec, 0x00a10880);
+	pci_write_config32 (dev, 0xf4, 0x80808588);
+	pci_write_config32 (dev, 0xf4, 0x00808588);
+	pci_write_config32 (dev, 0xf4, 0x00808588);
+	pci_write_config32 (dev, 0xfc, 0x301b1728);
+
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER;
+	//reg32 |= PCI_COMMAND_SERR;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	u8 access_cntl;
+
+	access_cntl = pci_read_config8(dev, 0x80);
+
+	/* Enable writes to protected registers. */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+
+	/* Restore protection. */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static void usb_ehci_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+  u32 usb_debug = 0;
+
+  if (PCI_SLOT(dev->path.pci.devfn) == 0x1a)
+    {
+	usb_debug = get_ehci_debug();
+	set_ehci_debug(0);
+    }
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+  if (PCI_SLOT(dev->path.pci.devfn) == 0x1a)
+    {
+        struct resource *res;
+        u32 base;
+	res = find_resource(dev, 0x10);
+	if (!res) return;
+	base = res->base;
+	set_ehci_debug(usb_debug);
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+    }
+#endif
+}
+
+
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= &usb_ehci_set_subsystem,
+};
+
+static struct device_operations usb_ehci_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= usb_ehci_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_ehci_init,
+	.scan_bus		= 0,
+	.ops_pci		= &lops_pci,
+};
+
+static const unsigned short pci_device_ids[] = { 0x3b34, 0x3b3c, 0 };
+
+static const struct pci_driver pch_usb_ehci __pci_driver = {
+	.ops	 = &usb_ehci_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};



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