[coreboot-gerrit] New patch to review for coreboot: 354650a usbdebug: Support i82801dx/ex southbridge

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Thu Jun 6 14:20:32 CEST 2013


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3381

-gerrit

commit 354650ac9bb970befb82da51aad62931cf8af01f
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jun 6 10:21:28 2013 +0300

    usbdebug: Support i82801dx/ex southbridge
    
    Tested on i82801dx system with board aopen/dxplplusu.
    No i82801gx register defines here, so drop the unused include.
    
    Change-Id: I522455ac79c87b9b6fc9cd8c4dc0da3563dfbfad
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/intel/i82801dx/Kconfig      | 13 +++++++++++++
 src/southbridge/intel/i82801dx/Makefile.inc |  3 +++
 src/southbridge/intel/i82801ex/Kconfig      | 12 ++++++++++++
 src/southbridge/intel/i82801ex/Makefile.inc |  3 +++
 src/southbridge/intel/i82801gx/usb_debug.c  |  1 -
 5 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index bad9936..4a43458 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -24,3 +24,16 @@ config SOUTHBRIDGE_INTEL_I82801DX
 	select IOAPIC
 	select HAVE_HARD_RESET
 	select HAVE_SMI_HANDLER
+	select HAVE_USBDEBUG
+
+if SOUTHBRIDGE_INTEL_I82801DX
+
+config EHCI_BAR
+	hex
+	default 0xfef00000
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0x80
+
+endif
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index e412ef9..061ddcc 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -33,3 +33,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c
+romstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+smm-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig
index 23a68b8..b1d7dbb 100644
--- a/src/southbridge/intel/i82801ex/Kconfig
+++ b/src/southbridge/intel/i82801ex/Kconfig
@@ -2,4 +2,16 @@ config SOUTHBRIDGE_INTEL_I82801EX
 	bool
 	select IOAPIC
 	select HAVE_HARD_RESET
+	select HAVE_USBDEBUG
 
+if SOUTHBRIDGE_INTEL_I82801EX
+
+config EHCI_BAR
+	hex
+	default 0xfef00000
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xa0
+
+endif
diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc
index fb76a98..3609fbe 100644
--- a/src/southbridge/intel/i82801ex/Makefile.inc
+++ b/src/southbridge/intel/i82801ex/Makefile.inc
@@ -9,3 +9,6 @@ ramstage-y += pci.c
 ramstage-y += ac97.c
 ramstage-y += watchdog.c
 ramstage-y += reset.c
+
+romstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c
diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index f447f7b..10a308f3 100644
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -25,7 +25,6 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <device/pci_def.h>
-#include "i82801gx.h"
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)



More information about the coreboot-gerrit mailing list