[coreboot-gerrit] Patch set updated for coreboot: a446c75 AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'

Paul Menzel (paulepanter@users.sourceforge.net) gerrit at coreboot.org
Wed Jun 5 09:51:16 CEST 2013

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3374


commit a446c751c3d6403b4f3398f07a2d5c46dc7291c5
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Wed Jun 5 14:32:51 2013 +0800

    AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'
    This issue can be reproduced in Linux by the following steps:
    1) use pm-suspend to suspend.
    2) use USB keyboard to wake up.
    3) use pm-suspend to suspend. FAIL To SUSPEND.
    The cause of this issue is:
    USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
    but this bit is not clear after wake up. So OS thinks there is a
    wake up signal and wake up immediately.
    In this patch, I add AcpiGpe0Blk using MMIO access and write 1
    on bit 11. Write 1 to clear as spec says.
    I have tested on Thatcher
    The same change was done for AMD Parmer in commit »AMD Parmer:
    fix issue 'S3 fails to suspend after wake up from USB keyboard'
    (03901124) [1].
    [1] http://review.coreboot.org/#/c/3347/
        (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1)
    Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
 src/mainboard/amd/thatcher/dsdt.asl | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl
index 7f08bbb..e48c9cf 100644
--- a/src/mainboard/amd/thatcher/dsdt.asl
+++ b/src/mainboard/amd/thatcher/dsdt.asl
@@ -202,6 +202,14 @@ DefinitionBlock (
 	/* PM1 Event Block
 	* First word is PM1_Status, Second word is PM1_Enable
+	/* AcpiGpe0Blk */
+	OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+		Field(GP0B, ByteAcc, NoLock, Preserve) {
+		, 11,
+		USBS, 1,
+	}
 	Scope(\_SB) {
 		/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
 		OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
@@ -844,6 +852,8 @@ DefinitionBlock (
 		*	Store(Arg0, Index(WKST,1))
 		* }
+		/* clear USB wake up signal */
+		Store(1, USBS)
 	} /* End Method(\_WAK) */

More information about the coreboot-gerrit mailing list