[coreboot-gerrit] Patch merged into coreboot/master: 1b22827 Asus F2A85-M: Fix the _CRS PCI0 bus info

gerrit at coreboot.org gerrit at coreboot.org
Mon Jun 3 17:50:26 CEST 2013

the following patch was just integrated into master:
commit 1b22827cf0f190f26dcccec5ae5f36eb4972cde4
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Mon May 27 20:39:18 2013 +0200

    Asus F2A85-M: Fix the _CRS PCI0 bus info
    On Asus F2A85-M, the Linux kernel complains that the _CRS method does
    not specify the number of PCI busses.
        [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS
    Just put there 256. This should be part of re-factoring of the whole
    ACPI stuff.
    The same change was already done for the AMD Brazos (SB800) boards,
    based on commit »Persimmon DSDT: Add secondary bus range to PCI0«
    (4733c647) [1].
    [1] http://review.coreboot.org/2592
    Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
    Reviewed-on: http://review.coreboot.org/3320
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth at se-eng.com>
    Reviewed-by: David Hubbard <david.c.hubbard+coreboot at gmail.com>

See http://review.coreboot.org/3320 for details.


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