[coreboot-gerrit] Patch merged into coreboot/master: c883fdc exynox5420: Remove the 5250 clock registers and fix the SPI frequency.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c883fdc964207d3871e8609c67988c07d448a87d
Author: Gabe Black <gabeblack at google.com>
Date:   Tue Jun 18 06:08:42 2013 -0700

    exynox5420: Remove the 5250 clock registers and fix the SPI frequency.
    
    The 5420 clock code still had a data structure in it for the 5250 clock
    registers which was used by some of the clock functions. That caused some
    clocks to be configured incorrectly, specifically the i2c clock which was
    running at about 80KHz instead of about 600KHz as configured by U-Boot.
    
    Also, the registers and bit positions used to set up the SPI bus were not
    consistent with U-Boot, and if the bus clock rate were set to 50MHz, a rate
    which has historically worked on snow, loading would fail. With these fixes
    the clock rate can be set to 50MHz and the device boots as much as is
    expected. I haven't yet measured the actual frequency of the bus to verify
    that it's now being calculated correctly.
    
    Change-Id: Id53448fcb6d186bddb3f889c84ba267135dfbc00
    Signed-off-by: Gabe Black <gabeblack at chromium.org>
    Reviewed-on: http://review.coreboot.org/3678
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/3678 for details.

-gerrit