[coreboot-gerrit] Patch set updated for coreboot: e98de3b include: Fix spelling
Martin Roth (martin.roth@se-eng.com)
gerrit at coreboot.org
Wed Jul 10 16:42:31 CEST 2013
Martin Roth (martin.roth at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3755
-gerrit
commit e98de3b206f27773150547901f26a3a5fccf3eab
Author: Martin Roth <martin.roth at se-eng.com>
Date: Tue Jul 9 21:46:01 2013 -0600
include: Fix spelling
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/include/boot/coreboot_tables.h | 6 +++---
src/include/boot/elf_boot.h | 4 ++--
src/include/bootstate.h | 2 +-
src/include/cbfs_core.h | 2 +-
src/include/cbmem.h | 4 ++--
src/include/console/console.h | 2 +-
src/include/console/post_codes.h | 10 +++++-----
src/include/cpu/amd/amdfam10_sysconf.h | 2 +-
src/include/cpu/amd/amdk8_sysconf.h | 2 +-
src/include/cpu/amd/gx2def.h | 12 ++++++------
src/include/cpu/amd/lxdef.h | 12 ++++++------
src/include/cpu/x86/mtrr.h | 4 ++--
src/include/cpu/x86/smm.h | 4 ++--
src/include/device/dram/ddr3.h | 2 +-
src/include/device/pci_def.h | 6 +++---
src/include/ehci.h | 2 +-
src/include/gpio.h | 2 +-
src/include/pc80/mc146818rtc.h | 2 +-
src/include/rmodule.h | 6 +++---
src/include/romstage_handoff.h | 6 +++---
src/include/swab.h | 2 +-
src/include/thread.h | 4 ++--
src/include/timer.h | 6 +++---
src/include/uart8250.h | 2 +-
24 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index ee1c29f..87819ce 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -6,11 +6,11 @@
/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
- * other means, such as quering the hardware directly.
+ * other means, such as querying the hardware directly.
*
* All of the information should be Position Independent Data.
* That is it should be safe to relocated any of the information
- * without it's meaning/correctnes changing. For table that
+ * without it's meaning/correctness changing. For table that
* can reasonably be used on multiple architectures the data
* size should be fixed. This should ease the transition between
* 32 bit and 64 bit architectures etc.
@@ -27,7 +27,7 @@
* table entry is required or not. This should remove much of the
* long term compatibility burden as table entries which are
* irrelevant or have been replaced by better alternatives may be
- * dropped. Of course it is polite and expidite to include extra
+ * dropped. Of course it is polite and expedite to include extra
* table entries and be backwards compatible, but it is not required.
*/
diff --git a/src/include/boot/elf_boot.h b/src/include/boot/elf_boot.h
index b119bab..89772a8 100644
--- a/src/include/boot/elf_boot.h
+++ b/src/include/boot/elf_boot.h
@@ -10,7 +10,7 @@
*
* All of the information must be Position Independent Data.
* That is it must be safe to relocate the whole ELF boot parameter
- * block without changing the meaning or correctnes of the data.
+ * block without changing the meaning or correctness of the data.
* Additionally it must be safe to permute the order of the ELF notes
* to any possible permutation without changing the meaning or correctness
* of the data.
@@ -51,7 +51,7 @@ typedef struct
#define EBN_BOOTLOADER_NAME 0x00000002
/* This specifies just the name of the bootloader for easy comparison */
#define EBN_BOOTLOADER_VERSION 0x00000003
-/* This specifies the version of the bootlader */
+/* This specifies the version of the bootloader */
#define EBN_COMMAND_LINE 0x00000004
/* This specifies a command line that can be set by user interaction,
* and is provided as a free form string to the loaded image.
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 40822a7..23398a2 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -148,7 +148,7 @@ struct boot_state_callback {
bscb_->arg = arg_
/* The following 2 functions schedule a callback to be called on entry/exit
- * to a given state. Note that thare are no ordering guarantees between the
+ * to a given state. Note that there are no ordering guarantees between the
* individual callbacks on a given state. 0 is returned on success < 0 on
* error. */
int boot_state_sched_on_entry(struct boot_state_callback *bscb,
diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h
index 20636e2..54e2f60 100644
--- a/src/include/cbfs_core.h
+++ b/src/include/cbfs_core.h
@@ -56,7 +56,7 @@
#include <stdint.h>
/** These are standard values for the known compression
- alogrithms that coreboot knows about for stages and
+ algorithms that coreboot knows about for stages and
payloads. Of course, other CBFS users can use whatever
values they want, as long as they understand them. */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index efb0f90..982a6d8 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -86,7 +86,7 @@ struct cbmem_entry;
* implemented by the board or chipset to define the upper address where
* cbmem lives. This address is required to be a 32-bit address. Additionally,
* the address needs to be consistent in both romstage and ramstage. The
- * dynamic cbmem infrasturue allocates new regions below the last allocated
+ * dynamic cbmem infrastructure allocates new regions below the last allocated
* region. Regions are defined by a cbmem_entry struct that is opaque. Regions
* may be removed, but the last one added is the only that can be removed.
*
@@ -100,7 +100,7 @@ struct cbmem_entry;
#define DYN_CBMEM_ALIGN_SIZE (4096)
-/* Initialze cbmem to be empty. */
+/* Initialize cbmem to be empty. */
void cbmem_initialize_empty(void);
/* Return the top address for dynamic cbmem. The address returned needs to
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 9112f35..7faa873 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -60,7 +60,7 @@ extern struct console_driver econsole_drivers[];
extern int console_loglevel;
#else
/* __PRE_RAM__ */
-/* Using a global varible can cause problems when we reset the stack
+/* Using a global variable can cause problems when we reset the stack
* from cache as ram to ram. If we make this a define USE_SHARED_STACK
* we could use the same code on all architectures.
*/
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index f66d276..a0dd694 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -24,7 +24,7 @@
* This aims to be a central point for POST codes used throughout coreboot.
* All POST codes should be declared here as macros, and post_code() should
* be used with the macros instead of hardcoded values. This allows us to
- * quicly reference POST codes when nothing is working
+ * quickly reference POST codes when nothing is working
*
* The format for a POST code macro is
* #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
@@ -93,7 +93,7 @@
* \brief Entry into coreboot in hardwaremain (RAM)
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has succesfully loaded and started executing.
+ * ramstage has successfully loaded and started executing.
*/
#define POST_ENTRY_RAMSTAGE 0x80
@@ -107,7 +107,7 @@
/**
* \brief Console boot message succeeded
*
- * First console message has been succesfully sent through the console backend
+ * First console message has been successfully sent through the console backend
* driver.
*/
#define POST_CONSOLE_BOOT_MSG 0x40
@@ -129,7 +129,7 @@
/**
* \brief Devices have been configured
*
- * Device confgration has completed.
+ * Device configuration has completed.
*/
#define POST_DEVICE_CONFIGURATION_COMPLETE 0x88
@@ -207,7 +207,7 @@
/*
* The following POST codes are taken from src/include/cpu/amd/geode_post_code.h
* They overlap with previous codes, and most are not even used
- * Some maiboards still require them, but they are deprecated. We want to consolidate
+ * Some mainboards still require them, but they are deprecated. We want to consolidate
* our own POST code structure with the codes above.
*
* standard AMD post definitions for the AMD Geode
diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h
index 2f08fd8..baba6ce 100644
--- a/src/include/cpu/amd/amdfam10_sysconf.h
+++ b/src/include/cpu/amd/amdfam10_sysconf.h
@@ -64,7 +64,7 @@ struct amdfam10_sysconf_t {
unsigned lift_bsp_apicid;
int apicid_offset;
- void *mb; // pointer for mb releated struct
+ void *mb; // pointer for mb related struct
};
diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h
index 3ae35fd..87bd4d5 100644
--- a/src/include/cpu/amd/amdk8_sysconf.h
+++ b/src/include/cpu/amd/amdk8_sysconf.h
@@ -19,7 +19,7 @@ struct amdk8_sysconf_t {
unsigned lift_bsp_apicid;
int apicid_offset;
- void *mb; // pointer for mb releated struct
+ void *mb; // pointer for mb related struct
};
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index ee55c2f..beb4c65 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -399,12 +399,12 @@
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
#define BMIO 6 /* Base Mask IO */
#define SCIO 7 /* Swiss 0xCeese IO */
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
-#define BMO_SMM 10 /* Specail marker for SMM */
-#define BM_SMM 11 /* Specail marker for SMM */
-#define BMO_DMM 12 /* Specail marker for DMM */
-#define BM_DMM 13 /* Specail marker for DMM */
+#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */
+#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */
+#define BMO_SMM 10 /* Special marker for SMM */
+#define BM_SMM 11 /* Special marker for SMM */
+#define BMO_DMM 12 /* Special marker for DMM */
+#define BM_DMM 13 /* Special marker for DMM */
#define RO_FB 14 /* special for Frame buffer. */
#define R_FB 15 /* special for FB. */
#define OTHER 0x0FE /* Special marker for other */
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 4eee156..da26895 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -533,12 +533,12 @@
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
#define BMIO 6 /* Base Mask IO*/
#define SCIO 7 /* Swiss 0xCeese IO*/
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/
-#define BMO_SMM 10 /* Specail marker for SMM*/
-#define BM_SMM 11 /* Specail marker for SMM*/
-#define BMO_DMM 12 /* Specail marker for DMM*/
-#define BM_DMM 13 /* Specail marker for DMM*/
+#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/
+#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/
+#define BMO_SMM 10 /* Special marker for SMM*/
+#define BM_SMM 11 /* Special marker for SMM*/
+#define BMO_DMM 12 /* Special marker for DMM*/
+#define BM_DMM 13 /* Special marker for DMM*/
#define RO_FB 14 /* special for Frame buffer.*/
#define R_FB 15 /* special for FB.*/
#define OTHER 0x0FE /* Special marker for other*/
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 38c3f7c..017a77e 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -47,14 +47,14 @@
* x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
* of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
* want to call the components of x86_setup_mtrrs() because of other
- * rquirements the ordering should still preserved.
+ * requirements the ordering should still preserved.
* 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
* of the nature of the global MTRR enable flag. Therefore, all direct
* or indirect callers of enable_fixed_mtrr() should ensure that the
* variable MTRR MSRs do not contain bad ranges.
* 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
* the caching of the ROM. However, it is set to uncacheable (UC). It
- * is the responsiblity of the caller to enable it by calling
+ * is the responsibility of the caller to enable it by calling
* x86_mtrr_enable_rom_caching().
*/
void x86_setup_mtrrs(void);
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index df7e3de..cacbff0 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -423,7 +423,7 @@ struct smm_runtime {
u32 save_state_size;
/* The apic_id_to_cpu provides a mapping from APIC id to cpu number.
* The cpu number is indicated by the index into the array by matching
- * the deafult APIC id and value at the index. The stub loader
+ * the default APIC id and value at the index. The stub loader
* initializes this array with a 1:1 mapping. If the APIC ids are not
* contiguous like the 1:1 mapping it is up to the caller of the stub
* loader to adjust this mapping. */
@@ -446,7 +446,7 @@ void *smm_get_save_state(int cpu);
#else
/* SMM Module Loading API */
-/* Ths smm_loader_params structure provides direction to the SMM loader:
+/* The smm_loader_params structure provides direction to the SMM loader:
* - stack_top - optional external stack provided to loader. It must be at
* least per_cpu_stack_size * num_concurrent_stacks in size.
* - per_cpu_stack_size - stack size per cpu for smm modules.
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 69c072b..53a42ee 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -63,7 +63,7 @@
/*
* Module type (byte 3, bits 3:0) of SPD
- * This definition is specific to DDR3. DDR2 SPDs have a diferent structure.
+ * This definition is specific to DDR3. DDR2 SPDs have a different structure.
*/
enum spd_dimm_type {
SPD_DIMM_TYPE_UNDEFINED = 0x00,
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 58a7321..ac20659 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -177,7 +177,7 @@
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
-#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
+#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCIX */
#define PCI_CAP_ID_HT 0x08 /* Hypertransport */
@@ -208,7 +208,7 @@
#define PCI_PM_PMC 2 /* PM Capabilities Register */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
-#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
+#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxiliary power support */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
@@ -255,7 +255,7 @@
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
-/* Message Signalled Interrupts registers */
+/* Message Signaled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
diff --git a/src/include/ehci.h b/src/include/ehci.h
index b096f42..f920352 100644
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -161,7 +161,7 @@ struct ehci_regs {
#define USBMODE_CM_IDLE (0<<0) /* idle state */
/* Moorestown has some non-standard registers, partially due to the fact that
- * its EHCI controller has both TT and LPM support. HOSTPCx are extentions to
+ * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
* PORTSCx
*/
#define HOSTPC0 0x84 /* HOSTPC extension */
diff --git a/src/include/gpio.h b/src/include/gpio.h
index f602b1e..3311fd6 100644
--- a/src/include/gpio.h
+++ b/src/include/gpio.h
@@ -57,7 +57,7 @@ enum gpio_types {
enum mvl3 {
LOGIC_0,
LOGIC_1,
- LOGIC_Z, /* high impedence / tri-stated / floating */
+ LOGIC_Z, /* high impedance / tri-stated / floating */
};
#endif /* GPIO_H */
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 29e0348..170a433 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -22,7 +22,7 @@
/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
- * totalling to a max high interval of 2.228 ms.
+ * totaling to a max high interval of 2.228 ms.
*/
# define RTC_UIP 0x80
# define RTC_DIV_CTL 0x70
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 35a82c1..247711a 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -95,18 +95,18 @@ struct rmodule_header {
u32 relocations_begin_offset;
u32 relocations_end_offset;
/* The starting address of the linked program. This address is vital
- * for determining relocation offsets as the reloction info and other
+ * for determining relocation offsets as the relocation info and other
* symbols (bss, entry point) need this value as a basis to calculate
* the offsets.
*/
u32 module_link_start_address;
/* The module_program_size is the size of memory used while running
- * the program. The program is assumed to consume a contiguos amount
+ * the program. The program is assumed to consume a contiguous amount
* of memory. */
u32 module_program_size;
/* This is program's execution entry point. */
u32 module_entry_point;
- /* Optional paramter structure that can be used to pass data into
+ /* Optional parameter structure that can be used to pass data into
* the module. */
u32 parameters_begin;
u32 parameters_end;
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index 3152fb2..699838a 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -23,12 +23,12 @@
#include <string.h>
#include <cbmem.h>
-/* It is the chipset's responsbility for maintaining the integrity of this
+/* It is the chipset's responsibility for maintaining the integrity of this
* structure in CBMEM. For instance, if chipset code adds this structure
* using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber
* fields it doesn't own. */
struct romstage_handoff {
- /* Inidicate if the current boot is an S3 resume. If
+ /* Indicate if the current boot is an S3 resume. If
* CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is
* responsible for initializing this variable. Otherwise, ramstage
* will be re-loaded from cbfs (which can be slower since it lives
@@ -42,7 +42,7 @@ struct romstage_handoff {
#if defined(__PRE_RAM__)
/* The romstage_handoff_find_or_add() function provides the necessary logic
- * for initializng the romstage_handoff structure in cbmem. Different components
+ * for initializing the romstage_handoff structure in cbmem. Different components
* of the romstage may be responsible for setting up different fields. Therefore
* that same logic flow should be used for allocating and initializing the
* structure. A newly allocated structure will be memset to 0. */
diff --git a/src/include/swab.h b/src/include/swab.h
index c5e4370..8a7daba 100644
--- a/src/include/swab.h
+++ b/src/include/swab.h
@@ -10,7 +10,7 @@
* separated swab functions from cpu_to_XX,
* to clean up support for bizarre-endian architectures.
*
- * See asm-i386/byteorder.h and suches for examples of how to provide
+ * See asm-i386/byteorder.h and such for examples of how to provide
* architecture-dependent optimized versions
*
*/
diff --git a/src/include/thread.h b/src/include/thread.h
index 148c448..0522337 100644
--- a/src/include/thread.h
+++ b/src/include/thread.h
@@ -43,7 +43,7 @@ void threads_initialize(void);
* current state in the boot state machine until it is complete. */
int thread_run(void (*func)(void *), void *arg);
/* thread_run_until is the same as thread_run() except that it blocks state
- * transitions from occuring in the (state, seq) pair of the boot state
+ * transitions from occurring in the (state, seq) pair of the boot state
* machine. */
int thread_run_until(void (*func)(void *), void *arg,
boot_state_t state, boot_state_sequence_t seq);
@@ -52,7 +52,7 @@ int thread_run_until(void (*func)(void *), void *arg,
int thread_yield_microseconds(unsigned microsecs);
/* Allow and prevent thread cooperation on current running thread. By default
- * all threads are marked to be cooperative. That means a thread can yeild
+ * all threads are marked to be cooperative. That means a thread can yield
* to another thread at a pre-determined switch point. Current there is
* only a single place where switching may occur: a call to udelay(). */
void thread_cooperate(void);
diff --git a/src/include/timer.h b/src/include/timer.h
index 40ac367..06128ce 100644
--- a/src/include/timer.h
+++ b/src/include/timer.h
@@ -67,13 +67,13 @@ int timers_run(void);
* 0 returned on success, < 0 on error. */
int timer_sched_callback(struct timeout_callback *tocb, unsigned long us);
-/* Add microseconds to an absoute time. */
+/* Add microseconds to an absolute time. */
static inline void mono_time_add_usecs(struct mono_time *mt, long us)
{
mt->microseconds += us;
}
-/* Add milliseconds to an absoute time. */
+/* Add milliseconds to an absolute time. */
static inline void mono_time_add_msecs(struct mono_time *mt, long ms)
{
mono_time_add_usecs(mt, ms * USECS_PER_MSEC);
@@ -85,7 +85,7 @@ static inline void mono_time_add_rela_time(struct mono_time *mt,
mono_time_add_usecs(mt, t->microseconds);
}
-/* Compare two absoluted times: Return -1, 0, or 1 if t1 is <, =, or > t2,
+/* Compare two absolute times: Return -1, 0, or 1 if t1 is <, =, or > t2,
* respectively. */
static inline int mono_time_cmp(const struct mono_time *t1,
const struct mono_time *t2)
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index d42e822..e6a318a 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -63,7 +63,7 @@
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define UART_LCR_PEN 0x08 /* Parity eneble */
+#define UART_LCR_PEN 0x08 /* Parity enable */
#define UART_LCR_EPS 0x10 /* Even Parity Select */
#define UART_LCR_STKP 0x20 /* Stick Parity */
#define UART_LCR_SBRK 0x40 /* Set Break */
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