[coreboot-gerrit] New patch to review for coreboot: 7d39934 AMD Hudson: show POST codes on a PCI device

[Idwer Vollering (vidwer@gmail.com)]

Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4559

-gerrit

commit 7d39934c91b911bf751517fd7bd33e93b46085ca
Author: Idwer Vollering <vidwer at gmail.com>
Date:   Sun Dec 22 20:55:41 2013 +0000

    AMD Hudson: show POST codes on a PCI device
    
    Show POST codes on a PCI device: implement hudson_pci_port80();.
    This shares much code with sb600/sb700/sb800.
    
    Tested on an Asus F2A85-M.
    
    Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a
    Signed-off-by: Idwer Vollering <vidwer at gmail.com>
---
 src/southbridge/amd/agesa/hudson/early_setup.c | 45 ++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index 96861c9..690e987 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -29,6 +29,51 @@
 #include <cbmem.h>
 #include "hudson.h"
 
+void hudson_pci_port80(void)
+{
+	u8 byte;
+	device_t dev;
+
+	/* P2P Bridge */
+	dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
+
+	/* Chip Control: Enable subtractive decoding */
+	byte = pci_read_config8(dev, 0x40);
+	byte |= 1 << 5;
+	pci_write_config8(dev, 0x40, byte);
+
+	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
+	byte = pci_read_config8(dev, 0x4B);
+	byte |= 1 << 7;
+	pci_write_config8(dev, 0x4B, byte);
+
+	/* The same IO Base and IO Limit here is meaningful because we set the
+	 * bridge to be subtractive. During early setup stage, we have to make
+	 * sure that data can go through port 0x80.
+	 */
+	/* IO Base: 0xf000 */
+	byte = pci_read_config8(dev, 0x1C);
+	byte |= 0xF << 4;
+	pci_write_config8(dev, 0x1C, byte);
+
+	/* IO Limit: 0xf000 */
+	byte = pci_read_config8(dev, 0x1D);
+	byte |= 0xF << 4;
+	pci_write_config8(dev, 0x1D, byte);
+
+	/* PCI Command: Enable IO response */
+	byte = pci_read_config8(dev, 0x04);
+	byte |= 1 << 0;
+	pci_write_config8(dev, 0x04, byte);
+
+	/* LPC controller */
+	dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+
+	byte = pci_read_config8(dev, 0x4A);
+	byte &= ~(1 << 5);      /* disable lpc port 80 */
+	pci_write_config8(dev, 0x4A, byte);
+}
+
 void hudson_lpc_port80(void)
 {
 	u8 byte;