[coreboot-gerrit] Patch merged into coreboot/master: c31eb36 exynos5420: Set SPLL to 400MHz

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c31eb3619d09671960d6fa2614c53fc5dfa2e4cf
Author: David Hendricks <dhendrix at chromium.org>
Date:   Fri Aug 9 18:59:02 2013 -0700

    exynos5420: Set SPLL to 400MHz
    
    Increase SPLL to 400MHz from 300MHz as we set SPLL as the
    switching parent for ARM and KFC. This value is as per
    recommendation of the hardware team.
    
    This is ported from https://gerrit.chromium.org/gerrit/62618
    
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223
    Reviewed-on: https://gerrit.chromium.org/gerrit/65432
    Reviewed-by: Gabe Black <gabeblack at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>
    Commit-Queue: Gabe Black <gabeblack at chromium.org>


See http://review.coreboot.org/4464 for details.

-gerrit