[coreboot-gerrit] Patch merged into coreboot/master: dad3433 exynos5420: correct the PMS value for CPLL

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit dad3433a759d0aac43027c1292420f468247cb8e
Author: David Hendricks <dhendrix at chromium.org>
Date:   Thu Aug 8 16:04:07 2013 -0700

    exynos5420: correct the PMS value for CPLL
    
    This patch matches the User Manual Table 7-2 about the PMS value for
    CPLL. This doesn't change the PLL frequency (before and after both make
    666MHz) but this is the suggested PMSK values for obtaining 666.
    (Suggested as per user manual).
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/
    
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Ia33e1971ab88da761000d443792560476514626b
    Reviewed-on: https://gerrit.chromium.org/gerrit/65281
    Reviewed-by: Gabe Black <gabeblack at chromium.org>
    Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>


See http://review.coreboot.org/4460 for details.

-gerrit