[coreboot-gerrit] Patch merged into coreboot/master: caa0f7d exynos5420: set L2ACTLR parameters for A15 cores

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit caa0f7d56bee6765c90b0739bc0bb349a9616f59
Author: David Hendricks <dhendrix at chromium.org>
Date:   Tue Aug 6 18:05:55 2013 -0700

    exynos5420: set L2ACTLR parameters for A15 cores
    
    This patch does the following for the A15 cores:
    - Disable clean/evict push to external
    - Enable hazard detect timout
    - Prevent gating the L2 logic clock
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/60154
    
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536
    Reviewed-on: https://gerrit.chromium.org/gerrit/64862
    Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>


See http://review.coreboot.org/4441 for details.

-gerrit