[coreboot-gerrit] Patch set updated for coreboot: 2319bec haswell: Misc updates from 1.6.1 ref code
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sat Dec 21 10:54:05 CET 2013
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4466
-gerrit
commit 2319becb198751f004ff2dbc1167f10fa358916b
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Mon Aug 12 13:51:22 2013 -0700
haswell: Misc updates from 1.6.1 ref code
These programming sequences were changed in the latest code.
Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65612
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/northbridge/intel/haswell/gma.c | 21 ++++++---------------
src/southbridge/intel/lynxpoint/pcie.c | 3 ---
2 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index f13ef7a..00d7583 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -350,20 +350,11 @@ static void gma_pm_init_post_vbios(struct device *dev)
gpu_is_ulx = 1;
/* CD Frequency */
- if (gtt_read(0x42014) & 0x1000000) {
- cdclk = 0; /* only 450mhz */
- } else {
- cdclk = 2; /* 337.5mhz, 450mhz, or 540mhz */
- if (gpu_is_ulx)
- cdclk = 0; /* only 337.5mhz */
-
- /* TODO: this check does not seem right... */
- if (haswell_is_ult() &&
- haswell_stepping() < HASWELL_STEPPING_MOBILE_D0)
- cdclk = 0; /* only 450mhz */
- else
- cdclk = 1; /* 337.5mhz and 450mhz */
- }
+ if ((gtt_read(0x42014) & 0x1000000) || gpu_is_ulx || haswell_is_ult())
+ cdclk = 0; /* fixed frequency */
+ else
+ cdclk = 2; /* variable frequency */
+
if (gpu_is_ulx || cdclk != 0)
gtt_rmw(0x130040, 0xf7ffffff, 0x04000000);
else
@@ -371,7 +362,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
/* More magic */
if (haswell_is_ult() || gpu_is_ulx) {
- if (cdclk == 1 && gpu_is_ulx == 0)
+ if (!gpu_is_ulx)
gtt_write(0x138128, 0x00000000);
else
gtt_write(0x138128, 0x00000001);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 6a4d75c..581b79d 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -649,9 +649,6 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74);
- /* Set undocumented bits in MPC2 register. */
- pcie_update_cfg(dev, 0xd4, ~0, (1 << 12) | (1 << 6));
-
/* Set Invalid Recieve Range Check Enable in MPC register. */
pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));
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