[coreboot-gerrit] Patch set updated for coreboot: b93da45 Calculate transcoder flags based on pipe config
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sat Dec 21 09:14:22 CET 2013
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4402
-gerrit
commit b93da45e3bef2217b643c1e2c897842059e70cc8
Author: Furquan Shaikh <furquan at google.com>
Date: Tue Jul 30 12:41:08 2013 -0700
Calculate transcoder flags based on pipe config
Works fine with all three panels with the change of 6 bits per color.
Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e
Reviewed-on: https://gerrit.chromium.org/gerrit/63762
Reviewed-by: Ronald G. Minnich <rminnich at chromium.org>
Commit-Queue: Furquan Shaikh <furquan at chromium.org>
Tested-by: Furquan Shaikh <furquan at chromium.org>
---
src/drivers/intel/gma/i915.h | 24 +++++++++++++
src/drivers/intel/gma/i915_reg.h | 1 +
src/drivers/intel/gma/intel_ddi.c | 66 ++++++++++++++++++++++++++++++++++++
src/lib/edid.c | 1 +
src/mainboard/google/slippy/gma.c | 12 +++++--
src/mainboard/google/slippy/i915io.c | 2 +-
6 files changed, 103 insertions(+), 3 deletions(-)
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 62fe023..1aed2bf 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -40,6 +40,22 @@
#define PRB0_START 0x02038
#define PRB0_CTL 0x0203c
+enum port {
+ PORT_A = 0,
+ PORT_B,
+ PORT_C,
+ PORT_D,
+ PORT_E,
+ I915_NUM_PORTS
+};
+
+enum pipe {
+ PIPE_A = 0,
+ PIPE_B,
+ PIPE_C,
+ I915_NUM_PIPES
+};
+
/* debug enums. These are for printks that, due to their place in the
* middle of graphics device IO, might change timing. Use with care
* or not at all.
@@ -143,6 +159,7 @@ struct intel_dp {
u32 pipesrc;
u32 stride;
struct intel_dp_m_n m_n;
+ u32 flags;
};
/* we may yet need these. */
@@ -197,3 +214,10 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
unsigned int pixel_clock,
unsigned int link_clock,
struct intel_dp_m_n *m_n);
+
+u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
+ enum port port,
+ enum pipe pipe,
+ int type,
+ int lane_count,
+ int pf_sz);
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h
index 27a3d2b..d0c8c85 100644
--- a/src/drivers/intel/gma/i915_reg.h
+++ b/src/drivers/intel/gma/i915_reg.h
@@ -4554,6 +4554,7 @@
#define DDI_BUF_EMP_MASK (0xf<<24)
#define DDI_BUF_IS_IDLE (1<<7)
#define DDI_A_4_LANES (1<<4)
+#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
#define DDI_PORT_WIDTH_X1 (0<<1)
#define DDI_PORT_WIDTH_X2 (1<<1)
#define DDI_PORT_WIDTH_X4 (3<<1)
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 220bd47..f1a40f1 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -157,3 +157,69 @@ void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port)
udelay(600);
}
+
+u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
+ enum port port,
+ enum pipe pipe,
+ int type,
+ int lane_count,
+ int pf_sz)
+{
+ u32 temp;
+
+ temp = TRANS_DDI_FUNC_ENABLE;
+ temp |= TRANS_DDI_SELECT_PORT(port);
+
+ switch (pipe_bpp) {
+ case 18:
+ temp |= TRANS_DDI_BPC_6;
+ break;
+ case 24:
+ temp |= TRANS_DDI_BPC_8;
+ break;
+ case 30:
+ temp |= TRANS_DDI_BPC_10;
+ break;
+ case 36:
+ temp |= TRANS_DDI_BPC_12;
+ break;
+ default:
+ printk(BIOS_ERR, "Invalid pipe_bpp: %d, *** Initialization will not succeed *** \n", pipe_bpp);
+ }
+
+ if (port == PORT_A) {
+ switch (pipe) {
+ case PIPE_A:
+ if (pf_sz)
+ temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
+ else
+ temp |= TRANS_DDI_EDP_INPUT_A_ON;
+ break;
+ case PIPE_B:
+ temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+ break;
+ case PIPE_C:
+ temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+ break;
+ default:
+ printk(BIOS_ERR, "Invalid pipe %d\n", pipe);
+ }
+ }
+
+ /* We need to check for TRANS_DDI_PVSYNC and TRANS_DDI_PHSYNC -- How? */
+
+ if (type == INTEL_OUTPUT_HDMI) {
+ /* Need to understand when to set TRANS_DDI_MODE_SELECT_HDMI / TRANS_DDI_MODE_SELECT_DVI */
+ } else if (type == INTEL_OUTPUT_ANALOG) {
+ /* Set TRANS_DDI_MODE_SELECT_FDI with lane_count */
+ } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
+ type == INTEL_OUTPUT_EDP) {
+ temp |= TRANS_DDI_MODE_SELECT_DP_SST;
+
+ temp |= DDI_PORT_WIDTH(lane_count);
+ } else {
+ printk(BIOS_ERR, "Invalid type %d for pipe\n", type);
+ }
+
+ return temp;
+}
diff --git a/src/lib/edid.c b/src/lib/edid.c
index dd7c46a..b2bd9b7 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -475,6 +475,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
* we have yet to see a case where that will happen.
*/
out->bpp = 32;
+
out->x_resolution = ALIGN(out->ha * ((out->bpp + 7) / 8),64) / (out->bpp/8);
out->y_resolution = out->va;
out->bytes_per_line = ALIGN(out->ha * ((out->bpp + 7) / 8),64);
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 52a7b0b..99dcbc5 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -288,6 +288,13 @@ void dp_init_dim_regs(struct intel_dp *dp)
dp->pfa_sz = (edid->ha << 16) | (edid->va);
+ dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */
+ dp->port,
+ dp->pipe,
+ dp->type,
+ dp->lane_count,
+ dp->pfa_sz);
+
intel_dp_compute_m_n(dp->bpp,
dp->lane_count,
dp->edid.pixel_clock,
@@ -310,6 +317,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
+ printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
}
int intel_dp_bw_code_to_link_rate(u8 link_bw);
@@ -363,8 +371,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
dp->panel_power_down_delay = 600;
dp->panel_power_up_delay = 200;
dp->panel_power_cycle_delay = 600;
- dp->pipe = 0;
- dp->port = 0;
+ dp->pipe = PIPE_A;
+ dp->port = PORT_A;
dp->clock = 160000;
dp->bpp = 32;
dp->type = INTEL_OUTPUT_EDP;
diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c
index c1e0547..e3f7f30 100644
--- a/src/mainboard/google/slippy/i915io.c
+++ b/src/mainboard/google/slippy/i915io.c
@@ -151,7 +151,7 @@ printk(BIOS_SPEW, "DP_MAX_DOWNSPREAD");
io_i915_write32(0x00230000,TRANS_DDI_FUNC_CTL_EDP);
io_i915_write32(0x00000010,0x7f008);
- io_i915_write32(0x82234000,TRANS_DDI_FUNC_CTL_EDP);
+ io_i915_write32(dp->flags,TRANS_DDI_FUNC_CTL_EDP);
io_i915_write32(0x80000010,0x7f008);
intel_dp_wait_panel_power_control(0xabcd000a);
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