[coreboot-gerrit] Patch set updated for coreboot: 0c0e322 armv7: add wrappers to read/write L2ACTLR
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sat Dec 21 09:04:34 CET 2013
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4437
-gerrit
commit 0c0e322131ea7b5e5a4495d89fde2ec5b6582921
Author: David Hendricks <dhendrix at chromium.org>
Date: Tue Aug 6 17:32:41 2013 -0700
armv7: add wrappers to read/write L2ACTLR
This adds inline wrappers to read the L2 cache auxiliary control
register (L2ACTLR).
Signed-off-by: David Hendricks <dhendrix at chromium.org>
Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f
Reviewed-on: https://gerrit.chromium.org/gerrit/64861
Commit-Queue: David Hendricks <dhendrix at chromium.org>
Reviewed-by: David Hendricks <dhendrix at chromium.org>
Tested-by: David Hendricks <dhendrix at chromium.org>
---
payloads/libpayload/include/armv7/arch/cache.h | 15 +++++++++++++++
src/arch/armv7/include/arch/cache.h | 15 +++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h
index 2928d10..0414da3 100644
--- a/payloads/libpayload/include/armv7/arch/cache.h
+++ b/payloads/libpayload/include/armv7/arch/cache.h
@@ -240,6 +240,21 @@ static inline void write_l2ctlr(uint32_t val)
isb();
}
+/* read L2 Auxiliary Control Register (L2ACTLR) */
+static inline uint32_t read_l2actlr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* write L2 Auxiliary Control Register (L2ACTLR) */
+static inline void write_l2actlr(uint32_t val)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
+ isb();
+}
+
/* read system control register (SCTLR) */
static inline uint32_t read_sctlr(void)
{
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index 5166af3..8a14ff9 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -246,6 +246,21 @@ static inline void write_l2ctlr(uint32_t val)
isb();
}
+/* read L2 Auxiliary Control Register (L2ACTLR) */
+static inline uint32_t read_l2actlr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* write L2 Auxiliary Control Register (L2ACTLR) */
+static inline void write_l2actlr(uint32_t val)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
+ isb();
+}
+
/* read system control register (SCTLR) */
static inline uint32_t read_sctlr(void)
{
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