[coreboot-gerrit] Patch set updated for coreboot: 9d19c06 falco: Force enable ASPM on PCIe Root Port 1

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Fri Dec 20 23:32:30 CET 2013


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4454

-gerrit

commit 9d19c06c7a29e523d4ac6c8b27631d5562019884
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 9 09:11:29 2013 -0700

    falco: Force enable ASPM on PCIe Root Port 1
    
    Boot on falco and look in /sys/firmware/log for
    the string "PCIe Root Port 1 ASPM is enabled"
    
    Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65315
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/falco/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index 82fc513..f453fd2 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -74,6 +74,9 @@ chip northbridge/intel/haswell
 			register "sio_i2c0_voltage" = "0" # 3.3V
 			register "sio_i2c1_voltage" = "0" # 3.3V
 
+			# Force enable ASPM for PCIe Port 1
+			register "pcie_port_force_aspm" = "0x01"
+
 			# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
 			register "icc_clock_disable" = "0x013e0000"
 



More information about the coreboot-gerrit mailing list