[coreboot-gerrit] Patch set updated for coreboot: 9c483c7 slippy/falco/peppy: Route USB to XHCI on resume

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Wed Dec 18 01:56:41 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4404

-gerrit

commit 9c483c781ac9f76945523c6d629fbbb59f3d8e50
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jul 30 15:43:43 2013 -0700

    slippy/falco/peppy: Route USB to XHCI on resume
    
    Turn on the pei_data flag that will instruct the reference code
    binary to route all USB ports to the XHCI controller on resume and
    disable the EHCI controller(s).
    
    Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63798
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/falco/romstage.c  | 1 +
 src/mainboard/google/peppy/romstage.c  | 1 +
 src/mainboard/google/slippy/romstage.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c
index fcf06a9..0ad4b97 100644
--- a/src/mainboard/google/falco/romstage.c
+++ b/src/mainboard/google/falco/romstage.c
@@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist)
 		// Enable 2x refresh mode
 		ddr_refresh_2x: 1,
 		max_ddr3_freq: 1600,
+		usb_xhci_on_resume: 1,
 		usb2_ports: {
 			/* Length, Enable, OCn#, Location */
 			{ 0x0064, 1, 0,               /* P0: Port A, CN8 */
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c
index c213b10..3f3aa6e 100644
--- a/src/mainboard/google/peppy/romstage.c
+++ b/src/mainboard/google/peppy/romstage.c
@@ -146,6 +146,7 @@ void mainboard_romstage_entry(unsigned long bist)
 		dimm_channel0_disabled: 2,
 		dimm_channel1_disabled: 2,
 		max_ddr3_freq: 1600,
+		usb_xhci_on_resume: 1,
 		usb2_ports: {
 			/* Length, Enable, OCn#, Location */
 			{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index a93196a..fdbac97 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -158,6 +158,7 @@ void mainboard_romstage_entry(unsigned long bist)
 		dimm_channel0_disabled: 2,
 		dimm_channel1_disabled: 2,
 		max_ddr3_freq: 1600,
+		usb_xhci_on_resume: 1,
 		usb2_ports: {
 			/* Length, Enable, OCn#, Location */
 			{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */



More information about the coreboot-gerrit mailing list