[coreboot-gerrit] Patch set updated for coreboot: b506f95 Pit: move parade writes to mainboard.c
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu Dec 12 22:12:51 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4362
-gerrit
commit b506f95edef3d49a340079fa07089cfde28f3db5
Author: Ronald G. Minnich <rminnich at google.com>
Date: Wed Jul 10 15:22:17 2013 -0700
Pit: move parade writes to mainboard.c
What gets written into the parade is highly mainboard-dependent.
So the parade_writes array needs to be there.
Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b
Signed-off-by: Ronald G. Minnich <rminnich at google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61486
Reviewed-by: David Hendricks <dhendrix at chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich at chromium.org>
Tested-by: Ronald G. Minnich <rminnich at chromium.org>
---
src/drivers/parade/ps8625/ps8625.c | 134 ++---------------------------------
src/drivers/parade/ps8625/ps8625.h | 10 ++-
src/mainboard/google/pit/mainboard.c | 124 +++++++++++++++++++++++++++++++-
3 files changed, 137 insertions(+), 131 deletions(-)
diff --git a/src/drivers/parade/ps8625/ps8625.c b/src/drivers/parade/ps8625/ps8625.c
index 6cbe3b7..05219b0 100644
--- a/src/drivers/parade/ps8625/ps8625.c
+++ b/src/drivers/parade/ps8625/ps8625.c
@@ -17,143 +17,19 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include "ps8625.h"
-
#include <device/i2c.h>
#include <stdint.h>
#include <stdlib.h>
-struct parade_write {
- uint8_t offset;
- uint8_t reg;
- uint8_t val;
-};
-
-static const struct parade_write parade_writes[] = {
- { 0x02, 0xa1, 0x01 }, /* HPD low */
- /*
- * SW setting
- * [1:0] SW output 1.2V voltage is lower to 96%
- */
- { 0x04, 0x14, 0x01 },
- /*
- * RCO SS setting
- * [5:4] = b01 0.5%, b10 1%, b11 1.5%
- */
- { 0x04, 0xe3, 0x20 },
- { 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */
- /*
- * RPHY Setting
- * [3:2] CDR tune wait cycle before
- * measure for fine tune b00: 1us,
- * 01: 0.5us, 10:2us, 11:4us.
- */
- { 0x04, 0x8a, 0x0c },
- { 0x04, 0x89, 0x08 }, /* [3] RFD always on */
- /*
- * CTN lock in/out:
- * 20000ppm/80000ppm. Lock out 2
- * times.
- */
- { 0x04, 0x71, 0x2d },
- /*
- * 2.7G CDR settings
- * NOF=40LSB for HBR CDR setting
- */
- { 0x04, 0x7d, 0x07 },
- { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */
- { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */
- /*
- * 1.62G CDR settings
- * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
- */
- { 0x04, 0xc0, 0x12 },
- { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */
- { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */
- { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */
- /*
- * RPIO Setting
- * [7:4] LVDS driver bias current :
- * 75% (250mV swing)
- */
- { 0x04, 0x00, 0xb0 },
- /*
- * [7:6] Right-bar GPIO output strength is 8mA
- */
- { 0x04, 0x15, 0x40 },
- /* EQ Training State Machine Setting */
- { 0x04, 0x54, 0x10 }, /* RCO calibration start */
- /* [4:0] MAX_LANE_COUNT set to one lane */
- { 0x01, 0x02, 0x81 },
- /* [4:0] LANE_COUNT_SET set to one lane */
- { 0x01, 0x21, 0x81 },
- { 0x00, 0x52, 0x20 },
- { 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */
- { 0x00, 0x62, 0x41 },
- /* Counter number, add 1ms counter delay */
- { 0x00, 0xf6, 0x01 },
- /*
- * [6]PWM function control by
- * DPCD0040f[7], default is PWM
- * block always works.
- */
- { 0x00, 0x77, 0x06 },
- /*
- * 04h Adjust VTotal tolerance to
- * fix the 30Hz no display issue
- */
- { 0x00, 0x4c, 0x04 },
- /* DPCD00400='h00, Parade OUI = 'h001cf8 */
- { 0x01, 0xc0, 0x00 },
- { 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */
- { 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */
- /*
- * DPCD403~408 = ASCII code
- * D2SLV5='h4432534c5635
- */
- { 0x01, 0xc3, 0x44 },
- { 0x01, 0xc4, 0x32 }, /* DPCD404 */
- { 0x01, 0xc5, 0x53 }, /* DPCD405 */
- { 0x01, 0xc6, 0x4c }, /* DPCD406 */
- { 0x01, 0xc7, 0x56 }, /* DPCD407 */
- { 0x01, 0xc8, 0x35 }, /* DPCD408 */
- /*
- * DPCD40A, Initial Code major revision
- * '01'
- */
- { 0x01, 0xca, 0x01 },
- /* DPCD40B, Initial Code minor revision '05' */
- { 0x01, 0xcb, 0x05 },
- /* DPCD720, Select internal PWM */
- { 0x01, 0xa5, 0xa0 },
- /*
- * FFh for 100% PWM of brightness, 0h for 0%
- * brightness
- */
- { 0x01, 0xa7, 0xff },
- /*
- * Set LVDS output as 6bit-VESA mapping,
- * single LVDS channel
- */
- { 0x01, 0xcc, 0x13 },
- /* Enable SSC set by register */
- { 0x02, 0xb1, 0x20 },
- /*
- * Set SSC enabled and +/-1% central
- * spreading
- */
- { 0x04, 0x10, 0x16 },
- /* MPU Clock source: LC => RCO */
- { 0x04, 0x59, 0x60 },
- { 0x04, 0x54, 0x14 }, /* LC -> RCO */
- { 0x02, 0xa1, 0x91 } /* HPD high */
-};
+#include "ps8625.h"
-void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base)
+void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base,
+ const struct parade_write *parade_writes,
+ int parade_write_count)
{
int i;
- for (i = 0; i < ARRAY_SIZE(parade_writes); i++) {
+ for (i = 0; i < parade_write_count; i++) {
const struct parade_write *w = ¶de_writes[i];
i2c_write(bus, chip_base + w->offset, w->reg, sizeof(w->reg),
&w->val, sizeof(w->val));
diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h
index 2ef7577..82f2499 100644
--- a/src/drivers/parade/ps8625/ps8625.h
+++ b/src/drivers/parade/ps8625/ps8625.h
@@ -20,6 +20,14 @@
#ifndef __PS8625_H__
#define __PS8625_H__
-void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base);
+struct parade_write {
+ uint8_t offset;
+ uint8_t reg;
+ uint8_t val;
+};
+
+void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base,
+ const struct parade_write *,
+ int parade_write_count);
#endif
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index b91040c..515424a 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -51,6 +51,126 @@ static struct edid edid = {
.bpp = 16,
};
+static const struct parade_write parade_writes[] = {
+ { 0x02, 0xa1, 0x01 }, /* HPD low */
+ /*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ { 0x04, 0x14, 0x01 },
+ /*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ { 0x04, 0xe3, 0x20 },
+ { 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */
+ /*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ { 0x04, 0x8a, 0x0c },
+ { 0x04, 0x89, 0x08 }, /* [3] RFD always on */
+ /*
+ * CTN lock in/out:
+ * 20000ppm/80000ppm. Lock out 2
+ * times.
+ */
+ { 0x04, 0x71, 0x2d },
+ /*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ { 0x04, 0x7d, 0x07 },
+ { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */
+ { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */
+ /*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ { 0x04, 0xc0, 0x12 },
+ { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */
+ { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */
+ { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */
+ /*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ { 0x04, 0x00, 0xb0 },
+ /*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ { 0x04, 0x15, 0x40 },
+ /* EQ Training State Machine Setting */
+ { 0x04, 0x54, 0x10 }, /* RCO calibration start */
+ /* [4:0] MAX_LANE_COUNT set to one lane */
+ { 0x01, 0x02, 0x81 },
+ /* [4:0] LANE_COUNT_SET set to one lane */
+ { 0x01, 0x21, 0x81 },
+ { 0x00, 0x52, 0x20 },
+ { 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */
+ { 0x00, 0x62, 0x41 },
+ /* Counter number, add 1ms counter delay */
+ { 0x00, 0xf6, 0x01 },
+ /*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ { 0x00, 0x77, 0x06 },
+ /*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ { 0x00, 0x4c, 0x04 },
+ /* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ { 0x01, 0xc0, 0x00 },
+ { 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */
+ { 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */
+ /*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ { 0x01, 0xc3, 0x44 },
+ { 0x01, 0xc4, 0x32 }, /* DPCD404 */
+ { 0x01, 0xc5, 0x53 }, /* DPCD405 */
+ { 0x01, 0xc6, 0x4c }, /* DPCD406 */
+ { 0x01, 0xc7, 0x56 }, /* DPCD407 */
+ { 0x01, 0xc8, 0x35 }, /* DPCD408 */
+ /*
+ * DPCD40A, Initial Code major revision
+ * '01'
+ */
+ { 0x01, 0xca, 0x01 },
+ /* DPCD40B, Initial Code minor revision '05' */
+ { 0x01, 0xcb, 0x05 },
+ /* DPCD720, Select internal PWM */
+ { 0x01, 0xa5, 0xa0 },
+ /*
+ * FFh for 100% PWM of brightness, 0h for 0%
+ * brightness
+ */
+ { 0x01, 0xa7, 0xff },
+ /*
+ * Set LVDS output as 6bit-VESA mapping,
+ * single LVDS channel
+ */
+ { 0x01, 0xcc, 0x13 },
+ /* Enable SSC set by register */
+ { 0x02, 0xb1, 0x20 },
+ /*
+ * Set SSC enabled and +/-1% central
+ * spreading
+ */
+ { 0x04, 0x10, 0x16 },
+ /* MPU Clock source: LC => RCO */
+ { 0x04, 0x59, 0x60 },
+ { 0x04, 0x54, 0x14 }, /* LC -> RCO */
+ { 0x02, 0xa1, 0x91 } /* HPD high */
+};
+
/* TODO: transplanted DP stuff, clean up once we have something that works */
static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */
static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */
@@ -83,7 +203,9 @@ static void parade_dp_bridge_setup(void)
exynos_pinmux_i2c7();
i2c_init(7, 100000, 0x00);
- parade_ps8625_bridge_setup(7, 0x48);
+ parade_ps8625_bridge_setup(7, 0x48,
+ parade_writes,
+ ARRAY_SIZE(parade_writes));
}
/*
More information about the coreboot-gerrit
mailing list