[coreboot-gerrit] New patch to review for coreboot: 831e24b Asus F2A85-M Move to ther proper SIO

Rudolf Marek (r.marek@assembler.cz) gerrit at coreboot.org
Sat Dec 7 22:52:14 CET 2013


Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4499

-gerrit

commit 831e24b313045c1df2c45ffaf231d91e0ff3cfd3
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Sat Dec 7 22:41:20 2013 +0100

    Asus F2A85-M Move to ther proper SIO
    
    The F2A85-M has IT8603E which is a strip down version of IT8728F. Change configuration from provisional IT8712F to the IT8728F.
    While at it also enable only needed LPC bridge decodes.
    
    Change-Id: I22067b13ea27ee37e959a246718d9559c2a3215d
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/mainboard/asus/f2a85-m/Kconfig        |  2 +-
 src/mainboard/asus/f2a85-m/agesawrapper.c |  7 -------
 src/mainboard/asus/f2a85-m/buildOpts.c    |  1 +
 src/mainboard/asus/f2a85-m/devicetree.cb  | 25 +++++++++++++------------
 src/mainboard/asus/f2a85-m/romstage.c     | 19 ++++++++++++++-----
 5 files changed, 29 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index 1192868..9101d3c 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -35,7 +35,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SERIAL_CPU_INIT
 	select AMDMCT
 	select HAVE_ACPI_TABLES
-	select SUPERIO_ITE_IT8712F
+	select SUPERIO_ITE_IT8728F
 	select BOARD_ROMSIZE_KB_8192
 	select GFXUMA
 
diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c
index 529878b..9a53f9f 100644
--- a/src/mainboard/asus/f2a85-m/agesawrapper.c
+++ b/src/mainboard/asus/f2a85-m/agesawrapper.c
@@ -142,8 +142,6 @@ agesawrapper_amdinitmmio (
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -160,11 +158,6 @@ agesawrapper_amdinitmmio (
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 0091cd9..a7f20fa 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -310,6 +310,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 
 #define DFLT_SMBUS0_BASE_ADDRESS            0xB00
 #define DFLT_SMBUS1_BASE_ADDRESS            0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
 #define DFLT_SIO_PME_BASE_ADDRESS           0xE00
 #define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
 #define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 0014381..da10ac4 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -60,7 +60,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 14.1 off end # IDE	0x439c
 				device pci 14.2 on  end # HDA	0x4383
 				device pci 14.3 on      # LPC	0x439d
-					chip superio/ite/it8712f
+					chip superio/ite/it8728f
 						device pnp 2e.0 off #  Floppy
 							io 0x60 = 0x3f0
 							irq 0x70 = 6
@@ -78,7 +78,11 @@ chip northbridge/amd/agesa/family15tn/root_complex
 							io 0x60 = 0x378
 							irq 0x70 = 7
 						end
-						device pnp 2e.4 off end #  EC
+						device pnp 2e.4 on #  Env Controller
+							io 0x60 = 0x290
+							io 0x62 = 0x220
+							irq 0x70 = 0
+						end
 						device pnp 2e.5 on #  Keyboard
 							io 0x60 = 0x60
 							io 0x62 = 0x64
@@ -87,19 +91,16 @@ chip northbridge/amd/agesa/family15tn/root_complex
 						device pnp 2e.6 off #  Mouse
 							irq 0x70 = 12
 						end
-						device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
-						end
-						device pnp 2e.8 off #  MIDI
-							io 0x60 = 0x300
-							irq 0x70 = 9
-						end
-						device pnp 2e.9 off #  GAME
-							io 0x60 = 0x220
+						device pnp 2e.7 on #  GPIO
+							io 0x60 = 0x228 #SMI
+							io 0x62 = 0x300 #Simple I/O
+							io 0x64 = 0x238 #Phony resource IT8603E does not have it
+							irq 0x70 = 0
 						end
 						device pnp 2e.a off end #  CIR
-					end	#superio/ite/it8712f
+					end	#superio/ite/it8728f
 				end	#device pci 14.3 # LPC
-				device pci 14.4 on  end # PCI	0x4384 # PCI-b conflict with GPIO.
+				device pci 14.4 on  end # PCI 0x4384
 				device pci 14.5 on  end # USB 2
 				device pci 14.6 off end # Gec
 				# SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away)
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 031bb50..990343b 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -34,11 +34,15 @@
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
 #include "southbridge/amd/agesa/hudson/smbus.h"
-#include "superio/ite/it8712f/early_serial.c"
 #include "cpu/amd/agesa/s3_resume.h"
 #include "src/drivers/pc80/i8254.c"
 #include "src/drivers/pc80/i8259.c"
 #include "cbmem.h"
+/* Note that the IT8603E is a strip down version of this chip */
+#include "superio/ite/it8728f/early_serial.h"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
+
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 void disable_cache_as_ram(void);
@@ -74,12 +78,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 
-		/* enable SIO decode */
+		/* enable SIO LPC decode */
 		dev = PCI_DEV(0, 0x14, 3);
 		byte = pci_read_config8(dev, 0x48);
 		byte |= 3;		/* 2e, 2f */
 		pci_write_config8(dev, 0x48, byte);
 
+		/* enable serial decode */
+		byte = pci_read_config8(dev, 0x44);
+		byte |= (1 << 6);  /* 0x3f8 */
+		pci_write_config8(dev, 0x44, byte);
+
 		post_code(0x30);
 
                 /* enable SB MMIO space */
@@ -88,9 +97,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		/* enable SIO clock */
 		sbxxx_enable_48mhzout();
-		it8712f_kill_watchdog();
-		it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
-		it8712f_enable_3vsbsw();
+		it8728f_kill_watchdog(GPIO_DEV);
+		it8728f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		it8728f_enable_3vsbsw(GPIO_DEV);
 		console_init();
 
 		/* turn on secondary smbus at b20 */



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