[coreboot-gerrit] New patch to review for coreboot: 8c18e75 NOTFORMERGE: cpu/intel: Make all CPUs load microcode from CBFS
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Sat Dec 7 19:26:09 CET 2013
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4495
-gerrit
commit 8c18e75276097bd60e28a9194c09ee2ba35e009e
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Fri Dec 6 23:14:54 2013 -0600
NOTFORMERGE: cpu/intel: Make all CPUs load microcode from CBFS
* Better description coming soon to a gerrit page near you *
The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.
Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/cpu/intel/model_1067x/Kconfig | 1 +
src/cpu/intel/model_106cx/Kconfig | 1 +
src/cpu/intel/model_65x/Kconfig | 1 +
src/cpu/intel/model_67x/Kconfig | 1 +
src/cpu/intel/model_68x/Kconfig | 1 +
src/cpu/intel/model_69x/Kconfig | 1 +
src/cpu/intel/model_69x/model_69x_init.c | 14 +-------------
src/cpu/intel/model_6bx/Kconfig | 1 +
src/cpu/intel/model_6dx/Kconfig | 1 +
src/cpu/intel/model_6dx/model_6dx_init.c | 12 +-----------
src/cpu/intel/model_6ex/Kconfig | 1 +
src/cpu/intel/model_6ex/Makefile.inc | 1 +
src/cpu/intel/model_6ex/model_6ex_init.c | 12 +-----------
src/cpu/intel/model_6fx/Kconfig | 1 +
src/cpu/intel/model_6fx/model_6fx_init.c | 2 +-
src/cpu/intel/model_6xx/Kconfig | 1 +
src/cpu/intel/model_f0x/Kconfig | 1 +
src/cpu/intel/model_f1x/Kconfig | 1 +
src/cpu/intel/model_f2x/Kconfig | 1 +
src/cpu/intel/model_f3x/Kconfig | 1 +
src/cpu/intel/model_f4x/Kconfig | 1 +
21 files changed, 21 insertions(+), 36 deletions(-)
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 852c9cd..7d5bf94 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_1067X
select SMP
select SSE2
select TSC_SYNC_MFENCE
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index e26bf1f..c438008 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -6,6 +6,7 @@ config CPU_INTEL_MODEL_106CX
select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
+ select SUPPORT_CPU_UCODE_IN_CBFS
config CPU_ADDR_BITS
int
diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig
index 1ef4813..e8f0767 100644
--- a/src/cpu/intel/model_65x/Kconfig
+++ b/src/cpu/intel/model_65x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_65X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig
index b65081c..74ef8d5 100644
--- a/src/cpu/intel/model_67x/Kconfig
+++ b/src/cpu/intel/model_67x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_67X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig
index f7f05f6..9d9983e 100644
--- a/src/cpu/intel/model_68x/Kconfig
+++ b/src/cpu/intel/model_68x/Kconfig
@@ -21,3 +21,4 @@
config CPU_INTEL_MODEL_68X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig
index 596763c..4e88979 100644
--- a/src/cpu/intel/model_69x/Kconfig
+++ b/src/cpu/intel/model_69x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_69X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index cb805ae..9ee7424 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -9,18 +9,6 @@
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
-static uint32_t microcode_updates[] = {
- #include "microcode-1376-m8069547.h"
- #include "microcode-1373-m1069507.h"
- #include "microcode-1374-m2069507.h"
-
- /* Dummy terminator */
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
-};
-
static void model_69x_init(device_t dev)
{
/* Turn on caching if we haven't already */
@@ -29,7 +17,7 @@ static void model_69x_init(device_t dev)
x86_mtrr_check();
/* Update the microcode */
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
/* Enable the local cpu apics */
setup_lapic();
diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig
index 10661d0..26b5995 100644
--- a/src/cpu/intel/model_6bx/Kconfig
+++ b/src/cpu/intel/model_6bx/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_6BX
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig
index 5e70f59..546d9ec 100644
--- a/src/cpu/intel/model_6dx/Kconfig
+++ b/src/cpu/intel/model_6dx/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_6DX
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 19b351d..06236a3 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -9,16 +9,6 @@
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
-static uint32_t microcode_updates[] = {
- #include "microcode-1355-m206d618.h"
-
- /* Dummy terminator */
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
-};
-
static void model_6dx_init(device_t dev)
{
/* Turn on caching if we haven't already */
@@ -27,7 +17,7 @@ static void model_6dx_init(device_t dev)
x86_mtrr_check();
/* Update the microcode */
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
/* Enable the local cpu apics */
setup_lapic();
diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig
index e2b1986..8187838 100644
--- a/src/cpu/intel/model_6ex/Kconfig
+++ b/src/cpu/intel/model_6ex/Kconfig
@@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6EX
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
index b515c4f..ee6614b 100644
--- a/src/cpu/intel/model_6ex/Makefile.inc
+++ b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,3 +1,4 @@
ramstage-y += model_6ex_init.c
subdirs-y += ../../x86/name
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index e9c63da..4dc642a 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -33,16 +33,6 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
-static const uint32_t microcode_updates[] = {
- #include "microcode-1624-m206e839.h"
- #include "microcode-1729-m206ec54.h"
- #include "microcode-1869-m806ec59.h"
- /* Dummy terminator */
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
-};
#define IA32_FEATURE_CONTROL 0x003a
@@ -160,7 +150,7 @@ static void model_6ex_init(device_t cpu)
x86_enable_cache();
/* Update the microcode */
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index 4517f17..3335a26 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -5,3 +5,4 @@ config CPU_INTEL_MODEL_6FX
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index faf1277..6825727 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -197,7 +197,7 @@ static void model_6fx_init(device_t cpu)
x86_enable_cache();
/* Update the microcode */
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
/* Print processor name */
fill_processor_name(processor_name);
diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig
index 96c7040..b572385 100644
--- a/src/cpu/intel/model_6xx/Kconfig
+++ b/src/cpu/intel/model_6xx/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_6XX
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig
index 9dd7fd0..0616589 100644
--- a/src/cpu/intel/model_f0x/Kconfig
+++ b/src/cpu/intel/model_f0x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_F0X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig
index ea75857..fd64920 100644
--- a/src/cpu/intel/model_f1x/Kconfig
+++ b/src/cpu/intel/model_f1x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_F1X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
index 50cac79..8483d33 100644
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_F2X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
index 4cfca83..8ae2dcf 100644
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_F3X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
index 97c909a..c21a274 100644
--- a/src/cpu/intel/model_f4x/Kconfig
+++ b/src/cpu/intel/model_f4x/Kconfig
@@ -1,3 +1,4 @@
config CPU_INTEL_MODEL_F4X
bool
select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
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