[coreboot-gerrit] New patch to review for coreboot: c923adf haswell: add option to change DqPinsInterleaved
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Dec 4 00:36:01 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4474
-gerrit
commit c923adfcee185ce45fe94c0f11fa77788e100096
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Tue Aug 13 11:18:42 2013 -0700
haswell: add option to change DqPinsInterleaved
Some mainboards will need to have this set.
Signed-off-by: Stefan Reinauer <reinauer at google.com>
Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
Reviewed-on: https://gerrit.chromium.org/gerrit/65722
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Tested-by: Stefan Reinauer <reinauer at google.com>
Commit-Queue: Stefan Reinauer <reinauer at google.com>
---
src/northbridge/intel/haswell/pei_data.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index f9d6e8b..f92c0a6 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -31,7 +31,7 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 14
+#define PEI_VERSION 15
#define MAX_USB2_PORTS 16
#define MAX_USB3_PORTS 16
@@ -92,6 +92,7 @@ struct pei_data
int dimm_channel1_disabled;
/* Enable 2x Refresh Mode */
int ddr_refresh_2x;
+ int dq_pins_interleaved;
/* Data read from flash and passed into MRC */
unsigned char *mrc_input;
unsigned int mrc_input_len;
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