[coreboot-gerrit] New patch to review for coreboot: 960e985 pit: Bump the EC SPI bus speed up to 5 MHz

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4386

-gerrit

commit 960e985911bc2d29e8ca56cc47e461c7a77d386e
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Jul 24 06:18:20 2013 -0700

    pit: Bump the EC SPI bus speed up to 5 MHz
    
    That speed is used with U-Boot instead of the more conservative 500 KHz.
    
    Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee
    Signed-off-by: Gabe Black <gabeblack at google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63193
    Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Commit-Queue: Gabe Black <gabeblack at chromium.org>
    Tested-by: Gabe Black <gabeblack at chromium.org>
---
 src/mainboard/google/pit/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 7ead3c9..b582f3e 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -126,7 +126,7 @@ static void setup_ec(void)
 {
 	/* SPI2 (EC) is slower and needs to work in half-duplex mode with
 	 * single byte bus width. */
-	clock_set_rate(PERIPH_ID_SPI2, 500000);
+	clock_set_rate(PERIPH_ID_SPI2, 5000000);
 	exynos_pinmux_spi2();
 }