[coreboot-gerrit] New patch to review for coreboot: 0d29feb peppy: Add backward-compatible RAM_ID table.

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Tue Dec 3 22:19:45 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4353

-gerrit

commit 0d29febaffab0bcdacfa45c50f66edf3148c5215
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date:   Mon Jul 8 14:26:35 2013 -0700

    peppy: Add backward-compatible RAM_ID table.
    
    Make use of google_chromeec_get_board_version to determine board
    version, and apply proper RAM_ID table to load correct SPD.
    
    Change-Id: I6a2d54759cf2ce98bf53df0db396c6e09368c714
    Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61192
    Reviewed-by: Dave Parker <dparker at chromium.org>
---
 src/mainboard/google/peppy/onboard.h  |  3 +++
 src/mainboard/google/peppy/romstage.c | 26 +++++++++++++++++++++-----
 2 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/peppy/onboard.h b/src/mainboard/google/peppy/onboard.h
index 23e8f1e..0036594 100644
--- a/src/mainboard/google/peppy/onboard.h
+++ b/src/mainboard/google/peppy/onboard.h
@@ -37,4 +37,7 @@
 #define BOARD_TOUCHSCREEN_I2C_BUS	2	/* I2C1 */
 #define BOARD_TOUCHSCREEN_I2C_ADDR	0x4a
 
+#define PEPPY_BOARD_VERSION_PROTO	0
+#define PEPPY_BOARD_VERSION_EVT		1
+
 #endif
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c
index bfa1681..c213b10 100644
--- a/src/mainboard/google/peppy/romstage.c
+++ b/src/mainboard/google/peppy/romstage.c
@@ -25,11 +25,13 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include "cpu/intel/haswell/haswell.h"
+#include "ec/google/chromeec/ec.h"
 #include "northbridge/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/pch.h"
 #include "southbridge/intel/lynxpoint/lp_gpio.h"
 #include "gpio.h"
+#include "onboard.h"
 
 const struct rcba_config_instruction rcba_config[] = {
 
@@ -83,6 +85,25 @@ static void copy_spd(struct pei_data *peid)
 	if (!spd_file)
 		die("SPD data not found.");
 
+	switch (google_chromeec_get_board_version()) {
+	case PEPPY_BOARD_VERSION_PROTO:
+		/* Index 0 is 2GB config with CH0 only. */
+		if (spd_index == 0)
+			peid->dimm_channel1_disabled = 3;
+		break;
+
+	case PEPPY_BOARD_VERSION_EVT:
+	default:
+		/* Index 0-2 are 4GB config with both CH0 and CH1.
+		 * Index 4-6 are 2GB config with CH0 only. */
+		if (spd_index > 3)
+		{
+			peid->dimm_channel1_disabled = 3;
+			spd_index &= 0x03;
+		}
+		break;
+	}
+
 	if (ntohl(spd_file->len) <
 	    ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
@@ -92,11 +113,6 @@ static void copy_spd(struct pei_data *peid)
 	if (spd_file->len < sizeof(peid->spd_data[0]))
 		die("Missing SPD data.");
 
-	/* Index 0-2 are 4GB config with both CH0 and CH1
-	 * Index 4-6 are 2GB config with CH0 only */
-	if (spd_index > 3)
-		peid->dimm_channel1_disabled = 3;
-
 	memcpy(peid->spd_data[0],
 	       ((char*)CBFS_SUBHEADER(spd_file)) +
 	       spd_index * sizeof(peid->spd_data[0]),



More information about the coreboot-gerrit mailing list