[coreboot-gerrit] New patch to review for coreboot: c69df0f lynxpoint: provide gpio_is_native()

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Tue Dec 3 21:20:34 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4324

-gerrit

commit c69df0f26755c1b2ddfcf08a12079c9c9ffd1b73
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Jun 21 13:37:23 2013 -0500

    lynxpoint: provide gpio_is_native()
    
    There's a need to determine if a specific gpio pin is
    is set up to be a native function or not. Implement this.
    
    Change-Id: I91d57a549e0f4fddc0b1849e5f74320fc839642c
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59589
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/lynxpoint/gpio.c    | 19 +++++++++++++++++++
 src/southbridge/intel/lynxpoint/lp_gpio.c |  7 +++++++
 src/southbridge/intel/lynxpoint/pch.h     |  2 ++
 3 files changed, 28 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c
index 147a1c0..c6d6a15 100644
--- a/src/southbridge/intel/lynxpoint/gpio.c
+++ b/src/southbridge/intel/lynxpoint/gpio.c
@@ -128,3 +128,22 @@ void set_gpio(int gpio_num, int value)
 	config |= value << bit;
 	outl(config, gpio_base + gpio_reg_offsets[index]);
 }
+
+int gpio_is_native(int gpio_num)
+{
+	static const int gpio_reg_offsets[] = {
+		GPIO_USE_SEL, GPIO_USE_SEL2, GPIO_USE_SEL3
+	};
+	u16 gpio_base = get_gpio_base();
+	int index, bit;
+	u32 config;
+
+	if (gpio_num > MAX_GPIO_NUMBER)
+		return 0; /* Just ignore wrong gpio numbers. */
+
+	index = gpio_num / 32;
+	bit = gpio_num % 32;
+
+	config = inl(gpio_base + gpio_reg_offsets[index]);
+	return !(config & (1 << bit));
+}
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index 7d1a28d..cb052b2 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -159,3 +159,10 @@ void set_gpio(int gpio_num, int value)
 	conf0 |= value << GPO_LEVEL_SHIFT;
 	outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num));
 }
+
+int gpio_is_native(int gpio_num)
+{
+	u16 gpio_base = get_gpio_base();
+
+	return !(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & 1);
+}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index d1fbbe7..8ef7918 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -201,6 +201,8 @@ unsigned get_gpios(const int *gpio_num_array);
  * set GPIO pin value
  */
 void set_gpio(int gpio_num, int value);
+/* Return non-zero if gpio is set to native function. 0 otherwise. */
+int gpio_is_native(int gpio_num);
 #endif
 
 #define MAINBOARD_POWER_OFF	0



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