[coreboot-gerrit] Patch merged into coreboot/master: 24c773c lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 24c773c6e93965886eb0491b7a1b38c8b5a2aeec
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Jun 19 10:49:29 2013 -0700

    lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
    
    LynxPoint-LP has a lot of GPEs and the "default" set has been
    moved to register 4 starting at bit offset 96.  This means
    that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP
    but still bit 13 in LPT-H.
    
    suspend on falco and wake from usb
    
    4 | 2013-06-19 10:49:17 | ACPI Enter | S3
    5 | 2013-06-19 10:49:22 | ACPI Wake | S3
    6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0
    
    Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59265
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/4253 for details.

-gerrit