[coreboot-gerrit] Patch set updated for coreboot: 24c773c lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Mon Dec 2 22:12:17 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4253

-gerrit

commit 24c773c6e93965886eb0491b7a1b38c8b5a2aeec
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Jun 19 10:49:29 2013 -0700

    lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
    
    LynxPoint-LP has a lot of GPEs and the "default" set has been
    moved to register 4 starting at bit offset 96.  This means
    that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP
    but still bit 13 in LPT-H.
    
    suspend on falco and wake from usb
    
    4 | 2013-06-19 10:49:17 | ACPI Enter | S3
    5 | 2013-06-19 10:49:22 | ACPI Wake | S3
    6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0
    
    Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59265
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/lynxpoint/acpi/audio.asl | 15 ++++++++++-----
 src/southbridge/intel/lynxpoint/acpi/usb.asl   | 22 ++++++++++++++++++++--
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl
index a455328..2bc1168 100644
--- a/src/southbridge/intel/lynxpoint/acpi/audio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl
@@ -27,10 +27,15 @@ Device (HDEF)
 {
 	Name (_ADR, 0x001b0000)
 
-	// Power Resources for Wake
-	Name (_PRW, Package(){
-		13,  // Bit 13 of GPE
-		 4   // Can wake from S4 state.
-	})
+	Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
+	Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
+
+	Method (_PRW, 0) { // Power Resources for Wake
+		If (\ISLP ()) {
+			Return (PRWL)
+		} Else {
+			Return (PRWH)
+		}
+	}
 }
 
diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl
index 5c1f6a5..6583cb3 100644
--- a/src/southbridge/intel/lynxpoint/acpi/usb.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl
@@ -27,7 +27,16 @@ Device (EHCI)
 {
 	Name(_ADR, 0x001d0000)
 
-	Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
+	Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
+	Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
+
+	Method (_PRW, 0) { // Power Resources for Wake
+		If (\ISLP ()) {
+			Return (PRWL)
+		} Else {
+			Return (PRWH)
+		}
+	}
 
 	// Leave USB ports on for to allow Wake from USB
 
@@ -61,7 +70,16 @@ Device (XHCI)
 {
 	Name(_ADR, 0x00140000)
 
-	Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
+	Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
+	Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
+
+	Method (_PRW, 0) { // Power Resources for Wake
+		If (\ISLP ()) {
+			Return (PRWL)
+		} Else {
+			Return (PRWH)
+		}
+	}
 
 	// Leave USB ports on for to allow Wake from USB
 



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