[coreboot-gerrit] New patch to review for coreboot: 33e21f6 Revert "intel/i945: Use MMCONF_SUPPORT_DEFAULT"
Gerd Hoffmann (kraxel@redhat.com)
gerrit at coreboot.org
Fri Aug 2 09:43:52 CEST 2013
Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3845
-gerrit
commit 33e21f68d713f325a2c24661cae946c05f7570f7
Author: Gerd Hoffmann <kraxel at redhat.com>
Date: Fri Aug 2 09:40:35 2013 +0200
Revert "intel/i945: Use MMCONF_SUPPORT_DEFAULT"
This reverts commit 032c23db08e6f0c6a2937092edafa26339aa4921.
Lenovo T60 is broken in master. Bisected down to this patch.
Reverting it unbreaks T60 support.
Change-Id: Ie58f5f8d390775cbc031205f95308a86d9695b1c
Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
src/mainboard/getac/p470/Kconfig | 1 +
src/mainboard/ibase/mb899/Kconfig | 1 +
src/mainboard/intel/d945gclf/Kconfig | 1 +
src/mainboard/kontron/986lcd-m/Kconfig | 1 +
src/mainboard/lenovo/t60/Kconfig | 1 +
src/mainboard/lenovo/x60/Kconfig | 1 +
src/mainboard/roda/rk886ex/Kconfig | 1 +
src/northbridge/intel/i945/Kconfig | 6 ------
src/northbridge/intel/i945/bootblock.c | 24 ------------------------
src/northbridge/intel/i945/early_init.c | 1 +
10 files changed, 8 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig
index 3fdf6f7..e7f3c95 100644
--- a/src/mainboard/getac/p470/Kconfig
+++ b/src/mainboard/getac/p470/Kconfig
@@ -36,6 +36,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_SLIC
+ select MMCONF_SUPPORT
select UDELAY_LAPIC
select BOARD_ROMSIZE_KB_1024
select GFXUMA
diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index 36353b3..6b3bdfa 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
+ select MMCONF_SUPPORT
select BOARD_ROMSIZE_KB_512
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 0a9de1a..cc9ceb5 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
+ select MMCONF_SUPPORT
select BOARD_ROMSIZE_KB_512
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig
index e8b7225..0dd28da 100644
--- a/src/mainboard/kontron/986lcd-m/Kconfig
+++ b/src/mainboard/kontron/986lcd-m/Kconfig
@@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
+ select MMCONF_SUPPORT
select BOARD_ROMSIZE_KB_1024
select GFXUMA
select CHANNEL_XOR_RANDOMIZATION
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
index e5d17b8..1ea0e96 100644
--- a/src/mainboard/lenovo/t60/Kconfig
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
+ select MMCONF_SUPPORT
select GFXUMA
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index 1a765fb..fdd9e20 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
+ select MMCONF_SUPPORT
select GFXUMA
select BOARD_ROMSIZE_KB_2048
select CHANNEL_XOR_RANDOMIZATION
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 2113deb..84a8543 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
+ select MMCONF_SUPPORT
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select BOARD_ROMSIZE_KB_1024
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 135cbe3..fbc9988 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -24,8 +24,6 @@ if NORTHBRIDGE_INTEL_I945
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
- select MMCONF_SUPPORT
- select MMCONF_SUPPORT_DEFAULT
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
@@ -34,10 +32,6 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
def_bool n
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/intel/i945/bootblock.c"
-
config VGA_BIOS_ID
string
default "8086,27a2"
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
deleted file mode 100644
index 4571446..0000000
--- a/src/northbridge/intel/i945/bootblock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-#include <arch/io.h>
-
-/* Just re-define this instead of including i945.h. It blows up romcc. */
-#define PCIEXBAR 0x48
-
-static void bootblock_northbridge_init(void)
-{
- uint32_t reg;
-
- /*
- * The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
- * to true. That way all subsequent non-explicit config accesses use
- * MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final
- * assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
- *
- * The PCIEXBAR is assumed to live in the memory mapped IO space under
- * 4GiB.
- */
- reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
-}
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 946f7aa..435d64d 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -172,6 +172,7 @@ static void i945_setup_bars(void)
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
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