[coreboot-gerrit] New patch to review for coreboot: 487572a AMD Kabini: Fix MMCONF_SUPPORT_DEFAULT for ramstage

Bruce Griffith (Bruce.Griffith@se-eng.com) gerrit at coreboot.org
Thu Aug 1 14:56:26 CEST 2013

Bruce Griffith (Bruce.Griffith at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3838


commit 487572a2fed37b69d3d189d3db18f916742ebf81
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Jul 3 09:44:28 2013 +0300

    AMD Kabini: Fix MMCONF_SUPPORT_DEFAULT for ramstage
    Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
    MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.
    The implementation of pci_default_config() always returned with
    pci_cf8_conf1. This means any PCI configuration access that did
    not target bus 0 used PCI IO config operations, if PCI MMIO config
    was not explicitly requested.
    Change-Id: I43e08afb83d61aae5f130e54cefa99279bfe5342
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-by: Marc Jones <marc.jones at se-eng.com>
    Reviewed-by: Aaron Durbin <adurbin at google.com>
 src/northbridge/amd/agesa/family16kb/northbridge.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 19886ef..c27a1b2 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -855,12 +855,7 @@ static struct device_operations pci_domain_ops = {
 	.enable_resources = domain_enable_resources,
 	.init		  = NULL,
 	.scan_bus	  = pci_domain_scan_bus,
-	.ops_pci_bus	  = &pci_ops_mmconf,
-	.ops_pci_bus	  = &pci_cf8_conf1,
+	.ops_pci_bus	  = pci_bus_default_ops,
 static void sysconf_init(device_t dev) // first node

More information about the coreboot-gerrit mailing list