[coreboot-gerrit] New patch to review for coreboot: 03a52d8 armv7: add wrapper for tlbimvaa
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Tue Apr 30 21:25:20 CEST 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3161
-gerrit
commit 03a52d8d2c747b62b262152dff01cd50ecff6b50
Author: David Hendricks <dhendrix at chromium.org>
Date: Tue Apr 30 12:20:53 2013 -0700
armv7: add wrapper for tlbimvaa
This adds an inline wrapper for the TLBIMVAA instruction (invalidate
unified TLB by MVA, all address space identifiers).
Change-Id: Ibcd289ecedaba8586ade26e36c177ff1fcaf91d3
Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
src/arch/armv7/include/arch/cache.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index 1db86dc..028cf18 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -108,6 +108,12 @@ static inline void tlbiall(void)
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
}
+/* invalidate unified TLB by MVA, all ASID */
+static inline void tlbimvaa(unsigned long mva)
+{
+ asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
+}
+
/* write data access control register (DACR) */
static inline void write_dacr(uint32_t val)
{
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