[coreboot-gerrit] New patch to review for coreboot: 3bb4361 arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.

[Hung-Te Lin (hungte@chromium.org)]

Hung-Te Lin (hungte at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3128

-gerrit

commit 3bb4361674863c3343b59db56f8793468b269da3
Author: Hung-Te Lin <hungte at chromium.org>
Date:   Thu Apr 25 16:14:19 2013 +0800

    arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.
    
    To support suspend/resume, PHY control must be reseted only on normal boot
    path.  This commit adds a new param "mem_reset" to specify that.
    
    Verified to boot successfully on Google/Snow.
    
    Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33
    Signed-off-by: Hung-Te Lin <hungte at chromium.org>
---
 src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 14 ++++++++++----
 src/cpu/samsung/exynos5250/setup.h         |  4 +++-
 src/mainboard/google/snow/romstage.c       |  2 +-
 3 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index 5bb8a37..132471d 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -61,7 +61,8 @@ static void reset_phy_ctrl(void)
 	udelay(500);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int mem_reset)
 {
 	unsigned int val;
 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
@@ -71,9 +72,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 	phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
 	phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
 	dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
-	printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: ");
-	reset_phy_ctrl();
-	printk(BIOS_SPEW, "done\n");
+
+	if (mem_reset) {
+		printk(BIOS_SPEW, "%s: reset phy: ", __func__);
+		reset_phy_ctrl();
+		printk(BIOS_SPEW, "done\n");
+	} else {
+		printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__);
+	}
 
 	/* Set Impedance Output Driver */
 	printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n");
diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h
index 4f7f58c..952c125 100644
--- a/src/cpu/samsung/exynos5250/setup.h
+++ b/src/cpu/samsung/exynos5250/setup.h
@@ -702,9 +702,11 @@ void mem_ctrl_init(void);
  *			which the DMC uses to decide how to split a memory
  *			chunk into smaller chunks to support concurrent
  *			accesses; may vary across boards.
+ * @param mem_reset	Reset memory when initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int mem_reset);
 
 void tzpc_init(void);
 /*
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 41b88e1..edbe009 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -184,7 +184,7 @@ void main(void)
 		mem->mpll_mdiv,
 		mem->frequency_mhz);
 
-	ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
+	ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1);
 	if (ret) {
 		printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
 		ret);