[coreboot-gerrit] Patch set updated for coreboot: 8f53695 google/snow: disable unused USB3.0 PLL to save power

David Hendricks (dhendrix@chromium.org) gerrit at coreboot.org
Fri Apr 19 20:18:52 CEST 2013


David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3109

-gerrit

commit 8f53695a6c1e7555eb878bc9113af0fe2beaadf2
Author: David Hendricks <dhendrix at chromium.org>
Date:   Thu Apr 18 13:46:00 2013 -0700

    google/snow: disable unused USB3.0 PLL to save power
    
    This PLL is unused and can be disabled to save about 250mW.
    
    Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/mainboard/google/snow/ramstage.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 1cd84e8..54d13d3 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -198,6 +198,16 @@ static struct video_info snow_dp_video_info = {
 #define EXYNOS5250_DP1_BASE	0x145b0000
 #define SNOW_MAX_DP_TRIES	5
 
+/*
+ * This function disables the USB3.0 PLL to save power
+ */
+static void disable_usb30_pll(void)
+{
+	enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11;
+
+	gpio_direction_output(usb3_pll_l, 0);
+}
+
 /* this happens after cpu_init where exynos resources are set */
 static void mainboard_init(device_t dev)
 {
@@ -215,6 +225,9 @@ static void mainboard_init(device_t dev)
 	/* Clock Gating all the unused IP's to save power */
 	clock_gate();
 
+	/* Disable USB3.0 PLL to save 250mW of power */
+	disable_usb30_pll();
+
 	snow_lcd_vdd();
 	do {
 		udelay(50);



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