[coreboot-gerrit] Patch merged into coreboot/master: 7f23aeb AMD Thatcher: Fix PCIE link issues

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7f23aeb05d57d4989783b35afce0017d3772fde6
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Tue Apr 2 10:49:09 2013 +0800

    AMD Thatcher: Fix PCIE link issues
    
    1). Thatcher PCIE x8 slot is reverse order.
    Although the PCIE slot is x16, it actually uses 8 lanes(15:8).
    Because the PCIE slot is configured by PortList[0], fix this item can enable the slot.
    A x1 PCIE network adapter works well in this slot.
    
    2). Fix DdiList to detect DP monitor or HDMI monitor.
    GPIO50 can be used to detect DP0/HDMI0 monitor.
    If GPIO50 is 1, it is DP monitor. If GPIO50 is 0, it is HDMI monitor.
    GPIO51 can be used to detect DP1/HDMI1 in the same way.
    
    3). Disable unused PCIE port and clean up code in PlatformGnbPcie.c and devicetree.cb.
    PCIE port 3 and 7 are not used in Thatcher.
    
    Change-Id: I8524b6fc1b6cdc03ba92e7191186bfb0986767c8
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
    Reviewed-on: http://review.coreboot.org/3011
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth at se-eng.com>

Build-Tested: build bot (Jenkins) at Mon Apr  8 09:39:16 2013, giving +1
Reviewed-By: Martin Roth <martin.roth at se-eng.com> at Fri Apr 12 05:59:52 2013, giving +2
See http://review.coreboot.org/3011 for details.

-gerrit