[coreboot-gerrit] Patch set updated for coreboot: cb32b84 GOOGLE/SNOW: add edp support to ramstage
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Wed Apr 10 03:06:55 CEST 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3055
-gerrit
commit cb32b844323dfadbd68e3374dfe65247f13553b7
Author: Ronald G. Minnich <rminnich at gmail.com>
Date: Tue Apr 9 14:39:34 2013 -0700
GOOGLE/SNOW: add edp support to ramstage
Add basic edp support to the ramstage. Not working.
Change-Id: I15086e03417edca7426c214e67b51719d8ed9341
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
src/cpu/samsung/exynos5-common/s5p-dp-core.h | 1 +
src/mainboard/google/snow/Kconfig | 1 +
src/mainboard/google/snow/ramstage.c | 178 ++++++++++++++++++++++++++-
3 files changed, 177 insertions(+), 3 deletions(-)
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
index 67c1990..2988d5d 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h
+++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
@@ -250,6 +250,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
/* startup and init */
+struct exynos5_fimd_panel;
void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms);
int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);
diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig
index 85b90a5..f070056 100644
--- a/src/mainboard/google/snow/Kconfig
+++ b/src/mainboard/google/snow/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# select MMCONF_SUPPORT
select EXYNOS_DISPLAYPORT
select CHROMEOS
+ select DRIVER_TI_TPS65090
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 9081629..9d6b168 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -18,13 +18,22 @@
*/
#include <console/console.h>
+#include <device/device.h>
+#include <device/i2c.h>
+#include <drivers/ti/tps65090/tps65090.h>
#include <cbmem.h>
+#include <delay.h>
+#include <arch/cache.h>
#include <arch/exception.h>
+#include <arch/gpio.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
+#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/power.h>
-#include <arch/cache.h>
+#include <cpu/samsung/exynos5-common/i2c.h>
+#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
+
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
@@ -35,7 +44,8 @@ void hardwaremain(int boot_complete);
void main(void)
{
console_init();
- printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n");
+ printk(BIOS_INFO,
+ "hello from ramstage; now with deluxe exception handling.\n");
/* set up coreboot tables */
high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
@@ -54,7 +64,8 @@ void main(void)
dcache_invalidate_all();
dcache_mmu_enable();
- /* this is going to move, but we must have it now and we're not sure where */
+ /* this is going to move, but we must have it now and we're
+ * not sure where */
exception_init();
const unsigned epll_hz = 192000000;
@@ -68,3 +79,164 @@ void main(void)
hardwaremain(0);
}
+
+/* TODO: transplanted DP stuff, clean up once we have something that works */
+static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */
+static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */
+static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */
+
+static void exynos_dp_bridge_setup(void)
+{
+ exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
+
+ gpio_set_value(dp_pd_l, 1);
+ gpio_cfg_pin(dp_pd_l, EXYNOS_GPIO_OUTPUT);
+ gpio_set_pull(dp_pd_l, EXYNOS_GPIO_PULL_NONE);
+
+ gpio_set_value(dp_rst_l, 0);
+ gpio_cfg_pin(dp_rst_l, EXYNOS_GPIO_OUTPUT);
+ gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE);
+ udelay(10);
+ gpio_set_value(dp_rst_l, 1);
+
+ udelay(90000); /* FIXME: this might be unnecessary */
+}
+
+static void exynos_dp_bridge_init(void)
+{
+ /* De-assert PD (and possibly RST) to power up the bridge */
+ gpio_set_value(dp_pd_l, 1);
+ gpio_set_value(dp_rst_l, 1);
+
+ /*
+ * We need to wait for 90ms after bringing up the bridge since
+ * there is a phantom "high" on the HPD chip during its
+ * bootup. The phantom high comes within 7ms of de-asserting
+ * PD and persists for at least 15ms. The real high comes
+ * roughly 50ms after PD is de-asserted. The phantom high
+ * makes it hard for us to know when the NXP chip is up.
+ */
+ udelay(90000); /* FIXME: this might be unnecessary */
+}
+
+static int exynos_dp_hotplug(void)
+{
+ /* Check HPD. If it's high, we're all good. */
+ if (gpio_get_value(dp_hpd))
+ return 0;
+ return -1;
+}
+
+static void exynos_dp_reset(void)
+{
+ gpio_set_value(dp_pd_l, 0);
+ gpio_set_value(dp_rst_l, 0);
+ /* paranoid delay period (300ms) */
+ udelay(300 * 1000);
+}
+
+#define LCD_T5_DELAY_MS 10
+#define LCD_T6_DELAY_MS 10
+
+static void snow_backlight_pwm(void)
+{
+ /*Configure backlight PWM as a simple output high (100% brightness) */
+ gpio_direction_output(GPIO_B20, 1);
+ udelay(LCD_T6_DELAY_MS * 1000);
+}
+
+static void snow_backlight_en(void)
+{
+ /* * Configure GPIO for LCD_BL_EN */
+ gpio_direction_output(GPIO_X30, 1);
+}
+
+#define TPS69050_BUS 4 /* Snow-specific */
+
+#define FET1_CTRL 0x0f
+#define FET6_CTRL 0x14
+
+static void snow_lcd_vdd(void)
+{
+ /* Enable FET6, lcd panel */
+ tps65090_fet_enable(TPS69050_BUS, FET6_CTRL);
+}
+
+static void snow_backlight_vdd(void)
+{
+ /* Enable FET1, backlight */
+ tps65090_fet_enable(TPS69050_BUS, FET1_CTRL);
+ udelay(LCD_T5_DELAY_MS * 1000);
+}
+
+//static struct video_info smdk5250_dp_config = {
+static struct video_info snow_dp_video_info = {
+ /* FIXME: fix video_info struct to use const for name */
+ .name = (char *)"eDP-LVDS NXP PTN3460",
+
+ .h_sync_polarity = 0,
+ .v_sync_polarity = 0,
+ .interlaced = 0,
+
+ .color_space = COLOR_RGB,
+ .dynamic_range = VESA,
+ .ycbcr_coeff = COLOR_YCBCR601,
+ .color_depth = COLOR_8,
+
+ .link_rate = LINK_RATE_2_70GBPS,
+ .lane_count = LANE_COUNT2,
+};
+
+/* FIXME: move some place more appropriate */
+#define EXYNOS5250_DP1_BASE 0x145b0000
+#define SNOW_MAX_DP_TRIES 5
+
+/* this happens after cpu_init where exynos resources are set */
+static void mainboard_init(device_t dev)
+{
+ int dp_tries;
+ unsigned int wait_ms;
+ struct s5p_dp_device dp_device = {
+ .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
+ .video_info = &snow_dp_video_info,
+ };
+
+ i2c_init(TPS69050_BUS, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ snow_lcd_vdd();
+ exynos_dp_bridge_setup();
+ for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) {
+ if (wait_ms) {
+ udelay(wait_ms);
+ wait_ms = 0;
+ }
+
+ exynos_dp_bridge_init();
+ if (exynos_dp_hotplug()) {
+ exynos_dp_reset();
+ continue;
+ }
+
+ if (dp_controller_init(&dp_device, &wait_ms))
+ continue;
+
+ snow_backlight_vdd();
+ snow_backlight_pwm();
+ snow_backlight_en();
+ /* if we're here, we're successful */
+ break;
+ }
+
+ if (dp_tries > SNOW_MAX_DP_TRIES)
+ printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "Samsung/Google ARM Chromebook",
+ .enable_dev = mainboard_enable,
+};
More information about the coreboot-gerrit
mailing list