[coreboot-gerrit] New patch to review for coreboot: c4a0546 armv7: specify operational condition codes for msr instruction

David Hendricks (dhendrix@chromium.org) gerrit at coreboot.org
Mon Apr 8 02:51:37 CEST 2013

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3037


commit c4a05467636ba94ead652be9588e9c96c85aa2a4
Author: David Hendricks <dhendrix at chromium.org>
Date:   Sun Apr 7 17:26:34 2013 -0700

    armv7: specify operational condition codes for msr instruction
    This adds condition codes when using the msr instruction. Although
    described as "optional" in the Cortex-A series programmer's guide,
    our experience with using the msr instruction in the payload suggests
    that the condition code is not optional and that this only worked
    in coreboot (and u-boot) because the processor comes up in SVC32 mode.
    (credit to Gabe Black for finding this, I'm only uploading the patch)
    Signed-off-by: Gabe Black <gabeblack at chromium.org>
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b
 src/arch/armv7/bootblock.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
index c647834..faf5475 100644
--- a/src/arch/armv7/bootblock.inc
+++ b/src/arch/armv7/bootblock.inc
@@ -58,7 +58,7 @@ reset:
 	mrs	r0, cpsr
 	bic	r0, r0, #0x1f
 	orr	r0, r0, #0xd3
-	msr	cpsr,r0
+	msr	cpsr_cxsf,r0
 	 * From Cortex-A Series Programmer's Guide:

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