[coreboot-gerrit] Patch set updated for coreboot: 7a596e2 samsung/exynos5: init display port and LCD
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Fri Apr 5 21:46:32 CEST 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2931
-gerrit
commit 7a596e2c224bd30d181b8f8b0166281e091496da
Author: Ronald G. Minnich <rminnich at gmail.com>
Date: Mon Mar 18 09:49:54 2013 -0700
samsung/exynos5: init display port and LCD
This adds resources for the display port controller and attempts to
go thru the init sequence.
TODO: split this apart when we have something working...
Change-Id: I2caa350f8c0e681f71e9646898dcdb36e10115b2
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
src/cpu/samsung/exynos5-common/exynos-fb.c | 6 +-
src/cpu/samsung/exynos5-common/i2c.c | 10 +-
src/cpu/samsung/exynos5-common/s5p-dp-core.h | 1 +
src/cpu/samsung/exynos5250/Kconfig | 2 +-
src/cpu/samsung/exynos5250/chip.h | 40 ++++++
src/cpu/samsung/exynos5250/cpu.c | 81 +++++++++--
src/mainboard/google/snow/devicetree.cb | 23 +--
src/mainboard/google/snow/ramstage.c | 203 ++++++++++++++++++++++++++-
8 files changed, 338 insertions(+), 28 deletions(-)
diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c
index 30d0767..ea6c0f1 100644
--- a/src/cpu/samsung/exynos5-common/exynos-fb.c
+++ b/src/cpu/samsung/exynos5-common/exynos-fb.c
@@ -100,7 +100,7 @@ static void fimd_bypass(void)
{
struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
- /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/
+ setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);
sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1;
}
@@ -582,11 +582,9 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data,
{
int ret = 0;
- //vi->res = panel_info->vl_col;
- //vi->yres = panel_info->vl_row;
-
fimd_bypass();
fb_init(panel_info, lcdbase, panel_data);
+ printk(BIOS_SPEW, "fb_init(%p, %p, %p) done\n", panel_info, lcdbase, panel_data);
/* Enable flushing after LCD writes if requested */
// forget it. lcd_set_flush_dcache(1);
diff --git a/src/cpu/samsung/exynos5-common/i2c.c b/src/cpu/samsung/exynos5-common/i2c.c
index 7384b50..e09496d 100644
--- a/src/cpu/samsung/exynos5-common/i2c.c
+++ b/src/cpu/samsung/exynos5-common/i2c.c
@@ -93,6 +93,7 @@ void i2c_set_early_reg(unsigned int base)
g_early_i2c_config = (struct s3c24x0_i2c *)base;
}
+#include <console/console.h>
static struct s3c24x0_i2c_bus *get_bus(int bus_idx)
{
/* If an early i2c config exists we just use that */
@@ -105,7 +106,7 @@ static struct s3c24x0_i2c_bus *get_bus(int bus_idx)
if (bus_idx < i2c_busses)
return &i2c_bus[bus_idx];
- debug("Undefined bus: %d\n", bus_idx);
+ printk(BIOS_ERR, "Undefined bus: %d, busses: %d\n", bus_idx, i2c_busses);
return NULL;
}
@@ -233,6 +234,7 @@ int i2c_set_bus_num(unsigned int bus)
struct s3c24x0_i2c_bus *i2c;
i2c = get_bus(bus);
+ printk(BIOS_DEBUG, "%s: bus: %u, i2c: %p\n", __func__, bus, i2c);
if (!i2c)
return -1;
g_current_bus = bus;
@@ -522,17 +524,21 @@ int i2c_probe(unsigned char chip)
return ret != I2C_OK;
}
+#include <console/console.h> /* FIXME: remove this */
int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buffer, int len)
{
struct s3c24x0_i2c_bus *i2c;
unsigned char xaddr[4];
int ret;
+ printk(BIOS_DEBUG, "%s: entered, chip: 0x%02x, addr: 0x%02x\n",
+ __func__, chip, addr);
if (alen > 4) {
debug("I2C read: addr len %d not supported\n", alen);
return 1;
}
+ printk(BIOS_DEBUG, "%s: checkpoint 1\n", __func__);
if (alen > 0) {
xaddr[0] = (addr >> 24) & 0xFF;
xaddr[1] = (addr >> 16) & 0xFF;
@@ -559,8 +565,10 @@ int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buf
i2c = get_bus(g_current_bus);
if (!i2c)
return -1;
+ printk(BIOS_DEBUG, "%s: checkpoint 2\n", __func__);
ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen],
alen, buffer, len);
+ printk(BIOS_DEBUG, "%s: bus: %u, ret %d\n", __func__, i2c->bus_num, ret);
if (ret) {
debug("I2c read: failed %d\n", ret);
return 1;
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
index 67c1990..2988d5d 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h
+++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
@@ -250,6 +250,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
/* startup and init */
+struct exynos5_fimd_panel;
void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms);
int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index ca306b6..cc67abd 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -96,4 +96,4 @@ config SYS_TEXT_BASE
config COREBOOT_TABLES_SIZE
hex
- default 0x100000
+ default 0x4000000
diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h
new file mode 100644
index 0000000..798cd26
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/chip.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5250_H
+#define CPU_SAMSUNG_EXYNOS5250_H
+
+struct cpu_samsung_exynos5250_config {
+ /* special magic numbers! */
+ int clkval_f;
+ int upper_margin;
+ int lower_margin;
+ int vsync;
+ int left_margin;
+ int right_margin;
+ int hsync;
+
+ int xres;
+ int yres;
+ int bpp;
+
+ u32 lcdbase;
+};
+
+#endif /* CPU_SAMSUNG_EXYNOS5250_H */
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index 4bb06e8..0a85322 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -1,13 +1,77 @@
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <delay.h>
#include <console/console.h>
#include <device/device.h>
-#include <arch/cache.h>
-#include <cpu/samsung/exynos5250/cpu.h>
+#include <cbmem.h>
+#include <cpu/samsung/exynos5250/fimd.h>
+#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
+#include "chip.h"
+#include "cpu.h"
#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
+/* we distinguish a display port device from a raw graphics device because there are
+ * dramatic differences in startup depending on graphics usage. To make startup fast
+ * and easier to understand and debug we explicitly name this common case. The alternate
+ * approach, involving lots of machine and callbacks, is hard to debug and verify.
+ */
+static void exynos_displayport_init(device_t dev)
+{
+ int ret;
+ struct cpu_samsung_exynos5250_config *conf = dev->chip_info;
+ /* put these on the stack. If, at some point, we want to move this code to a
+ * pre-ram stage, it will be much easier.
+ */
+ vidinfo_t vi;
+ struct exynos5_fimd_panel panel;
+ unsigned long int fb_size;
+ u32 lcdbase;
+
+ printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf);
+ memset(&vi, 0, sizeof(vi));
+ memset(&panel, 0, sizeof(panel));
+
+ panel.is_dp = 1; /* Display I/F is eDP */
+ /* while it is true that we did a memset to zero,
+ * we leave some 'set to zero' entries here to make
+ * it clear what's going on. Graphics is confusing.
+ */
+ panel.is_mipi = 0;
+ panel.fixvclk = 0;
+ panel.ivclk = 0;
+ panel.clkval_f = conf->clkval_f;
+ panel.upper_margin = conf->upper_margin;
+ panel.lower_margin = conf->lower_margin;
+ panel.vsync = conf->vsync;
+ panel.left_margin = conf->left_margin;
+ panel.right_margin = conf->right_margin;
+ panel.hsync = conf->hsync;
+
+ vi.vl_col = conf->xres;
+ vi.vl_row = conf->yres;
+ vi.vl_bpix = conf->bpp;
+ /*
+ * The size is a magic number from hardware. Allocate enough for the
+ * frame buffer and color map.
+ */
+ fb_size = conf->xres * conf->yres * sizeof(unsigned long);
+ lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB);
+ printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase));
+ mmio_resource(dev, 0, lcdbase/KiB, 64);
+ vi.cmap = (void *)lcdbase;
+
+ lcdbase += 64*KiB;
+ mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB);
+ printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase);
+ ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase);
+}
+
static void cpu_init(device_t dev)
{
+ exynos_displayport_init(dev);
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
}
@@ -18,22 +82,19 @@ static void cpu_noop(device_t dev)
static struct device_operations cpu_ops = {
.read_resources = cpu_noop,
.set_resources = cpu_noop,
- .enable_resources = cpu_noop,
- .init = cpu_init,
+ .enable_resources = cpu_init,
+ .init = cpu_noop,
.scan_bus = 0,
};
-static void enable_dev(device_t dev)
+static void enable_exynos5250_dev(device_t dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_ops;
- }
+ dev->ops = &cpu_ops;
}
struct chip_operations cpu_samsung_exynos5250_ops = {
CHIP_NAME("CPU Samsung Exynos 5250")
- .enable_dev = enable_dev,
+ .enable_dev = enable_exynos5250_dev,
};
void exynos5250_config_l2_cache(void)
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index 4c88ea8..41ed45e 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -17,16 +17,17 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# FIXME: this is just a stub for now
chip cpu/samsung/exynos5250
-
-device cpu_cluster 0 on
-end
-
-device domain 0 on
- chip drivers/generic/generic # I2C0 controller
- device i2c 6 on end # ?
- device i2c 9 on end # ?
- end
-end
+ device cpu_cluster 0 on end
+ register "xres" = "1366"
+ register "yres" = "768"
+ register "bpp" = "16"
+ # complex magic timing!
+ register "clkval_f" = "2"
+ register "upper_margin" = "14"
+ register "lower_margin" = "3"
+ register "vsync" = "5"
+ register "left_margin" = "80"
+ register "right_margin" = "48"
+ register "hsync" = "32"
end
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 9081629..0618a86 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -18,13 +18,20 @@
*/
#include <console/console.h>
+#include <device/device.h>
+#include <device/i2c.h> /* FIXME: for backlight FET enable */
#include <cbmem.h>
+#include <delay.h>
+#include <arch/cache.h>
#include <arch/exception.h>
+#include <arch/gpio.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
+#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/power.h>
-#include <arch/cache.h>
+#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
+
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
@@ -68,3 +75,197 @@ void main(void)
hardwaremain(0);
}
+
+/* TODO: transplanted DP stuff, clean up once we have something that works */
+static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */
+static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */
+static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */
+
+static void exynos_dp_bridge_setup(void)
+{
+#if 0
+ if (fdt_gpio_isvalid(&local.dp_rst)) {
+ fdtdec_set_gpio(&local.dp_rst, 1);
+ gpio_cfg_pin(local.dp_rst.gpio, EXYNOS_GPIO_OUTPUT);
+ gpio_set_pull(local.dp_rst.gpio, EXYNOS_GPIO_PULL_NONE);
+ udelay(10);
+ fdtdec_set_gpio(&local.dp_rst, 0);
+ }
+#endif
+ exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
+
+ gpio_set_value(dp_pd_l, 1);
+ gpio_cfg_pin(dp_pd_l, EXYNOS_GPIO_OUTPUT);
+ gpio_set_pull(dp_pd_l, EXYNOS_GPIO_PULL_NONE);
+
+ gpio_set_value(dp_rst_l, 0);
+ gpio_cfg_pin(dp_rst_l, EXYNOS_GPIO_OUTPUT);
+ gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE);
+ udelay(10);
+ gpio_set_value(dp_rst_l, 1);
+
+ udelay(90000); /* FIXME: this might be unnecessary */
+}
+
+static void exynos_dp_bridge_init(void)
+{
+ /* De-assert PD (and possibly RST) to power up the bridge */
+ gpio_set_value(dp_pd_l, 1);
+ gpio_set_value(dp_rst_l, 1);
+
+ /*
+ * We need to wait for 90ms after bringing up the bridge since there
+ * is a phantom "high" on the HPD chip during its bootup. The phantom
+ * high comes within 7ms of de-asserting PD and persists for at least
+ * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
+ * phantom high makes it hard for us to know when the NXP chip is up.
+ */
+ udelay(90000); /* FIXME: this might be unnecessary */
+}
+
+static int exynos_dp_hotplug(void)
+{
+ /* Check HPD. If it's high, we're all good. */
+ if (gpio_get_value(dp_hpd))
+ return 0;
+ return -1;
+}
+
+static void exynos_dp_reset(void)
+{
+ gpio_set_value(dp_pd_l, 0);
+ gpio_set_value(dp_rst_l, 0);
+ /* paranoid delay period (300ms) */
+ udelay(300 * 1000);
+}
+
+#define LCD_T5_DELAY_MS 10
+#define LCD_T6_DELAY_MS 10
+
+static void snow_backlight_pwm(void)
+{
+ /*Configure backlight PWM as a simple output high (100% brightness) */
+ gpio_direction_output(GPIO_B20, 1);
+ udelay(LCD_T6_DELAY_MS * 1000);
+}
+
+static void snow_backlight_en(void)
+{
+ /* * Configure GPIO for LCD_BL_EN */
+ gpio_direction_output(GPIO_X30, 1);
+}
+
+#define TPS69050_BUS 4 /* Snow-specific */
+
+#define TPS69050_ADDR 0x48
+#define FET1_CTRL 0x0f
+#define FET6_CTRL 0x14
+
+static void snow_lcd_vdd(void)
+{
+ uint8_t val = 0xbb;
+ printk(BIOS_DEBUG, "%s: attempting to enable FET6\n", __func__);
+ i2c_set_bus_num(TPS69050_BUS);
+ i2c_read(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val));
+ printk(BIOS_DEBUG, "%s: FET6_CTRL before: 0x%02x\n", __func__, val);
+ val |= 1;
+ i2c_write(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val));
+
+ i2c_read(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val));
+ printk(BIOS_DEBUG, "%s: FET6_CTRL after: 0x%02x\n", __func__, val);
+// return board_ldo_enable(6); /* Enable FET6, lcd panel */
+}
+
+static void snow_backlight_vdd(void)
+{
+ uint8_t val = 0xbb;
+// return board_ldo_enable(1); /* Enable FET1, backlight */
+ /* FIXME: implement more paranoid tps65090EXYNOS5250_DP1_ADDR fet routine */
+// ret = tps65090_fet_enable(1);
+ printk(BIOS_DEBUG, "%s: attempting to enable FET1\n", __func__);
+ i2c_set_bus_num(TPS69050_BUS);
+ i2c_read(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val));
+ printk(BIOS_DEBUG, "%s: FET1_CTRL before: 0x%02x\n", __func__, val);
+ val |= 1;
+ i2c_write(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val));
+ udelay(LCD_T5_DELAY_MS * 1000);
+
+ i2c_read(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val));
+ printk(BIOS_DEBUG, "%s: FET1_CTRL after: 0x%02x\n", __func__, val);
+}
+
+//static struct video_info smdk5250_dp_config = {
+static struct video_info snow_dp_video_info = {
+ /* FIXME: fix video_info struct to use const for name */
+ .name = (char *)"eDP-LVDS NXP PTN3460",
+
+ .h_sync_polarity = 0,
+ .v_sync_polarity = 0,
+ .interlaced = 0,
+
+ .color_space = COLOR_RGB,
+ .dynamic_range = VESA,
+ .ycbcr_coeff = COLOR_YCBCR601,
+ .color_depth = COLOR_8,
+
+ .link_rate = LINK_RATE_2_70GBPS,
+ .lane_count = LANE_COUNT2,
+};
+
+/* FIXME: move some place more appropriate */
+#define EXYNOS5250_DP1_BASE 0x145b0000
+#define SNOW_MAX_DP_TRIES 5
+
+static void mainboard_init(device_t dev)
+{
+ int dp_tries;
+ unsigned int wait_ms;
+ struct s5p_dp_device dp_device = {
+ .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
+ .video_info = &snow_dp_video_info,
+ };
+
+ /* this happens after cpu_init where exynos resources are set */
+ /* Set the i2c register address base so i2c works before FDT */
+
+ /* FIXME: fix the braindead i2c crap leftover from u-boot */
+ i2c_set_early_reg(0x12ca0000);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ snow_lcd_vdd();
+ exynos_dp_bridge_setup();
+ for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) {
+ if (wait_ms) {
+ udelay(wait_ms);
+ wait_ms = 0;
+ }
+
+ exynos_dp_bridge_init();
+ if (exynos_dp_hotplug()) {
+ exynos_dp_reset();
+ continue;
+ }
+
+ if (dp_controller_init(&dp_device, &wait_ms))
+ continue;
+
+ snow_backlight_vdd();
+ snow_backlight_pwm();
+ snow_backlight_en();
+ /* if we're here, we're successful */
+ break;
+ }
+
+ if (dp_tries > SNOW_MAX_DP_TRIES)
+ printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "Samsung/Google ARM Chromebook",
+ .enable_dev = mainboard_enable,
+};
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