[coreboot-gerrit] New patch to review for coreboot: f79f561 i945: Make it compile with CONFIG_DYNAMIC_CBMEM=y

[Denis Carikli (GNUtoo@no-log.org)]

Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3023

-gerrit

commit f79f561c1e91ab44ca89f654871684dc6ca77a87
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Thu Apr 4 22:57:07 2013 +0200

    i945: Make it compile with CONFIG_DYNAMIC_CBMEM=y
    
    The get_top_of_ram function was adapted from the
      same function in raminit.c in the same directory.
    
    Change-Id: I4ee6b2a5f44860f51b96aa506398a516930d14f4
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
 src/northbridge/intel/i945/northbridge.c | 47 ++++++++++++++++++++++++++++++++
 src/northbridge/intel/i945/raminit.c     |  7 +++++
 2 files changed, 54 insertions(+)

diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 9d97f0c..9e6896a 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -29,8 +29,53 @@
 #include <cbmem.h>
 #include <cpu/cpu.h>
 #include <arch/acpi.h>
+#include "raminit.h"
 #include "i945.h"
 
+#if CONFIG_DYNAMIC_CBMEM
+
+unsigned long get_top_of_ram(void)
+{
+        u32 tom;
+	device_t dev0, dev2;
+
+	dev0 = dev_find_slot(0, PCI_DEVFN(0, 0));
+	dev2 = dev_find_slot(0, PCI_DEVFN(2, 0));
+
+        if (pci_read_config8(dev0, DEVEN) & ((1 << 4) | (1 << 3))) {
+                /* IGD enabled, get top of Memory from BSM register */
+                tom = pci_read_config32(dev2, 0x5c);
+        } else {
+                tom = (pci_read_config8(dev0, TOLUD) & 0xf7) << 24;
+        }
+
+        /* if TSEG enabled subtract size */
+        switch(pci_read_config8(dev0, ESMRAM)) {
+        case 0x01:
+                /* 1MB TSEG */
+                tom -= 0x10000;
+                break;
+        case 0x03:
+                /* 2MB TSEG */
+                tom -= 0x20000;
+                break;
+        case 0x05:
+                /* 8MB TSEG */
+                tom -= 0x80000;
+                break;
+        default:
+                /* TSEG either disabled or invalid */
+                break;
+        }
+        return (unsigned long) tom;
+}
+
+void *cbmem_top(void)
+{
+        return (void *)get_top_of_ram();
+}
+#endif
+
 static int get_pcie_bar(u32 *base, u32 *len)
 {
 	device_t dev;
@@ -88,6 +133,8 @@ static void pci_domain_set_resources(device_t dev)
 	uint16_t reg16;
 	unsigned long long tomk, tomk_stolen;
 	uint64_t tseg_memory_base = 0, tseg_memory_size = 0;
+	extern uint64_t high_tables_base;
+	extern uint64_t high_tables_size;
 
 	/* Can we find out how much memory we can use at most
 	 * this way?
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b1a0684..e2137d8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -28,10 +28,17 @@
 #include "i945.h"
 #include <cbmem.h>
 
+#if CONFIG_DYNAMIC_CBMEM
+void *cbmem_top(void)
+{
+        return (void *)get_top_of_ram();
+}
+#else
 struct cbmem_entry *get_cbmem_toc(void)
 {
 	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
 }
+#endif
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP