[coreboot-gerrit] Patch set updated for coreboot: e14fe8d mtrr: add rom caching comment about hyperthreads
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Wed Apr 3 19:29:56 CEST 2013
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3018
-gerrit
commit e14fe8da5ae27c752c7dcb0b27793e0864e54d96
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Apr 3 09:57:53 2013 -0500
mtrr: add rom caching comment about hyperthreads
Explicitly call out the effects of hyperthreads running the
MTRR code and its impact on the enablement of ROM caching.
Change-Id: I14b8f3fdc112340b8f483f2e554c5680576a8a7c
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/include/cpu/x86/mtrr.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 15a5cad..38c3f7c 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -74,7 +74,11 @@ int x86_mtrr_check(void);
/* ROM caching can be used after variable MTRRs are set up. Beware that
* enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on
* one's IO hole size and WRCOMB resources. Be sure to check the console
- * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. */
+ * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that
+ * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the
+ * rom caching will be disabled if all threads run the MTRR code. Therefore,
+ * one needs to call x86_mtrr_enable_rom_caching() after all threads of the
+ * same core have run the MTRR code. */
#if CONFIG_CACHE_ROM
void x86_mtrr_enable_rom_caching(void);
void x86_mtrr_disable_rom_caching(void);
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