[coreboot-gerrit] Patch merged into coreboot/master: 13cc952 haswell: keep ROM cache enabled

gerrit at coreboot.org gerrit at coreboot.org
Wed Apr 3 19:25:44 CEST 2013

the following patch was just integrated into master:
commit 13cc952a13ea29d9c5016a861d97da8326c87c4e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Apr 1 16:49:31 2013 -0500

    haswell: keep ROM cache enabled
    The MP code on haswell was mirroring the BSPs MTRRs. In addition it
    was cleaning up the ROM cache so that the MTRR register values were
    the same once the OS was booted. Since the hyperthread sibling of
    the BSP was going through this path the ROM cache was getting torn
    down once the hyperthread was brought up.
    That said, there was no differnce in observed boot time keeping the
    ROM cache enabled.
    Change-Id: I2a59988fcfeea9291202c961636ea761c2538837
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/3008
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Wed Apr  3 18:04:58 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Apr  3 19:25:41 2013, giving +2
See http://review.coreboot.org/3008 for details.


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