[coreboot-gerrit] New patch to review for coreboot: dfd02e5 haswell: enable ROM caching

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Wed Apr 3 17:00:06 CEST 2013

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3016


commit dfd02e5d90a03f711063f1dc67be1531fbe518e4
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Apr 3 09:55:22 2013 -0500

    haswell: enable ROM caching
    If ROM caching is selected the haswell CPU initialization code
    will enable ROM caching after all other CPU threads are brought
    Change-Id: I75424bb75174bfeca001468c3272e6375e925122
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
 src/cpu/intel/haswell/haswell_init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 0bb11a8..18636b0 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -551,6 +551,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
 	/* After SMM relocation a 2nd microcode load is required. */
+	/* Enable ROM caching if option was selected. */
+	x86_mtrr_enable_rom_caching();
 static struct device_operations cpu_dev_ops = {

More information about the coreboot-gerrit mailing list