Re: IRQ routing: how to do the mainboard_picr_data/_intr_data structures?
by Mike Banon
Thank you very much for your advice, dear Naresh, I will try matching
the UEFI routing.
Dear Elyes, huge thanks to you for telling me about "getpir" utility -
never heard about it before!
> this old "getpir" utility may help you ;)
> You may have to run:
> coreboot/util$ git revert 6c90f3334e65ff4b0ff4900df77bc33d53beb677
What I already discovered:
*) To activate the irq_tables.c / intel_irq_routing_table code, I need
to enable CONFIG_HAVE_PIRQ_TABLE and CONFIG_GENERATE_PIRQ_TABLE. But I
don't see it having any visible effect on the IRQ routing: instead,
maybe this intel_irq_routing_table is supposed to be a reflection of
this routing?
*) By adding to mainboard.c / mainboard_pirq_data structure these lines
{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /*
x4 PCIe: 02.3 */ /* 0:04.00 / 2:00.00 - IRQ 3 */
{NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /*
x4 PCIe: 02.4 */ /* 0:05.00 / 3:00.00 - IRQ 3 */
I got the interrupts assigned to Ethernet 2:00.00 and WiFi 3:00.00
devices, which are behind the 0:04.00 and 0:05.00 bridges
respectively. And this assignment is even visible by KolibriOS now!
But I don't know if it's normal that a lot of devices are sharing the
same IRQ 3 now, is it bad?
*) For a moment I thought that only _pirq_data structure matters, and
set the contains of picr_data/_intr_data to all 0x1F to check this
though. But a laptop can't boot with such a change ;-)
What I have trouble understanding:
what is the relationship between mainboard_picr_data/_intr_data,
_pirq_data, and intel_irq_routing_table?
If I got the intel_irq_routing_table with getpir - how to convert its'
contents to these other tables so that they match each other?
Best regards,
Mike Banon
On Tue, Nov 10, 2020 at 5:52 PM Naresh G. Solanki
<naresh.solanki.2011(a)gmail.com> wrote:
>
> Hi Mike,
>
> I see that IRQ routing that you set in Coreboot is different then that in UEFI bios.
> I recommend you first try to match them.
> Required data is already available in the dump you took.
>
> Also this link can be of help:
> https://gist.github.com/mcastelino/4acda7c2407f1c51e68f3f994d8ffc98
>
> IRQ routing is mandatory for non-MSI capable devices so make sure you best match them with UEFI bios for now.
>
> There might be some other issues other than IRQ routing but you can focus on them later as they dont seem critical.
>
> Please let me know how it goes.
>
> Regards,
> Naresh G Solanki
>
> On Mon, Nov 9, 2020 at 7:43 PM Mike Banon <mikebdp2(a)gmail.com> wrote:
>>
>> Dear Naresh, please check the attached archive for these files (and
>> tell if there's anything else I need to show)
>>
>> On Thu, Nov 5, 2020 at 8:08 PM Naresh G. Solanki
>> <naresh.solanki.2011(a)gmail.com> wrote:
>> >
>> > Can you give following output with coreboot and OEM bios.
>> > lspci -vvvk
>> > dmesg
>> > cat /proc/interrupt
>> >
>> >
>> > On Thu, 5 Nov, 2020, 6:29 pm Mike Banon, <mikebdp2(a)gmail.com> wrote:
>> >>
>> >> Still need your help, friend
>> >>
>> >> On Sat, Oct 24, 2020 at 11:15 AM Mike Banon <mikebdp2(a)gmail.com> wrote:
>> >> >
>> >> > Although I found this article
>> >> > https://www.coreboot.org/Creating_Valid_IRQ_Tables , I'm not sure if
>> >> > it applies to mainboard_picr_data/_intr_data : considering a problem
>> >> > from my previous msg - where a copy-paste of old picr/intr data
>> >> > structures gave the bad results. Could you please clarify if this
>> >> > article is still valid for these new data structures? If not, how to
>> >> > get the correct values for mainboard_picr_data/_intr_data using Linux?
>> >> >
>> >> >
>> >> > On Tue, Oct 20, 2020 at 6:23 PM Mike Banon <mikebdp2(a)gmail.com> wrote:
>> >> > >
>> >> > > Dear friends, I'm trying to properly program the IRQ tables for Lenovo
>> >> > > G505S, because the old IRQ routing is bad and doesn't work for a
>> >> > > simple OS like Kolibri. Full details are in the comments under this
>> >> > > change:
>> >> > >
>> >> > > https://review.coreboot.org/c/coreboot/+/46587/
>> >> > >
>> >> > > When I used the old picr_data/intr_data values of G505S for the new
>> >> > > structures, I got only 1 IRQ working. However, with a copy-paste of
>> >> > > AM1I-A - surprisingly 12 IRQs and a laptop boots, but still some
>> >> > > problems. Please advise how to compose mainboard_picr_data/_intr_data
>> >> > > and also a intel_irq_routing_table, your help will be very much
>> >> > > appreciated.
>> >> > >
>> >> > > Best regards,
>> >> > > Mike Banon
>> >> _______________________________________________
>> >> coreboot mailing list -- coreboot(a)coreboot.org
>> >> To unsubscribe send an email to coreboot-leave(a)coreboot.org
>
>
>
> --
> Best regards,
> Naresh G. Solanki
3 years, 5 months
Re: No instructions for the Biostar AM1ML?
by Mike Banon
Hi there Nicholas,
Recently I've provided a lot of instructions for you at Biostar AM1ML
thread on Reddit. Below, for the archival purposes, is a repost from
https://www.reddit.com/r/coreboot/comments/u4ncpe/biostar_am1ml/ :
1) Biostar AM1ML seems to have a socket'ed DIP8 chip, so it is
possible to flash just by a USB CH341A (preferably with a green PCB)
to get it done. You also need a DIP8 or PLCC extraction tool, to be
able to safely remove a DIP8 chip from a socket without bending its'
pins. In addition, maybe order a USB extension cable for convenience.
There are also DIP8 test clips, but they are expensive compared to
SOIC8 ones - and, since the chip is socket'ed - are not essential. Any
cheapest DIP8 or PLCC extraction tool from AliExpress - still should
be good enough. Usually I'm using a PLCC one even for DIP8 chips,
slightly more convenient IMHO, but you can get both considering their
dirt cheap price.
2) It's quite easy to build a coreboot for AM1ML, also because it's
AMD so you don't need to extract / use any parts of your original BIOS
(like the people often need to do for their Intels). You could follow
use the instructions at Lenovo G505S hacking page
(http://dangerousprototypes.com/docs/Lenovo_G505S_hacking) : these
not-merged-yet patches can benefit any AMD, and although I don't
provide an example config for AM1ML, you can take an example config of
AM1I-A (very similar board from the same AMD family) as the base for
your own config.
3) You don't need to change anything in this ./csb_patcher.sh script
for your AM1ML board (well, unless you'd like to help me by improving
some code ;-) ). Just use a script as-is and reply N when it asks to
apply the G505S / A88XM-E / AM1I-A configs.
coreboot uses a hidden ./coreboot/.config file as a place for storing
the configuration, and "apply" in that context - means copying a
board's example config from ./coreboot/configs/filename to
./coreboot/.config
Each of the primary patches - either does a small improvement for you,
or no improvement but no harm too: i.e. there's no IRQ improvement for
your board in "AMD good irq" (if you'd like - do a similar one by
yourself). So you could reply Y to all the other patches.
After the launch of a script, you need to somehow get a good config
for your board and put to ./coreboot/.config . To produce a good
config for your AM1ML, I propose to do the following:
*) Look at this diff
(https://github.com/mikebdp2/temp_4friend/commit/cbc0885faa9b5a338153c44ba5e…)
between the default AM1I-A config VS my improved version, research
about these changed options and decide by yourself if you'd like to
add any of these changes on top of your default AM1ML config. To avoid
the error-prone manual text editing, open "make menuconfig" while at
./coreboot/ directory, figure out the menu location of any particular
config by pressing / key, then go there and enable it manually.
*) Also check this diff
(https://github.com/mikebdp2/temp_4friend/commit/3ddc6cc095ce19aba007fe4e874…)
between the default AM1ML config VS the latest known good AM1ML config
which has been "refreshed" by putting it into the coreboot directory,
running "make menuconfig" and saving the changes (some config options
appear, some disappear, etc.) and also review it.
In addition, for the working integrated graphics, you will need to get
the AtomBIOS blob. I provide some of these blobs by one of the
unofficial patches installed by a script above -
https://review.coreboot.org/c/coreboot/+/58748 - including
pci1002,9830.rom for the iGPU of Athlon 5370 on AM1I-A; but this
top-of-the-line CPU for AM1 socket is rare (many people only have
5350) and I don't know if "extracted_on_AM1I-A" AtomBIOS will be
compatible for your board since it may have different internal
configuration values. To get your own AtomBIOS, first of all update
your UEFI to the latest version - so that AtomBIOS may be also fresher
- and I recommend you to use a "Retrieval via Linux kernel" method;
there's also a more advanced "Ultimate" method described at my post
here (https://mail.coreboot.org/pipermail/coreboot/2017-July/084660.html)
but it's more time consuming and I hope you won't need it.
After getting the AtomBIOS rom, rename it to pciXXXX,YYYY.rom where
XXXX and YYYY are PCI vendor ID / device ID of your iGPU (could be
found with lspci -vvvnn), put to your ./coreboot/ directory and choose
the CONFIG_VGA_BIOS_ID="XXXX,YYYY" ,
CONFIG_VGA_BIOS_FILE="pciXXXX,YYYY.rom" in your config.
Then you could go ahead, build your coreboot, and maybe run
"./csb_patcher.sh flop" if you'd like to add some awesome floppy-based
OS which will be available as the SeaBIOS boot entries.
Advanced:
To improve the irqs for your AMD board, you may look at the source
code improvements I did for g505s / a88xm-e / am1i-a boards, and try
to do something similar for your am1ml by trial and error. Although
the sophisticated OS like Linux works fine even with the "bad irq
routing" (unless it is seriously messed up, in which case it will
freeze while booting), the floppy-based hobby OS like KolibriOS may
have a trouble accessing some peripheral devices (i.e. network card)
if you don't fix your IRQs. So, if you'd have some free time after
successfully coreboot'ing your board, you may try improving your IRQs.
And, if you do some unofficial patches (good IRQs, AtomBIOS ROM,
custom config, etc) after a review I may include them to my collection
above, for everyone's benefit and a speedy future coreboot builds for
AM1ML.
With the latest version of a proprietary UEFI is installed, run these
tools (getpir / mptable)
(https://review.coreboot.org/c/coreboot/+/48322) - their output is
partially wrong, but for a starting point it's better than nothing.
Then you copy-paste the "AMD good IRQs" code for i.e. AM1I-A which is
fam16h platform like your board (although I spent more time on G505S
fam15h so it could be higher quality) - and try to adjust it for your
board by trial and error.
> When do I know when I've got it right?
When a Linux is still able to boot fine (it freezes while booting if
seriously messed up), and KolibriOS correctly assigns the IRQs to your
PCI devices (you can check it in KolibriOS GUI utility available at
Control Panel) : so as result i.e. your network card is accessible to
Kolibri and you could browse the Internet or use IRCC for online
chatting (provided that an Ethernet driver is available for your
controller). Being able to do this - was my primary reason for
creating the "good IRQ" patches.
Hope this helps, if any questions I'll be glad to help you further ;-)
On Thu, Apr 21, 2022 at 12:56 PM Nicholas C. L. Ipsen via coreboot
<coreboot(a)coreboot.org> wrote:
>
> Hi everyone,
>
> I recently managed to find a Biostar AM1ML, primarily purchasing it because I thought it would be a good board for a router with coreboot to make it 100% open source. However, even though the board is listed as supported, I can find no flashing instructions anywhere.
>
> Does anyone on this mailing list have experience flashing this board? I don't need anyone to hold my hand, but I would appreciate knowing what flashing method works, at least. Would hate to fry the chip.
>
>
> --
> Nicholas C. L. Ipsen
> _______________________________________________
> coreboot mailing list -- coreboot(a)coreboot.org
> To unsubscribe send an email to coreboot-leave(a)coreboot.org
--
Best regards, Mike Banon
Open Source Community Manager of 3mdeb - https://3mdeb.com/
2 years