Patch set updated for serialice: 5d05c96 Add config option for LPC/PCI POST card

[Rudolf Marek]

Rudolf Marek ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1682

-gerrit

commit 5d05c964ee40c6d5e035332092c20ef796f451de
Author: Rudolf Marek <[e-mail]>
Date:   Sun Nov 11 15:59:24 2012 +0100

    Add config option for LPC/PCI POST card
    
    It turns out that first works POST card than serial port.
    Make it a nice Kconfig option and convert #if 0 existing
    code to use it.
    
    Change-Id: I38af84211d686484deabcec0002d7d261993e4d6
    Signed-off-by: Rudolf Marek <[e-mail]>
---
 SerialICE/Kconfig                    | 15 +++++++++++++
 SerialICE/mainboard/intel_d945gclf.c |  3 ++-
 SerialICE/mainboard/roda_rk886ex.c   |  5 +++--
 SerialICE/southbridge/amd-sbxxx.c    | 43 +++++++++++++++++++++++++++++++++++-
 SerialICE/southbridge/intel-ich7.c   |  4 +++-
 5 files changed, 65 insertions(+), 5 deletions(-)

diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index 38f3e03..32e2895 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -323,6 +323,21 @@ config EXPERIMENTAL
 	  We do not make any guarantees about anything that is marked
 	  as EXPERIMENTAL! You have been warned!
 
+choice
+	prompt "POST card"
+	default POST_NONE
+
+config POST_NONE
+	boolean "None"
+
+config POST_PCI
+	boolean "PCI POST card"
+
+config POST_LPC
+	boolean "LPC POST card"
+
+endchoice
+
 config EXPERT
 	bool "Expert mode"
 	help
diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c
index c78f3bc..85d4d82 100644
--- a/SerialICE/mainboard/intel_d945gclf.c
+++ b/SerialICE/mainboard/intel_d945gclf.c
@@ -18,6 +18,7 @@
  */
 
 /* This is a chipset init file for the Intel D945GCLF mainboard */
+#include "config.h"
 
 const char boardname[33]="Intel D945GCLF                  ";
 
@@ -35,7 +36,7 @@ static void southbridge_init(void)
 	// Set up RCBA
 	pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
 
-#if 0
+#if defined(CONFIG_POST_LPC)
 	// port80 writes go to LPC:
 	reg32 = RCBA32(GCS);
 	reg32 = reg32 & ~0x04;
diff --git a/SerialICE/mainboard/roda_rk886ex.c b/SerialICE/mainboard/roda_rk886ex.c
index e3e02c1..048f30d 100644
--- a/SerialICE/mainboard/roda_rk886ex.c
+++ b/SerialICE/mainboard/roda_rk886ex.c
@@ -20,6 +20,8 @@
 /*
  * This is an example chipset init file for the Roda RK886EX (Rocky 3+)
  */
+#include "config.h"
+
 const char boardname[33]="Roda RK886EX (Rocky III+)       ";
 
 /* Hardware specific functions */
@@ -36,12 +38,11 @@ static void southbridge_init(void)
 	// Set up RCBA
 	pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
 
-#if 0
+#if defined(CONFIG_POST_LPC)
 	// port80 writes go to LPC:
 	reg32 = RCBA32(GCS);
 	reg32 = reg32 & ~0x04;
 	RCBA32(GCS) = reg32;
-	outb(0x23, 0x80);
 #endif
 
 	// Set up SuperIO LPC forwards
diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c
index 86f1278..37dca92 100644
--- a/SerialICE/southbridge/amd-sbxxx.c
+++ b/SerialICE/southbridge/amd-sbxxx.c
@@ -23,6 +23,8 @@
  * o enables POST card (see #if 0)
  */
 
+#include "config.h"
+
 #define MMIO_NON_POSTED_START 0xfed00000
 #define MMIO_NON_POSTED_END   0xfedfffff
 #define SB_MMIO 0xFED80000
@@ -44,7 +46,7 @@ static void sbxxx_enable_48mhzout(void)
 
 static void southbridge_init(void)
 {
-	u16 reg16;
+	u8 reg8;
 	u32 reg32;
 
 	/* route FED00000 - FEDFFFFF as non-posted to SB */
@@ -65,4 +67,43 @@ static void southbridge_init(void)
 	/* Enable LPC decoding of 0x2e/0x2f, 0x4e/0x4f 0x3f8  */
 	pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6));
 	pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x48), (1 << 1) | (1 << 0));
+
+#if defined(CONFIG_POST_PCI)
+	/* Chip Control: Enable subtractive decoding */
+	reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x40));
+	reg8 |= 1 << 5;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x40), reg8);
+
+	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
+	reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4b));
+	reg8 |= 1 << 7;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4b), reg8);
+
+	/* The same IO Base and IO Limit here is meaningful because we set the
+	 * bridge to be subtractive. During early setup stage, we have to make
+	 * sure that data can go through port 0x80.
+	 */
+	/* IO Base: 0xf000 */
+	reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1c));
+	reg8 |= 0xf << 4;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1c), reg8);
+
+	/* IO Limit: 0xf000 */
+	reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1d));
+	reg8 |= 0xf << 4;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1d), reg8);
+
+	/* PCI Command: Enable IO response */
+	reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4));
+	reg8 |= 1 << 0;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4) , reg8);
+
+	reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 3, 0x4a));
+	reg8 &= ~(1 << 5);	/* disable lpc port 80 */
+	pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x4a), reg8);
+#elif defined(CONFIG_POST_LPC)
+	reg8 = pci_read_config8(PCI_ADDR(0, 0x14, 3, 0x4a));
+	reg8 |= (1 << 5);	/* enable lpc port 80 */
+	pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x4a), reg8);
+#endif
 }
diff --git a/SerialICE/southbridge/intel-ich7.c b/SerialICE/southbridge/intel-ich7.c
index 3688084..c58aca1 100644
--- a/SerialICE/southbridge/intel-ich7.c
+++ b/SerialICE/southbridge/intel-ich7.c
@@ -23,6 +23,8 @@
  * o the watchdog is turned off
  */
 
+#include "config.h"
+
 #define RCBA	0xfed1c000
 #define   GCS	0x3410
 #define RCBA32(x) *((volatile u32 *)(RCBA + x))
@@ -35,7 +37,7 @@ static void southbridge_init(void)
 	// Set up RCBA
 	pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
 
-#if 0
+#if defined(CONFIG_POST_LPC)
 	// port80 writes go to LPC:
 	reg32 = RCBA32(GCS);
 	reg32 = reg32 & ~0x04;