Idwer Vollering (vidwer@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2911
-gerrit
commit 3f2c7897a318d4ad6dec08f6817fc7fa4ece1f81 Author: Idwer Vollering vidwer@gmail.com Date: Tue Mar 26 01:08:46 2013 +0100
SerialICE: move superio defines
Move local superio defines to a header file.
Change-Id: Ic7a55a2b2848bc7f647e73b97f5cae4836c0e3c1 Signed-off-by: Idwer Vollering vidwer@gmail.com --- SerialICE/mainboard/amd_serengeti-cheetah.c | 17 +++++++------- SerialICE/mainboard/aopen_dxpl-plus.c | 26 ++++++++++----------- SerialICE/mainboard/asrock_775i65g.c | 18 +++++++-------- SerialICE/mainboard/asrock_939a785gmh.c | 16 ++++++------- SerialICE/mainboard/asrock_p4i65gv.c | 18 +++++++-------- SerialICE/mainboard/asus_f2a85-m.c | 20 ++++++++--------- SerialICE/mainboard/asus_k8v-x.c | 20 ++++++++--------- SerialICE/mainboard/asus_m2v-mx_se.c | 20 ++++++++--------- SerialICE/mainboard/asus_m4a77td-pro.c | 20 ++++++++--------- SerialICE/mainboard/asus_p4p800-vm.c | 18 +++++++-------- SerialICE/mainboard/commell_lv_672.c | 20 ++++++++--------- SerialICE/mainboard/hp_dl165_g6.c | 18 +++++++-------- SerialICE/mainboard/intel_d845gbv2.c | 16 ++++++------- SerialICE/mainboard/msi_ms6178.c | 16 ++++++------- SerialICE/mainboard/msi_ms7133.c | 2 +- SerialICE/mainboard/televideo_tc7010.c | 35 +++++++++++++++-------------- SerialICE/mainboard/tyan_s2892.c | 17 +++++++------- SerialICE/mainboard/tyan_s2895.c | 5 ++--- SerialICE/mainboard/tyan_s2912.c | 17 +++++++------- SerialICE/mainboard/via_epia_m850.c | 14 ++++++------ SerialICE/superio.h | 6 +++++ 21 files changed, 180 insertions(+), 179 deletions(-)
diff --git a/SerialICE/mainboard/amd_serengeti-cheetah.c b/SerialICE/mainboard/amd_serengeti-cheetah.c index bd35711..933e30e 100644 --- a/SerialICE/mainboard/amd_serengeti-cheetah.c +++ b/SerialICE/mainboard/amd_serengeti-cheetah.c @@ -20,22 +20,21 @@
const char boardname[] = "AMD SERENGETI CHEETAH";
-#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h"
static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/aopen_dxpl-plus.c b/SerialICE/mainboard/aopen_dxpl-plus.c index 44cdb34..2f1d901 100644 --- a/SerialICE/mainboard/aopen_dxpl-plus.c +++ b/SerialICE/mainboard/aopen_dxpl-plus.c @@ -19,7 +19,7 @@
const char boardname[] = "AOpen DXPL Plus";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
/* Hardware specific functions */ static void southbridge_init(void) @@ -42,24 +42,24 @@ static void southbridge_init(void)
static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh);
- pnp_set_logical_device(SUPERIO_CONFIG_PORT, 4); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 4); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
#if 0 /* Must route GPIO to UART2 before enabling this */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); #endif
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_775i65g.c b/SerialICE/mainboard/asrock_775i65g.c index 27d1c36..9870e45 100644 --- a/SerialICE/mainboard/asrock_775i65g.c +++ b/SerialICE/mainboard/asrock_775i65g.c @@ -19,7 +19,7 @@
const char boardname[] = "ASRock 775i65G";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
/* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_939a785gmh.c b/SerialICE/mainboard/asrock_939a785gmh.c index d44a50b..0c92a60 100644 --- a/SerialICE/mainboard/asrock_939a785gmh.c +++ b/SerialICE/mainboard/asrock_939a785gmh.c @@ -20,20 +20,20 @@
const char boardname[] = "Asrock 939a785gmh";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/asrock_p4i65gv.c b/SerialICE/mainboard/asrock_p4i65gv.c index ccb40ec..8cffca0 100644 --- a/SerialICE/mainboard/asrock_p4i65gv.c +++ b/SerialICE/mainboard/asrock_p4i65gv.c @@ -19,7 +19,7 @@
const char boardname[] = "ASRock P4i65GV";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
/* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627HG */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc0); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c index 53a75b6..af1b14e 100644 --- a/SerialICE/mainboard/asus_f2a85-m.c +++ b/SerialICE/mainboard/asus_f2a85-m.c @@ -20,25 +20,25 @@
const char boardname[] = "Asus F2A85-M";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
static void superio_init(void) { u8 byte; - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh);
/* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); }
diff --git a/SerialICE/mainboard/asus_k8v-x.c b/SerialICE/mainboard/asus_k8v-x.c index df010c9..7e3ee5f 100644 --- a/SerialICE/mainboard/asus_k8v-x.c +++ b/SerialICE/mainboard/asus_k8v-x.c @@ -20,24 +20,24 @@
const char boardname[] = "ASUS K8V-X";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh);
/* Disable the watchdog. */ -// pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); -// pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); +// pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); +// pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m2v-mx_se.c b/SerialICE/mainboard/asus_m2v-mx_se.c index ab2a289..7d98739 100644 --- a/SerialICE/mainboard/asus_m2v-mx_se.c +++ b/SerialICE/mainboard/asus_m2v-mx_se.c @@ -20,24 +20,24 @@
const char boardname[] = "ASUS M2V-MX SE";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh);
/* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_m4a77td-pro.c b/SerialICE/mainboard/asus_m4a77td-pro.c index b41c97d..2c9ab34 100644 --- a/SerialICE/mainboard/asus_m4a77td-pro.c +++ b/SerialICE/mainboard/asus_m4a77td-pro.c @@ -21,24 +21,24 @@
const char boardname[] = "ASUS M4A77TD-PRO";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
static void superio_init(void) { - pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh);
/* Disable the watchdog. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 7); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x72, 0x00);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/asus_p4p800-vm.c b/SerialICE/mainboard/asus_p4p800-vm.c index 9208870..8a59f7d 100644 --- a/SerialICE/mainboard/asus_p4p800-vm.c +++ b/SerialICE/mainboard/asus_p4p800-vm.c @@ -19,7 +19,7 @@
const char boardname[] = "ASUS P4P800-VM";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
/* Hardware specific functions */ static void mainboard_set_ich5(void) @@ -39,15 +39,15 @@ static void mainboard_set_ich5(void) /* Winbond W83627THF */ static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); /* Set the clock to 48MHz */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0x42); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0x42); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/commell_lv_672.c b/SerialICE/mainboard/commell_lv_672.c index 047bc9f..0c8d6cd 100644 --- a/SerialICE/mainboard/commell_lv_672.c +++ b/SerialICE/mainboard/commell_lv_672.c @@ -19,7 +19,7 @@
const char boardname[] = "Commell LV-672";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
/* Hardware specific functions */ static void southbridge_init(void) @@ -49,19 +49,19 @@ static void southbridge_init(void)
static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh);
/* Settings for Winbond W83627THF/THG */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc2); /* Select oscillator */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc2); /* Select oscillator */
- pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/hp_dl165_g6.c b/SerialICE/mainboard/hp_dl165_g6.c index 745bf26..f1f70fe 100644 --- a/SerialICE/mainboard/hp_dl165_g6.c +++ b/SerialICE/mainboard/hp_dl165_g6.c @@ -21,9 +21,7 @@
const char boardname[] = "HP DL165 G6";
-#define SCH4307_CONFIG_PORT 0x162e -#define SUPERIO_CONFIG_PORT 0x2e -#define SUPERIO_SP1 2 +#include "superio.h"
static void superio_init(void) { @@ -45,13 +43,13 @@ static void superio_init(void) pnp_exit_ext_func_mode(SCH4307_CONFIG_PORT);
/* Enable the serial port. */ - outb(0x5a, SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, SUPERIO_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - outb(0xa5, SUPERIO_CONFIG_PORT); + outb(0x5a, SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, SUPERIO_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + outb(0xa5, SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/intel_d845gbv2.c b/SerialICE/mainboard/intel_d845gbv2.c index 6cbd703..aaf1cf8 100644 --- a/SerialICE/mainboard/intel_d845gbv2.c +++ b/SerialICE/mainboard/intel_d845gbv2.c @@ -19,7 +19,7 @@
const char boardname[] = "Intel D845GBV2";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
/* Hardware specific functions */ static void southbridge_init(void) @@ -39,16 +39,16 @@ static void southbridge_init(void)
static void superio_init(void) { - pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT_2eh);
/* Settings for LPC47M172 with LD_NUM = 0. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 3); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 3); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/msi_ms6178.c b/SerialICE/mainboard/msi_ms6178.c index fd4af8f..639994f 100644 --- a/SerialICE/mainboard/msi_ms6178.c +++ b/SerialICE/mainboard/msi_ms6178.c @@ -30,7 +30,7 @@ const char boardname[] = "MSI MS6178"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08)
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
static void southbridge_init(void) { @@ -53,16 +53,16 @@ static void southbridge_init(void)
static void superio_init(void) { - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh);
/* Set CLKSEL=1 to select 48 MHz (otherwise serial won't work). */ - pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc4); + pnp_write_register(SUPERIO_CONFIG_PORT_2eh, 0x24, 0xc4);
- pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 2); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
pnp_exit_ext_func_mode(0x2e); } diff --git a/SerialICE/mainboard/msi_ms7133.c b/SerialICE/mainboard/msi_ms7133.c index 1248f78..784a2b7 100644 --- a/SerialICE/mainboard/msi_ms7133.c +++ b/SerialICE/mainboard/msi_ms7133.c @@ -31,7 +31,7 @@ const char boardname[] = "MSI MS7133"; #define TCO2_STS (TCOBASE + 0x06) #define TCO1_CNT (TCOBASE + 0x08)
-#define SUPERIO_CONFIG_PORT 0x4e +#include "superio.h"
static void southbridge_init(void) { diff --git a/SerialICE/mainboard/televideo_tc7010.c b/SerialICE/mainboard/televideo_tc7010.c index a915387..5c92437 100644 --- a/SerialICE/mainboard/televideo_tc7010.c +++ b/SerialICE/mainboard/televideo_tc7010.c @@ -19,16 +19,17 @@
const char boardname[] = "Televideo TC7010";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h" + #define PM_BASE 0xe8
static void superio_init(void) { /* Set base address of power management unit */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, PM_BASE); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, PM_BASE); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
/* Use on-chip clock multiplier */ outb(0x03, PM_BASE); @@ -38,20 +39,20 @@ static void superio_init(void) while (!(inb(PM_BASE + 1) & 0x80)) ;
/* Enable the serial ports. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 6); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 6); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
/* Set LDN 5 UART Mode */ - outb(0x21, SUPERIO_CONFIG_PORT); - outb(inb(SUPERIO_CONFIG_PORT + 1) | (1 << 3), SUPERIO_CONFIG_PORT + 1); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + outb(0x21, SUPERIO_CONFIG_PORT_2eh); + outb(inb(SUPERIO_CONFIG_PORT_2eh + 1) | (1 << 3), SUPERIO_CONFIG_PORT_2eh + 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2892.c b/SerialICE/mainboard/tyan_s2892.c index 043ebf7..bb4427a 100644 --- a/SerialICE/mainboard/tyan_s2892.c +++ b/SerialICE/mainboard/tyan_s2892.c @@ -20,8 +20,7 @@
const char boardname[] = "Tyan S2892";
-#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h"
static void sio_setup(void) { @@ -41,16 +40,16 @@ static void sio_setup(void) static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, CONFIG_SERIAL_PORT); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, CONFIG_SERIAL_PORT); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/tyan_s2895.c b/SerialICE/mainboard/tyan_s2895.c index 8606bbe..edc4920 100644 --- a/SerialICE/mainboard/tyan_s2895.c +++ b/SerialICE/mainboard/tyan_s2895.c @@ -20,7 +20,6 @@
const char boardname[] = "Tyan S2895";
-#define SUPERIO_CONFIG_PORT 0x2e #define SUPERIO_GPIO_IO_BASE 0x400
#define LPC47B397_SP1 4 /* Com1 */ @@ -68,7 +67,7 @@ static void superio_init(void) dword |= (1<<16); pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword);
- smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); @@ -77,7 +76,7 @@ static void superio_init(void) static void chipset_init(void) { superio_init(); - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_SP1, CONFIG_SERIAL_PORT); + smsc_enable_serial(SUPERIO_CONFIG_PORT_2eh, LPC47B397_SP1, CONFIG_SERIAL_PORT); __asm__ __volatile__("\ jmp skip\n\ .align 128\n\ diff --git a/SerialICE/mainboard/tyan_s2912.c b/SerialICE/mainboard/tyan_s2912.c index 77b5d29..9d74a18 100644 --- a/SerialICE/mainboard/tyan_s2912.c +++ b/SerialICE/mainboard/tyan_s2912.c @@ -20,22 +20,21 @@
const char boardname[] = "Tyan S2912";
-#define SUPERIO_CONFIG_PORT 0x2e -#define W83627HF_SP1 2 +#include "superio.h"
static void superio_init(void) { int i; - pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT_2eh);
/* Enable the serial port. */ - pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); - pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT_2eh, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1);
- pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/mainboard/via_epia_m850.c b/SerialICE/mainboard/via_epia_m850.c index 55c2574..89c1335 100644 --- a/SerialICE/mainboard/via_epia_m850.c +++ b/SerialICE/mainboard/via_epia_m850.c @@ -19,7 +19,7 @@
const char boardname[] = "VIA EPIA M-850";
-#define SUPERIO_CONFIG_PORT 0x2e +#include "superio.h"
static inline void pnp_enter_conf_state(u16 port) { @@ -34,12 +34,12 @@ static inline void pnp_exit_conf_state(u16 port)
static void superio_init(void) { - pnp_enter_conf_state(SUPERIO_CONFIG_PORT); - pnp_set_logical_device(SUPERIO_CONFIG_PORT, 0); - pnp_set_enable(SUPERIO_CONFIG_PORT, 0); - pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x03f8); - pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - pnp_exit_conf_state(SUPERIO_CONFIG_PORT); + pnp_enter_conf_state(SUPERIO_CONFIG_PORT_2eh); + pnp_set_logical_device(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT_2eh, 0x03f8); + pnp_set_enable(SUPERIO_CONFIG_PORT_2eh, 1); + pnp_exit_conf_state(SUPERIO_CONFIG_PORT_2eh); }
static void chipset_init(void) diff --git a/SerialICE/superio.h b/SerialICE/superio.h new file mode 100644 index 0000000..9edca27 --- /dev/null +++ b/SerialICE/superio.h @@ -0,0 +1,6 @@ +#define SUPERIO_CONFIG_PORT_2eh 0x2e +#define SUPERIO_CONFIG_PORT_4eh 0x4e +#define W83627HF_SP1 2 + +#define SCH4307_CONFIG_PORT 0x162e +#define SUPERIO_SP1 2