Stefan Tauner (stefan.tauner@gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1578
-gerrit
commit 9f23af0cea64e81707d13926b750faeb03a4fd1c Author: Stefan Tauner stefan.tauner@gmx.at Date: Mon Mar 25 20:45:39 2013 +0100
Add support for Intel D945GNT
This is based on the patch from Beata dalHagen, see http://serialice.com/pipermail/serialice/2012-May/000372.html This version has only been compile tested. It seems like we should use kconfig more, but i don't know this stuff good enough yet. Still better than copying the whole file :)
Change-Id: Ia4058d0f73f8357b97d7c0fe1868d9a289c4e2f7 Signed-off-by: Stefan Tauner stefan.tauner@gmx.at --- SerialICE/Kconfig | 5 +- SerialICE/mainboard/intel_d945gclf.c | 92 ------------------------------- SerialICE/mainboard/intel_d94x.c | 102 +++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+), 93 deletions(-)
diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 3d5fa9c..fc56696 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -42,6 +42,9 @@ config BOARD_RODA_RK886EX config BOARD_INTEL_D945GCLF bool "Intel D945GCLF"
+config BOARD_INTEL_D945GNT + bool "Intel D945GNT" + config BOARD_DELL_S1850 bool "Dell PowerEdge S1850"
@@ -132,7 +135,7 @@ config BOARD_INIT default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M default "roda_rk886ex.c" if BOARD_RODA_RK886EX - default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF + default "intel_d94x.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT default "dell_s1850.c" if BOARD_DELL_S1850 default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c deleted file mode 100644 index 85d4d82..0000000 --- a/SerialICE/mainboard/intel_d945gclf.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * SerialICE - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is a chipset init file for the Intel D945GCLF mainboard */ -#include "config.h" - -const char boardname[33]="Intel D945GCLF "; - -/* Hardware specific functions */ - -#define RCBA 0xfed1c000 -#define GCS 0x3410 -#define RCBA32(x) *((volatile u32 *)(RCBA + x)) - -static void southbridge_init(void) -{ - u16 reg16; - u32 reg32; - - // Set up RCBA - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); - -#if defined(CONFIG_POST_LPC) - // port80 writes go to LPC: - reg32 = RCBA32(GCS); - reg32 = reg32 & ~0x04; - RCBA32(GCS) = reg32; - outb(0x23, 0x80); -#endif - - // Enable Serial IRQ - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); - // Set COM1 decode range - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); - // Enable COM1 - pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d); - // Enable SIO PM Events at 0x680 - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x007c0681); - - // Disable watchdog -#define PMBASE 0x500 -#define TCOBASE (PMBASE + 0x60) - pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); - pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); - reg16 = inw(TCOBASE + 0x08); - reg16 |= (1 << 11); - outw(reg16, TCOBASE + 0x08); - outw(0x0008, TCOBASE + 0x04); - outw(0x0002, TCOBASE + 0x06); -} - -static void superio_init(void) -{ - pnp_enter_ext_func_mode_alt(0x2e); - - pnp_set_logical_device(0x2e, 4); // COM-A - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x3f8); - pnp_set_irq0(0x2e, 4); - pnp_set_enable(0x2e, 1); - - pnp_set_logical_device(0x2e, 10); // PM - pnp_set_enable(0x2e, 0); - pnp_set_iobase0(0x2e, 0x680); - pnp_set_irq0(0x2e, 3); - pnp_set_enable(0x2e, 1); - - pnp_exit_ext_func_mode(0x2e); -} - -static void chipset_init(void) -{ - southbridge_init(); - superio_init(); -} - diff --git a/SerialICE/mainboard/intel_d94x.c b/SerialICE/mainboard/intel_d94x.c new file mode 100644 index 0000000..f3fd0ea --- /dev/null +++ b/SerialICE/mainboard/intel_d94x.c @@ -0,0 +1,102 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is a chipset init file for the Intel D945GCLF/D945GNT mainboards */ +#include "config.h" + +#if defined(CONFIG_BOARD_INTEL_D945GCLF) +const char boardname[33]="Intel D945GCLF "; +#elif defined(CONFIG_BOARD_INTEL_D945GNT) +const char boardname[33]="Intel D945GNT "; +#else +#error "Unsupported board" +#endif + +/* Hardware specific functions */ + +#define RCBA 0xfed1c000 +#define GCS 0x3410 +#define RCBA32(x) *((volatile u32 *)(RCBA + x)) + +static void southbridge_init(void) +{ + u16 reg16; + u32 reg32; + + // Set up RCBA + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1); + +#if defined(CONFIG_POST_LPC) + // port80 writes go to LPC: + reg32 = RCBA32(GCS); + reg32 = reg32 & ~0x04; + RCBA32(GCS) = reg32; + outb(0x23, 0x80); +#endif + + // Enable Serial IRQ + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0); + // Set COM1 decode range + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010); + // Enable COM1 + pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d); + // Enable SIO PM Events at 0x680 + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x007c0681); + + // Disable watchdog +#define PMBASE 0x500 +#define TCOBASE (PMBASE + 0x60) + pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1); + pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80); + reg16 = inw(TCOBASE + 0x08); + reg16 |= (1 << 11); + outw(reg16, TCOBASE + 0x08); + outw(0x0008, TCOBASE + 0x04); + outw(0x0002, TCOBASE + 0x06); +} + +static void superio_init(u8 cfg_port, u8 com_port, u8 pm) +{ + pnp_enter_ext_func_mode_alt(cfg_port); + + pnp_set_logical_device(cfg_port, com_port); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x3f8); + pnp_set_irq0(cfg_port, 4); + pnp_set_enable(cfg_port, 1); + + pnp_set_logical_device(cfg_port, pm); + pnp_set_enable(cfg_port, 0); + pnp_set_iobase0(cfg_port, 0x680); + pnp_set_irq0(cfg_port, 3); + pnp_set_enable(cfg_port, 1); + + pnp_exit_ext_func_mode(cfg_port); +} + +static void chipset_init(void) +{ + southbridge_init(); +#if defined(CONFIG_BOARD_INTEL_D945GCLF) + superio_init(0x2e, 4, 10); +#elif defined(CONFIG_BOARD_INTEL_D945GNT) + superio_init(0x2e, 3, 4); // LPC47M182 +#endif +} +